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[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_state_inlines.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300, void* state)
39 {
40 struct r300_blend_state* blend = (struct r300_blend_state*)state;
41 struct pipe_framebuffer_state* fb =
42 (struct pipe_framebuffer_state*)r300->fb_state.state;
43 CS_LOCALS(r300);
44
45 BEGIN_CS(8);
46 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
47 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
48 if (fb->nr_cbufs) {
49 OUT_CS(blend->blend_control);
50 OUT_CS(blend->alpha_blend_control);
51 OUT_CS(blend->color_channel_mask);
52 } else {
53 OUT_CS(0);
54 OUT_CS(0);
55 OUT_CS(0);
56 /* XXX also disable fastfill here once it's supported */
57 }
58 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
59 END_CS;
60 }
61
62 void r300_emit_blend_color_state(struct r300_context* r300, void* state)
63 {
64 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
65 struct r300_screen* r300screen = r300_screen(r300->context.screen);
66 CS_LOCALS(r300);
67
68 if (r300screen->caps->is_r500) {
69 BEGIN_CS(3);
70 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
71 OUT_CS(bc->blend_color_red_alpha);
72 OUT_CS(bc->blend_color_green_blue);
73 END_CS;
74 } else {
75 BEGIN_CS(2);
76 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
77 END_CS;
78 }
79 }
80
81 void r300_emit_clip_state(struct r300_context* r300, void* state)
82 {
83 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
84 int i;
85 struct r300_screen* r300screen = r300_screen(r300->context.screen);
86 CS_LOCALS(r300);
87
88 if (r300screen->caps->has_tcl) {
89 BEGIN_CS(5 + (6 * 4));
90 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
91 (r300screen->caps->is_r500 ?
92 R500_PVS_UCP_START : R300_PVS_UCP_START));
93 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
94 for (i = 0; i < 6; i++) {
95 OUT_CS_32F(clip->ucp[i][0]);
96 OUT_CS_32F(clip->ucp[i][1]);
97 OUT_CS_32F(clip->ucp[i][2]);
98 OUT_CS_32F(clip->ucp[i][3]);
99 }
100 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
101 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
102 END_CS;
103 } else {
104 BEGIN_CS(2);
105 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
106 END_CS;
107 }
108
109 }
110
111 void r300_emit_dsa_state(struct r300_context* r300, void* state)
112 {
113 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
114 struct r300_screen* r300screen = r300_screen(r300->context.screen);
115 struct pipe_framebuffer_state* fb =
116 (struct pipe_framebuffer_state*)r300->fb_state.state;
117 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
118 CS_LOCALS(r300);
119
120 BEGIN_CS(r300screen->caps->is_r500 ? 8 : 6);
121 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
122 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
123
124 if (fb->zsbuf) {
125 OUT_CS(dsa->z_buffer_control);
126 OUT_CS(dsa->z_stencil_control);
127 } else {
128 OUT_CS(0);
129 OUT_CS(0);
130 }
131
132 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
133
134 if (r300screen->caps->is_r500) {
135 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
136 }
137 END_CS;
138 }
139
140 static const float * get_shader_constant(
141 struct r300_context * r300,
142 struct rc_constant * constant,
143 struct r300_constant_buffer * externals)
144 {
145 struct r300_viewport_state* viewport =
146 (struct r300_viewport_state*)r300->viewport_state.state;
147 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
148 struct pipe_texture *tex;
149
150 switch(constant->Type) {
151 case RC_CONSTANT_EXTERNAL:
152 return externals->constants[constant->u.External];
153
154 case RC_CONSTANT_IMMEDIATE:
155 return constant->u.Immediate;
156
157 case RC_CONSTANT_STATE:
158 switch (constant->u.State[0]) {
159 /* Factor for converting rectangle coords to
160 * normalized coords. Should only show up on non-r500. */
161 case RC_STATE_R300_TEXRECT_FACTOR:
162 tex = &r300->textures[constant->u.State[1]]->tex;
163 vec[0] = 1.0 / tex->width0;
164 vec[1] = 1.0 / tex->height0;
165 break;
166
167 /* Texture compare-fail value. Shouldn't ever show up, but if
168 * it does, we'll be ready. */
169 case RC_STATE_SHADOW_AMBIENT:
170 vec[3] = 0;
171 break;
172
173 case RC_STATE_R300_VIEWPORT_SCALE:
174 if (r300->tcl_bypass) {
175 vec[0] = 1;
176 vec[1] = 1;
177 vec[2] = 1;
178 } else {
179 vec[0] = viewport->xscale;
180 vec[1] = viewport->yscale;
181 vec[2] = viewport->zscale;
182 }
183 break;
184
185 case RC_STATE_R300_VIEWPORT_OFFSET:
186 if (!r300->tcl_bypass) {
187 vec[0] = viewport->xoffset;
188 vec[1] = viewport->yoffset;
189 vec[2] = viewport->zoffset;
190 }
191 break;
192
193 default:
194 debug_printf("r300: Implementation error: "
195 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
196 }
197 break;
198
199 default:
200 debug_printf("r300: Implementation error: "
201 "Unhandled constant type %d\n", constant->Type);
202 }
203
204 /* This should either be (0, 0, 0, 1), which should be a relatively safe
205 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
206 * state factors. */
207 return vec;
208 }
209
210 /* Convert a normal single-precision float into the 7.16 format
211 * used by the R300 fragment shader.
212 */
213 static uint32_t pack_float24(float f)
214 {
215 union {
216 float fl;
217 uint32_t u;
218 } u;
219 float mantissa;
220 int exponent;
221 uint32_t float24 = 0;
222
223 if (f == 0.0)
224 return 0;
225
226 u.fl = f;
227
228 mantissa = frexpf(f, &exponent);
229
230 /* Handle -ve */
231 if (mantissa < 0) {
232 float24 |= (1 << 23);
233 mantissa = mantissa * -1.0;
234 }
235 /* Handle exponent, bias of 63 */
236 exponent += 62;
237 float24 |= (exponent << 16);
238 /* Kill 7 LSB of mantissa */
239 float24 |= (u.u & 0x7FFFFF) >> 7;
240
241 return float24;
242 }
243
244 void r300_emit_fragment_program_code(struct r300_context* r300,
245 struct rX00_fragment_program_code* generic_code)
246 {
247 struct r300_fragment_program_code * code = &generic_code->code.r300;
248 int i;
249 CS_LOCALS(r300);
250
251 BEGIN_CS(15 +
252 code->alu.length * 4 +
253 (code->tex.length ? (1 + code->tex.length) : 0));
254
255 OUT_CS_REG(R300_US_CONFIG, code->config);
256 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
257 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
258
259 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
260 for(i = 0; i < 4; ++i)
261 OUT_CS(code->code_addr[i]);
262
263 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
264 for (i = 0; i < code->alu.length; i++)
265 OUT_CS(code->alu.inst[i].rgb_inst);
266
267 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
268 for (i = 0; i < code->alu.length; i++)
269 OUT_CS(code->alu.inst[i].rgb_addr);
270
271 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
272 for (i = 0; i < code->alu.length; i++)
273 OUT_CS(code->alu.inst[i].alpha_inst);
274
275 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
276 for (i = 0; i < code->alu.length; i++)
277 OUT_CS(code->alu.inst[i].alpha_addr);
278
279 if (code->tex.length) {
280 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
281 for(i = 0; i < code->tex.length; ++i)
282 OUT_CS(code->tex.inst[i]);
283 }
284
285 END_CS;
286 }
287
288 void r300_emit_fs_constant_buffer(struct r300_context* r300,
289 struct rc_constant_list* constants)
290 {
291 int i;
292 CS_LOCALS(r300);
293
294 if (constants->Count == 0)
295 return;
296
297 BEGIN_CS(constants->Count * 4 + 1);
298 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
299 for(i = 0; i < constants->Count; ++i) {
300 const float * data = get_shader_constant(r300,
301 &constants->Constants[i],
302 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
303 OUT_CS(pack_float24(data[0]));
304 OUT_CS(pack_float24(data[1]));
305 OUT_CS(pack_float24(data[2]));
306 OUT_CS(pack_float24(data[3]));
307 }
308 END_CS;
309 }
310
311 static void r300_emit_fragment_depth_config(struct r300_context* r300,
312 struct r300_fragment_shader* fs)
313 {
314 CS_LOCALS(r300);
315
316 BEGIN_CS(4);
317 if (r300_fragment_shader_writes_depth(fs)) {
318 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
319 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
320 } else {
321 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
322 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
323 }
324 END_CS;
325 }
326
327 void r500_emit_fragment_program_code(struct r300_context* r300,
328 struct rX00_fragment_program_code* generic_code)
329 {
330 struct r500_fragment_program_code * code = &generic_code->code.r500;
331 int i;
332 CS_LOCALS(r300);
333
334 BEGIN_CS(13 +
335 ((code->inst_end + 1) * 6));
336 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
337 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
338 OUT_CS_REG(R500_US_CODE_RANGE,
339 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
340 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
341 OUT_CS_REG(R500_US_CODE_ADDR,
342 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
343
344 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
345 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
346 for (i = 0; i <= code->inst_end; i++) {
347 OUT_CS(code->inst[i].inst0);
348 OUT_CS(code->inst[i].inst1);
349 OUT_CS(code->inst[i].inst2);
350 OUT_CS(code->inst[i].inst3);
351 OUT_CS(code->inst[i].inst4);
352 OUT_CS(code->inst[i].inst5);
353 }
354
355 END_CS;
356 }
357
358 void r500_emit_fs_constant_buffer(struct r300_context* r300,
359 struct rc_constant_list* constants)
360 {
361 int i;
362 CS_LOCALS(r300);
363
364 if (constants->Count == 0)
365 return;
366
367 BEGIN_CS(constants->Count * 4 + 3);
368 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
369 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
370 for (i = 0; i < constants->Count; i++) {
371 const float * data = get_shader_constant(r300,
372 &constants->Constants[i],
373 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
374 OUT_CS_32F(data[0]);
375 OUT_CS_32F(data[1]);
376 OUT_CS_32F(data[2]);
377 OUT_CS_32F(data[3]);
378 }
379 END_CS;
380 }
381
382 void r300_emit_fb_state(struct r300_context* r300, void* state)
383 {
384 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
385 struct r300_screen* r300screen = r300_screen(r300->context.screen);
386 struct r300_texture* tex;
387 struct pipe_surface* surf;
388 int i;
389 CS_LOCALS(r300);
390
391 BEGIN_CS((10 * fb->nr_cbufs) + (fb->zsbuf ? 10 : 0) + 6);
392
393 /* Flush and free renderbuffer caches. */
394 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
395 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
396 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
397 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
398 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
399 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
400
401 /* Set the number of colorbuffers. */
402 if (fb->nr_cbufs > 1) {
403 if (r300screen->caps->is_r500) {
404 OUT_CS_REG(R300_RB3D_CCTL,
405 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
406 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
407 } else {
408 OUT_CS_REG(R300_RB3D_CCTL,
409 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
410 }
411 } else {
412 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
413 }
414
415 /* Set up colorbuffers. */
416 for (i = 0; i < fb->nr_cbufs; i++) {
417 surf = fb->cbufs[i];
418 tex = (struct r300_texture*)surf->texture;
419 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
420
421 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
422 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
423
424 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
425 OUT_CS_RELOC(tex->buffer, tex->fb_state.colorpitch[surf->level],
426 0, RADEON_GEM_DOMAIN_VRAM, 0);
427
428 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
429 }
430
431 /* Set up a zbuffer. */
432 if (fb->zsbuf) {
433 surf = fb->zsbuf;
434 tex = (struct r300_texture*)surf->texture;
435 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
436
437 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
438 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
439
440 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
441
442 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
443 OUT_CS_RELOC(tex->buffer, tex->fb_state.depthpitch[surf->level],
444 0, RADEON_GEM_DOMAIN_VRAM, 0);
445 }
446
447 END_CS;
448 }
449
450 static void r300_emit_query_start(struct r300_context *r300)
451 {
452 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
453 struct r300_query *query = r300->query_current;
454 CS_LOCALS(r300);
455
456 if (!query)
457 return;
458
459 BEGIN_CS(4);
460 if (caps->family == CHIP_FAMILY_RV530) {
461 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
462 } else {
463 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
464 }
465 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
466 END_CS;
467 query->begin_emitted = TRUE;
468 }
469
470
471 static void r300_emit_query_finish(struct r300_context *r300,
472 struct r300_query *query)
473 {
474 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
475 CS_LOCALS(r300);
476
477 assert(caps->num_frag_pipes);
478
479 BEGIN_CS(6 * caps->num_frag_pipes + 2);
480 /* I'm not so sure I like this switch, but it's hard to be elegant
481 * when there's so many special cases...
482 *
483 * So here's the basic idea. For each pipe, enable writes to it only,
484 * then put out the relocation for ZPASS_ADDR, taking into account a
485 * 4-byte offset for each pipe. RV380 and older are special; they have
486 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
487 * so there's a chipset cap for that. */
488 switch (caps->num_frag_pipes) {
489 case 4:
490 /* pipe 3 only */
491 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
492 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
493 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
494 0, RADEON_GEM_DOMAIN_GTT, 0);
495 case 3:
496 /* pipe 2 only */
497 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
498 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
499 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
500 0, RADEON_GEM_DOMAIN_GTT, 0);
501 case 2:
502 /* pipe 1 only */
503 /* As mentioned above, accomodate RV380 and older. */
504 OUT_CS_REG(R300_SU_REG_DEST,
505 1 << (caps->high_second_pipe ? 3 : 1));
506 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
507 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
508 0, RADEON_GEM_DOMAIN_GTT, 0);
509 case 1:
510 /* pipe 0 only */
511 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
512 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
513 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
514 0, RADEON_GEM_DOMAIN_GTT, 0);
515 break;
516 default:
517 debug_printf("r300: Implementation error: Chipset reports %d"
518 " pixel pipes!\n", caps->num_frag_pipes);
519 assert(0);
520 }
521
522 /* And, finally, reset it to normal... */
523 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
524 END_CS;
525 }
526
527 static void rv530_emit_query_single(struct r300_context *r300,
528 struct r300_query *query)
529 {
530 CS_LOCALS(r300);
531
532 BEGIN_CS(8);
533 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
534 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
535 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
536 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
537 END_CS;
538 }
539
540 static void rv530_emit_query_double(struct r300_context *r300,
541 struct r300_query *query)
542 {
543 CS_LOCALS(r300);
544
545 BEGIN_CS(14);
546 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
547 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
548 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
549 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
550 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
551 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
552 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
553 END_CS;
554 }
555
556 void r300_emit_query_end(struct r300_context* r300)
557 {
558 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
559 struct r300_query *query = r300->query_current;
560
561 if (!query)
562 return;
563
564 if (query->begin_emitted == FALSE)
565 return;
566
567 if (caps->family == CHIP_FAMILY_RV530) {
568 if (caps->num_z_pipes == 2)
569 rv530_emit_query_double(r300, query);
570 else
571 rv530_emit_query_single(r300, query);
572 } else
573 r300_emit_query_finish(r300, query);
574 }
575
576 void r300_emit_rs_state(struct r300_context* r300, void* state)
577 {
578 struct r300_rs_state* rs = (struct r300_rs_state*)state;
579 float scale, offset;
580 CS_LOCALS(r300);
581
582 BEGIN_CS(18 + (rs->polygon_offset_enable ? 5 : 0));
583 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
584
585 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
586
587 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
588 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
589 OUT_CS(rs->point_minmax);
590 OUT_CS(rs->line_control);
591
592 if (rs->polygon_offset_enable) {
593 scale = rs->depth_scale * 12;
594 offset = rs->depth_offset;
595
596 switch (r300->zbuffer_bpp) {
597 case 16:
598 offset *= 4;
599 break;
600 case 24:
601 offset *= 2;
602 break;
603 }
604
605 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
606 OUT_CS_32F(scale);
607 OUT_CS_32F(offset);
608 OUT_CS_32F(scale);
609 OUT_CS_32F(offset);
610 }
611
612 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
613 OUT_CS(rs->polygon_offset_enable);
614 OUT_CS(rs->cull_mode);
615 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
616 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
617 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
618 END_CS;
619 }
620
621 void r300_emit_rs_block_state(struct r300_context* r300, void* state)
622 {
623 struct r300_rs_block* rs = (struct r300_rs_block*)state;
624 unsigned i;
625 struct r300_screen* r300screen = r300_screen(r300->context.screen);
626 /* It's the same for both INST and IP tables */
627 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
628 CS_LOCALS(r300);
629
630 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
631
632 BEGIN_CS(5 + count*2);
633 if (r300screen->caps->is_r500) {
634 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
635 } else {
636 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
637 }
638 for (i = 0; i < count; i++) {
639 OUT_CS(rs->ip[i]);
640 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
641 }
642
643 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
644 OUT_CS(rs->count);
645 OUT_CS(rs->inst_count);
646
647 if (r300screen->caps->is_r500) {
648 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
649 } else {
650 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
651 }
652 for (i = 0; i < count; i++) {
653 OUT_CS(rs->inst[i]);
654 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
655 }
656
657 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
658 rs->count, rs->inst_count);
659
660 END_CS;
661 }
662
663 void r300_emit_scissor_state(struct r300_context* r300, void* state)
664 {
665 unsigned minx, miny, maxx, maxy;
666 uint32_t top_left, bottom_right;
667 struct r300_screen* r300screen = r300_screen(r300->context.screen);
668 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
669 struct pipe_framebuffer_state* fb =
670 (struct pipe_framebuffer_state*)r300->fb_state.state;
671 CS_LOCALS(r300);
672
673 minx = miny = 0;
674 maxx = fb->width;
675 maxy = fb->height;
676
677 if (((struct r300_rs_state*)r300->rs_state.state)->rs.scissor) {
678 minx = MAX2(minx, scissor->minx);
679 miny = MAX2(miny, scissor->miny);
680 maxx = MIN2(maxx, scissor->maxx);
681 maxy = MIN2(maxy, scissor->maxy);
682 }
683
684 /* Special case for zero-area scissor.
685 *
686 * We can't allow the variables maxx and maxy to be zero because they are
687 * subtracted from later in the code, which would cause emitting ~0 and
688 * making the kernel checker angry.
689 *
690 * Let's consider we change maxx and maxy to 1, which is effectively
691 * a one-pixel area. We must then change minx and miny to a number which is
692 * greater than 1 to get the zero area back. */
693 if (!maxx || !maxy) {
694 minx = 2;
695 miny = 2;
696 maxx = 1;
697 maxy = 1;
698 }
699
700 if (r300screen->caps->is_r500) {
701 top_left =
702 (minx << R300_SCISSORS_X_SHIFT) |
703 (miny << R300_SCISSORS_Y_SHIFT);
704 bottom_right =
705 ((maxx - 1) << R300_SCISSORS_X_SHIFT) |
706 ((maxy - 1) << R300_SCISSORS_Y_SHIFT);
707 } else {
708 /* Offset of 1440 in non-R500 chipsets. */
709 top_left =
710 ((minx + 1440) << R300_SCISSORS_X_SHIFT) |
711 ((miny + 1440) << R300_SCISSORS_Y_SHIFT);
712 bottom_right =
713 (((maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
714 (((maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
715 }
716
717 BEGIN_CS(3);
718 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
719 OUT_CS(top_left);
720 OUT_CS(bottom_right);
721 END_CS;
722 }
723
724 void r300_emit_texture(struct r300_context* r300,
725 struct r300_sampler_state* sampler,
726 struct r300_texture* tex,
727 unsigned offset)
728 {
729 uint32_t filter0 = sampler->filter0;
730 uint32_t format0 = tex->state.format0;
731 unsigned min_level, max_level;
732 CS_LOCALS(r300);
733
734 /* to emulate 1D textures through 2D ones correctly */
735 if (tex->tex.target == PIPE_TEXTURE_1D) {
736 filter0 &= ~R300_TX_WRAP_T_MASK;
737 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
738 }
739
740 if (tex->is_npot) {
741 /* NPOT textures don't support mip filter, unfortunately.
742 * This prevents incorrect rendering. */
743 filter0 &= ~R300_TX_MIN_FILTER_MIP_MASK;
744 } else {
745 /* determine min/max levels */
746 /* the MAX_MIP level is the largest (finest) one */
747 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
748 min_level = MIN2(sampler->min_lod, max_level);
749 format0 |= R300_TX_NUM_LEVELS(max_level);
750 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
751 }
752
753 BEGIN_CS(16);
754 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
755 (offset << 28));
756 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
757 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
758
759 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
760 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
761 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
762 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
763 OUT_CS_RELOC(tex->buffer,
764 R300_TXO_MACRO_TILE(tex->macrotile) |
765 R300_TXO_MICRO_TILE(tex->microtile),
766 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
767 END_CS;
768 }
769
770 void r300_emit_aos(struct r300_context* r300, unsigned offset)
771 {
772 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
773 struct pipe_vertex_element *velem = r300->vertex_element;
774 int i;
775 unsigned size1, size2, aos_count = r300->vertex_element_count;
776 unsigned packet_size = (aos_count * 3 + 1) / 2;
777 CS_LOCALS(r300);
778
779 BEGIN_CS(2 + packet_size + aos_count * 2);
780 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
781 OUT_CS(aos_count);
782
783 for (i = 0; i < aos_count - 1; i += 2) {
784 vb1 = &vbuf[velem[i].vertex_buffer_index];
785 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
786 size1 = util_format_get_blocksize(velem[i].src_format);
787 size2 = util_format_get_blocksize(velem[i+1].src_format);
788
789 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
790 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
791 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
792 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
793 }
794
795 if (aos_count & 1) {
796 vb1 = &vbuf[velem[i].vertex_buffer_index];
797 size1 = util_format_get_blocksize(velem[i].src_format);
798
799 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
800 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
801 }
802
803 for (i = 0; i < aos_count; i++) {
804 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
805 RADEON_GEM_DOMAIN_GTT, 0, 0);
806 }
807 END_CS;
808 }
809
810 void r300_emit_vertex_format_state(struct r300_context* r300, void* state)
811 {
812 struct r300_vertex_info* vertex_info = (struct r300_vertex_info*)state;
813 unsigned i;
814 CS_LOCALS(r300);
815
816 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
817
818 BEGIN_CS(26);
819 OUT_CS_REG(R300_VAP_VTX_SIZE, vertex_info->vinfo.size);
820
821 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
822 OUT_CS(vertex_info->vinfo.hwfmt[0]);
823 OUT_CS(vertex_info->vinfo.hwfmt[1]);
824 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
825 OUT_CS(vertex_info->vinfo.hwfmt[2]);
826 OUT_CS(vertex_info->vinfo.hwfmt[3]);
827 for (i = 0; i < 4; i++) {
828 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
829 vertex_info->vinfo.hwfmt[i]);
830 }
831
832 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
833 for (i = 0; i < 8; i++) {
834 OUT_CS(vertex_info->vap_prog_stream_cntl[i]);
835 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
836 vertex_info->vap_prog_stream_cntl[i]);
837 }
838 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
839 for (i = 0; i < 8; i++) {
840 OUT_CS(vertex_info->vap_prog_stream_cntl_ext[i]);
841 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
842 vertex_info->vap_prog_stream_cntl_ext[i]);
843 }
844 END_CS;
845 }
846
847
848 void r300_emit_vertex_program_code(struct r300_context* r300,
849 struct r300_vertex_program_code* code)
850 {
851 int i;
852 struct r300_screen* r300screen = r300_screen(r300->context.screen);
853 unsigned instruction_count = code->length / 4;
854
855 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
856 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
857 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
858 int temp_count = MAX2(code->num_temporaries, 1);
859 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
860 vtx_mem_size / output_count, 10);
861 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
862
863 CS_LOCALS(r300);
864
865 if (!r300screen->caps->has_tcl) {
866 debug_printf("r300: Implementation error: emit_vertex_shader called,"
867 " but has_tcl is FALSE!\n");
868 return;
869 }
870
871 BEGIN_CS(9 + code->length);
872 /* R300_VAP_PVS_CODE_CNTL_0
873 * R300_VAP_PVS_CONST_CNTL
874 * R300_VAP_PVS_CODE_CNTL_1
875 * See the r5xx docs for instructions on how to use these. */
876 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
877 OUT_CS(R300_PVS_FIRST_INST(0) |
878 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
879 R300_PVS_LAST_INST(instruction_count - 1));
880 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
881 OUT_CS(instruction_count - 1);
882
883 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
884 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
885 for (i = 0; i < code->length; i++)
886 OUT_CS(code->body.d[i]);
887
888 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
889 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
890 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
891 R300_PVS_VF_MAX_VTX_NUM(12) |
892 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
893 END_CS;
894 }
895
896 void r300_emit_vertex_shader(struct r300_context* r300,
897 struct r300_vertex_shader* vs)
898 {
899 r300_emit_vertex_program_code(r300, &vs->code);
900 }
901
902 void r300_emit_vs_constant_buffer(struct r300_context* r300,
903 struct rc_constant_list* constants)
904 {
905 int i;
906 struct r300_screen* r300screen = r300_screen(r300->context.screen);
907 CS_LOCALS(r300);
908
909 if (!r300screen->caps->has_tcl) {
910 debug_printf("r300: Implementation error: emit_vertex_shader called,"
911 " but has_tcl is FALSE!\n");
912 return;
913 }
914
915 if (constants->Count == 0)
916 return;
917
918 BEGIN_CS(constants->Count * 4 + 3);
919 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
920 (r300screen->caps->is_r500 ?
921 R500_PVS_CONST_START : R300_PVS_CONST_START));
922 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
923 for (i = 0; i < constants->Count; i++) {
924 const float * data = get_shader_constant(r300,
925 &constants->Constants[i],
926 &r300->shader_constants[PIPE_SHADER_VERTEX]);
927 OUT_CS_32F(data[0]);
928 OUT_CS_32F(data[1]);
929 OUT_CS_32F(data[2]);
930 OUT_CS_32F(data[3]);
931 }
932 END_CS;
933 }
934
935 void r300_emit_viewport_state(struct r300_context* r300, void* state)
936 {
937 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
938 CS_LOCALS(r300);
939
940 if (r300->tcl_bypass) {
941 BEGIN_CS(2);
942 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
943 END_CS;
944 } else {
945 BEGIN_CS(9);
946 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
947 OUT_CS_32F(viewport->xscale);
948 OUT_CS_32F(viewport->xoffset);
949 OUT_CS_32F(viewport->yscale);
950 OUT_CS_32F(viewport->yoffset);
951 OUT_CS_32F(viewport->zscale);
952 OUT_CS_32F(viewport->zoffset);
953 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
954 END_CS;
955 }
956 }
957
958 void r300_emit_texture_count(struct r300_context* r300)
959 {
960 uint32_t tx_enable = 0;
961 int i;
962 CS_LOCALS(r300);
963
964 /* Notice that texture_count and sampler_count are just sizes
965 * of the respective arrays. We still have to check for the individual
966 * elements. */
967 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
968 if (r300->textures[i]) {
969 tx_enable |= 1 << i;
970 }
971 }
972
973 BEGIN_CS(2);
974 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
975 END_CS;
976
977 }
978
979 void r300_emit_ztop_state(struct r300_context* r300, void* state)
980 {
981 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
982 CS_LOCALS(r300);
983
984 BEGIN_CS(2);
985 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
986 END_CS;
987 }
988
989 void r300_flush_textures(struct r300_context* r300)
990 {
991 CS_LOCALS(r300);
992
993 BEGIN_CS(2);
994 OUT_CS_REG(R300_TX_INVALTAGS, 0);
995 END_CS;
996 }
997
998 static void r300_flush_pvs(struct r300_context* r300)
999 {
1000 CS_LOCALS(r300);
1001
1002 BEGIN_CS(2);
1003 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
1004 END_CS;
1005 }
1006
1007 void r300_emit_buffer_validate(struct r300_context *r300)
1008 {
1009 struct pipe_framebuffer_state* fb =
1010 (struct pipe_framebuffer_state*)r300->fb_state.state;
1011 struct r300_texture* tex;
1012 unsigned i;
1013 boolean invalid = FALSE;
1014
1015 /* Clean out BOs. */
1016 r300->winsys->reset_bos(r300->winsys);
1017
1018 validate:
1019 /* Color buffers... */
1020 for (i = 0; i < fb->nr_cbufs; i++) {
1021 tex = (struct r300_texture*)fb->cbufs[i]->texture;
1022 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1023 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1024 0, RADEON_GEM_DOMAIN_VRAM)) {
1025 r300->context.flush(&r300->context, 0, NULL);
1026 goto validate;
1027 }
1028 }
1029 /* ...depth buffer... */
1030 if (fb->zsbuf) {
1031 tex = (struct r300_texture*)fb->zsbuf->texture;
1032 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1033 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1034 0, RADEON_GEM_DOMAIN_VRAM)) {
1035 r300->context.flush(&r300->context, 0, NULL);
1036 goto validate;
1037 }
1038 }
1039 /* ...textures... */
1040 for (i = 0; i < r300->texture_count; i++) {
1041 tex = r300->textures[i];
1042 if (!tex)
1043 continue;
1044 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1045 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1046 r300->context.flush(&r300->context, 0, NULL);
1047 goto validate;
1048 }
1049 }
1050 /* ...occlusion query buffer... */
1051 if (r300->dirty_state & R300_NEW_QUERY) {
1052 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1053 0, RADEON_GEM_DOMAIN_GTT)) {
1054 r300->context.flush(&r300->context, 0, NULL);
1055 goto validate;
1056 }
1057 }
1058 /* ...and vertex buffer. */
1059 if (r300->vbo) {
1060 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1061 RADEON_GEM_DOMAIN_GTT, 0)) {
1062 r300->context.flush(&r300->context, 0, NULL);
1063 goto validate;
1064 }
1065 } else {
1066 /* debug_printf("No VBO while emitting dirty state!\n"); */
1067 }
1068 if (!r300->winsys->validate(r300->winsys)) {
1069 r300->context.flush(&r300->context, 0, NULL);
1070 if (invalid) {
1071 /* Well, hell. */
1072 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1073 exit(1);
1074 }
1075 invalid = TRUE;
1076 goto validate;
1077 }
1078 }
1079
1080 /* Emit all dirty state. */
1081 void r300_emit_dirty_state(struct r300_context* r300)
1082 {
1083 struct r300_screen* r300screen = r300_screen(r300->context.screen);
1084 struct r300_atom* atom;
1085 unsigned i, dwords = 1024;
1086 int dirty_tex = 0;
1087
1088 /* Check the required number of dwords against the space remaining in the
1089 * current CS object. If we need more, then flush. */
1090
1091 foreach(atom, &r300->atom_list) {
1092 if (atom->dirty || atom->always_dirty) {
1093 dwords += atom->size;
1094 }
1095 }
1096
1097 /* Make sure we have at least 2*1024 spare dwords. */
1098 /* XXX It would be nice to know the number of dwords we really need to
1099 * XXX emit. */
1100 while (!r300->winsys->check_cs(r300->winsys, dwords)) {
1101 r300->context.flush(&r300->context, 0, NULL);
1102 }
1103
1104 if (r300->dirty_state & R300_NEW_QUERY) {
1105 r300_emit_query_start(r300);
1106 r300->dirty_state &= ~R300_NEW_QUERY;
1107 }
1108
1109 foreach(atom, &r300->atom_list) {
1110 if (atom->dirty || atom->always_dirty) {
1111 atom->emit(r300, atom->state);
1112 atom->dirty = FALSE;
1113 }
1114 }
1115
1116 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1117 r300_emit_fragment_depth_config(r300, r300->fs);
1118 if (r300screen->caps->is_r500) {
1119 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1120 } else {
1121 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1122 }
1123 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1124 }
1125
1126 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1127 if (r300screen->caps->is_r500) {
1128 r500_emit_fs_constant_buffer(r300,
1129 &r300->fs->shader->code.constants);
1130 } else {
1131 r300_emit_fs_constant_buffer(r300,
1132 &r300->fs->shader->code.constants);
1133 }
1134 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1135 }
1136
1137 /* Samplers and textures are tracked separately but emitted together. */
1138 if (r300->dirty_state &
1139 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1140 r300_emit_texture_count(r300);
1141
1142 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1143 if (r300->dirty_state &
1144 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1145 if (r300->textures[i]) {
1146 r300_emit_texture(r300,
1147 r300->sampler_states[i],
1148 r300->textures[i],
1149 i);
1150 dirty_tex |= r300->dirty_state & (R300_NEW_TEXTURE << i);
1151 }
1152 r300->dirty_state &=
1153 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1154 }
1155 }
1156 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1157 }
1158
1159 if (dirty_tex) {
1160 r300_flush_textures(r300);
1161 }
1162
1163 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1164 r300_flush_pvs(r300);
1165 }
1166
1167 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1168 r300_emit_vertex_shader(r300, r300->vs);
1169 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1170 }
1171
1172 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1173 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1174 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1175 }
1176
1177 /* XXX
1178 assert(r300->dirty_state == 0);
1179 */
1180
1181 /* Finally, emit the VBO. */
1182 /* r300_emit_vertex_buffer(r300); */
1183
1184 r300->dirty_hw++;
1185 }