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r300g: Add back dirty state check.
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_state_derived.h"
36 #include "r300_state_inlines.h"
37 #include "r300_texture.h"
38 #include "r300_vs.h"
39
40 void r300_emit_blend_state(struct r300_context* r300, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 CS_LOCALS(r300);
44 BEGIN_CS(8);
45 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
46 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
47 if (r300->framebuffer_state.nr_cbufs) {
48 OUT_CS(blend->blend_control);
49 OUT_CS(blend->alpha_blend_control);
50 OUT_CS(blend->color_channel_mask);
51 } else {
52 OUT_CS(0);
53 OUT_CS(0);
54 OUT_CS(0);
55 /* XXX also disable fastfill here once it's supported */
56 }
57 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
58 END_CS;
59 }
60
61 void r300_emit_blend_color_state(struct r300_context* r300, void* state)
62 {
63 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
64 struct r300_screen* r300screen = r300_screen(r300->context.screen);
65 CS_LOCALS(r300);
66
67 if (r300screen->caps->is_r500) {
68 BEGIN_CS(3);
69 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
70 OUT_CS(bc->blend_color_red_alpha);
71 OUT_CS(bc->blend_color_green_blue);
72 END_CS;
73 } else {
74 BEGIN_CS(2);
75 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
76 END_CS;
77 }
78 }
79
80 void r300_emit_clip_state(struct r300_context* r300, void* state)
81 {
82 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
83 int i;
84 struct r300_screen* r300screen = r300_screen(r300->context.screen);
85 CS_LOCALS(r300);
86
87 if (r300screen->caps->has_tcl) {
88 BEGIN_CS(5 + (6 * 4));
89 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
90 (r300screen->caps->is_r500 ?
91 R500_PVS_UCP_START : R300_PVS_UCP_START));
92 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
93 for (i = 0; i < 6; i++) {
94 OUT_CS_32F(clip->ucp[i][0]);
95 OUT_CS_32F(clip->ucp[i][1]);
96 OUT_CS_32F(clip->ucp[i][2]);
97 OUT_CS_32F(clip->ucp[i][3]);
98 }
99 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
100 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
101 END_CS;
102 } else {
103 BEGIN_CS(2);
104 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
105 END_CS;
106 }
107
108 }
109
110 void r300_emit_dsa_state(struct r300_context* r300, void* state)
111 {
112 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
113 struct r300_screen* r300screen = r300_screen(r300->context.screen);
114 CS_LOCALS(r300);
115
116 BEGIN_CS(r300screen->caps->is_r500 ? 8 : 6);
117 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
118
119 /* not needed since we use the 8bit alpha ref */
120 /*if (r300screen->caps->is_r500) {
121 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
122 }*/
123
124 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
125 OUT_CS(dsa->z_buffer_control);
126 OUT_CS(dsa->z_stencil_control);
127 OUT_CS(dsa->stencil_ref_mask);
128
129 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
130 if (r300screen->caps->is_r500) {
131 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
132 }
133 END_CS;
134 }
135
136 static const float * get_shader_constant(
137 struct r300_context * r300,
138 struct rc_constant * constant,
139 struct r300_constant_buffer * externals)
140 {
141 struct r300_viewport_state* viewport =
142 (struct r300_viewport_state*)r300->viewport_state.state;
143 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
144 struct pipe_texture *tex;
145
146 switch(constant->Type) {
147 case RC_CONSTANT_EXTERNAL:
148 return externals->constants[constant->u.External];
149
150 case RC_CONSTANT_IMMEDIATE:
151 return constant->u.Immediate;
152
153 case RC_CONSTANT_STATE:
154 switch (constant->u.State[0]) {
155 /* Factor for converting rectangle coords to
156 * normalized coords. Should only show up on non-r500. */
157 case RC_STATE_R300_TEXRECT_FACTOR:
158 tex = &r300->textures[constant->u.State[1]]->tex;
159 vec[0] = 1.0 / tex->width0;
160 vec[1] = 1.0 / tex->height0;
161 break;
162
163 /* Texture compare-fail value. */
164 /* XXX Since Gallium doesn't support GL_ARB_shadow_ambient,
165 * this is always (0,0,0,0), right? */
166 case RC_STATE_SHADOW_AMBIENT:
167 vec[3] = 0;
168 break;
169
170 case RC_STATE_R300_VIEWPORT_SCALE:
171 if (r300->tcl_bypass) {
172 vec[0] = 1;
173 vec[1] = 1;
174 vec[2] = 1;
175 } else {
176 vec[0] = viewport->xscale;
177 vec[1] = viewport->yscale;
178 vec[2] = viewport->zscale;
179 }
180 break;
181
182 case RC_STATE_R300_VIEWPORT_OFFSET:
183 if (!r300->tcl_bypass) {
184 vec[0] = viewport->xoffset;
185 vec[1] = viewport->yoffset;
186 vec[2] = viewport->zoffset;
187 }
188 break;
189
190 default:
191 debug_printf("r300: Implementation error: "
192 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
193 }
194 break;
195
196 default:
197 debug_printf("r300: Implementation error: "
198 "Unhandled constant type %d\n", constant->Type);
199 }
200
201 /* This should either be (0, 0, 0, 1), which should be a relatively safe
202 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
203 * state factors. */
204 return vec;
205 }
206
207 /* Convert a normal single-precision float into the 7.16 format
208 * used by the R300 fragment shader.
209 */
210 static uint32_t pack_float24(float f)
211 {
212 union {
213 float fl;
214 uint32_t u;
215 } u;
216 float mantissa;
217 int exponent;
218 uint32_t float24 = 0;
219
220 if (f == 0.0)
221 return 0;
222
223 u.fl = f;
224
225 mantissa = frexpf(f, &exponent);
226
227 /* Handle -ve */
228 if (mantissa < 0) {
229 float24 |= (1 << 23);
230 mantissa = mantissa * -1.0;
231 }
232 /* Handle exponent, bias of 63 */
233 exponent += 62;
234 float24 |= (exponent << 16);
235 /* Kill 7 LSB of mantissa */
236 float24 |= (u.u & 0x7FFFFF) >> 7;
237
238 return float24;
239 }
240
241 void r300_emit_fragment_program_code(struct r300_context* r300,
242 struct rX00_fragment_program_code* generic_code)
243 {
244 struct r300_fragment_program_code * code = &generic_code->code.r300;
245 int i;
246 CS_LOCALS(r300);
247
248 BEGIN_CS(15 +
249 code->alu.length * 4 +
250 (code->tex.length ? (1 + code->tex.length) : 0));
251
252 OUT_CS_REG(R300_US_CONFIG, code->config);
253 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
254 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
255
256 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
257 for(i = 0; i < 4; ++i)
258 OUT_CS(code->code_addr[i]);
259
260 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
261 for (i = 0; i < code->alu.length; i++)
262 OUT_CS(code->alu.inst[i].rgb_inst);
263
264 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
265 for (i = 0; i < code->alu.length; i++)
266 OUT_CS(code->alu.inst[i].rgb_addr);
267
268 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
269 for (i = 0; i < code->alu.length; i++)
270 OUT_CS(code->alu.inst[i].alpha_inst);
271
272 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
273 for (i = 0; i < code->alu.length; i++)
274 OUT_CS(code->alu.inst[i].alpha_addr);
275
276 if (code->tex.length) {
277 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
278 for(i = 0; i < code->tex.length; ++i)
279 OUT_CS(code->tex.inst[i]);
280 }
281
282 END_CS;
283 }
284
285 void r300_emit_fs_constant_buffer(struct r300_context* r300,
286 struct rc_constant_list* constants)
287 {
288 int i;
289 CS_LOCALS(r300);
290
291 if (constants->Count == 0)
292 return;
293
294 BEGIN_CS(constants->Count * 4 + 1);
295 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
296 for(i = 0; i < constants->Count; ++i) {
297 const float * data = get_shader_constant(r300,
298 &constants->Constants[i],
299 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
300 OUT_CS(pack_float24(data[0]));
301 OUT_CS(pack_float24(data[1]));
302 OUT_CS(pack_float24(data[2]));
303 OUT_CS(pack_float24(data[3]));
304 }
305 END_CS;
306 }
307
308 static void r300_emit_fragment_depth_config(struct r300_context* r300,
309 struct r300_fragment_shader* fs)
310 {
311 CS_LOCALS(r300);
312
313 BEGIN_CS(4);
314 if (r300_fragment_shader_writes_depth(fs)) {
315 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
316 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
317 } else {
318 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
319 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
320 }
321 END_CS;
322 }
323
324 void r500_emit_fragment_program_code(struct r300_context* r300,
325 struct rX00_fragment_program_code* generic_code)
326 {
327 struct r500_fragment_program_code * code = &generic_code->code.r500;
328 int i;
329 CS_LOCALS(r300);
330
331 BEGIN_CS(13 +
332 ((code->inst_end + 1) * 6));
333 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
334 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
335 OUT_CS_REG(R500_US_CODE_RANGE,
336 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
337 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
338 OUT_CS_REG(R500_US_CODE_ADDR,
339 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
340
341 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
342 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
343 for (i = 0; i <= code->inst_end; i++) {
344 OUT_CS(code->inst[i].inst0);
345 OUT_CS(code->inst[i].inst1);
346 OUT_CS(code->inst[i].inst2);
347 OUT_CS(code->inst[i].inst3);
348 OUT_CS(code->inst[i].inst4);
349 OUT_CS(code->inst[i].inst5);
350 }
351
352 END_CS;
353 }
354
355 void r500_emit_fs_constant_buffer(struct r300_context* r300,
356 struct rc_constant_list* constants)
357 {
358 int i;
359 CS_LOCALS(r300);
360
361 if (constants->Count == 0)
362 return;
363
364 BEGIN_CS(constants->Count * 4 + 3);
365 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
366 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
367 for (i = 0; i < constants->Count; i++) {
368 const float * data = get_shader_constant(r300,
369 &constants->Constants[i],
370 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
371 OUT_CS_32F(data[0]);
372 OUT_CS_32F(data[1]);
373 OUT_CS_32F(data[2]);
374 OUT_CS_32F(data[3]);
375 }
376 END_CS;
377 }
378
379 void r300_emit_fb_state(struct r300_context* r300,
380 struct pipe_framebuffer_state* fb)
381 {
382 struct r300_texture* tex;
383 struct pipe_surface* surf;
384 int i;
385 CS_LOCALS(r300);
386
387 /* Shouldn't fail unless there is a bug in the state tracker. */
388 assert(fb->nr_cbufs <= 4);
389
390 BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
391 (fb->zsbuf ? 10 : 3) + 6);
392
393 /* Flush and free renderbuffer caches. */
394 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
395 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
396 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
397 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
398 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
399 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
400
401 /* Set the number of colorbuffers. */
402 OUT_CS_REG(R300_RB3D_CCTL, R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
403
404 /* Set up colorbuffers. */
405 for (i = 0; i < fb->nr_cbufs; i++) {
406 surf = fb->cbufs[i];
407 tex = (struct r300_texture*)surf->texture;
408 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
409
410 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
411 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
412
413 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
414 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
415 r300_translate_colorformat(tex->tex.format), 0,
416 RADEON_GEM_DOMAIN_VRAM, 0);
417
418 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
419 r300_translate_out_fmt(surf->format));
420 }
421
422 /* Disable unused colorbuffers. */
423 for (; i < 4; i++) {
424 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
425 }
426
427 /* Set up the Z/stencil buffer, or disable it. */
428 if (fb->zsbuf) {
429 surf = fb->zsbuf;
430 tex = (struct r300_texture*)surf->texture;
431 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
432
433 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
434 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
435
436 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
437
438 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
439 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level], 0,
440 RADEON_GEM_DOMAIN_VRAM, 0);
441 } else {
442 OUT_CS_REG_SEQ(R300_ZB_CNTL, 2);
443 OUT_CS(0x0);
444 OUT_CS(0x0);
445 }
446
447 END_CS;
448 }
449
450 static void r300_emit_query_start(struct r300_context *r300)
451 {
452 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
453 struct r300_query *query = r300->query_current;
454 CS_LOCALS(r300);
455
456 if (!query)
457 return;
458
459 BEGIN_CS(4);
460 if (caps->family == CHIP_FAMILY_RV530) {
461 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
462 } else {
463 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
464 }
465 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
466 END_CS;
467 query->begin_emitted = TRUE;
468 }
469
470
471 static void r300_emit_query_finish(struct r300_context *r300,
472 struct r300_query *query)
473 {
474 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
475 CS_LOCALS(r300);
476
477 assert(caps->num_frag_pipes);
478
479 BEGIN_CS(6 * caps->num_frag_pipes + 2);
480 /* I'm not so sure I like this switch, but it's hard to be elegant
481 * when there's so many special cases...
482 *
483 * So here's the basic idea. For each pipe, enable writes to it only,
484 * then put out the relocation for ZPASS_ADDR, taking into account a
485 * 4-byte offset for each pipe. RV380 and older are special; they have
486 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
487 * so there's a chipset cap for that. */
488 switch (caps->num_frag_pipes) {
489 case 4:
490 /* pipe 3 only */
491 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
492 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
493 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
494 0, RADEON_GEM_DOMAIN_GTT, 0);
495 case 3:
496 /* pipe 2 only */
497 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
498 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
499 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
500 0, RADEON_GEM_DOMAIN_GTT, 0);
501 case 2:
502 /* pipe 1 only */
503 /* As mentioned above, accomodate RV380 and older. */
504 OUT_CS_REG(R300_SU_REG_DEST,
505 1 << (caps->high_second_pipe ? 3 : 1));
506 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
507 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
508 0, RADEON_GEM_DOMAIN_GTT, 0);
509 case 1:
510 /* pipe 0 only */
511 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
512 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
513 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
514 0, RADEON_GEM_DOMAIN_GTT, 0);
515 break;
516 default:
517 debug_printf("r300: Implementation error: Chipset reports %d"
518 " pixel pipes!\n", caps->num_frag_pipes);
519 assert(0);
520 }
521
522 /* And, finally, reset it to normal... */
523 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
524 END_CS;
525 }
526
527 static void rv530_emit_query_single(struct r300_context *r300,
528 struct r300_query *query)
529 {
530 CS_LOCALS(r300);
531
532 BEGIN_CS(8);
533 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
534 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
535 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
536 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
537 END_CS;
538 }
539
540 static void rv530_emit_query_double(struct r300_context *r300,
541 struct r300_query *query)
542 {
543 CS_LOCALS(r300);
544
545 BEGIN_CS(14);
546 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
547 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
548 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
549 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
550 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
551 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
552 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
553 END_CS;
554 }
555
556 void r300_emit_query_end(struct r300_context* r300)
557 {
558 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
559 struct r300_query *query = r300->query_current;
560
561 if (!query)
562 return;
563
564 if (query->begin_emitted == FALSE)
565 return;
566
567 if (caps->family == CHIP_FAMILY_RV530) {
568 if (caps->num_z_pipes == 2)
569 rv530_emit_query_double(r300, query);
570 else
571 rv530_emit_query_single(r300, query);
572 } else
573 r300_emit_query_finish(r300, query);
574 }
575
576 void r300_emit_rs_state(struct r300_context* r300, void* state)
577 {
578 struct r300_rs_state* rs = (struct r300_rs_state*)state;
579 CS_LOCALS(r300);
580
581 BEGIN_CS(22);
582 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
583 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
584 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
585 OUT_CS(rs->point_minmax);
586 OUT_CS(rs->line_control);
587 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
588 OUT_CS(rs->depth_scale_front);
589 OUT_CS(rs->depth_offset_front);
590 OUT_CS(rs->depth_scale_back);
591 OUT_CS(rs->depth_offset_back);
592 OUT_CS(rs->polygon_offset_enable);
593 OUT_CS(rs->cull_mode);
594 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
595 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
596 OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
597 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
598 END_CS;
599 }
600
601 void r300_emit_rs_block_state(struct r300_context* r300,
602 struct r300_rs_block* rs)
603 {
604 int i;
605 struct r300_screen* r300screen = r300_screen(r300->context.screen);
606 CS_LOCALS(r300);
607
608 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
609
610 BEGIN_CS(21);
611 if (r300screen->caps->is_r500) {
612 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
613 } else {
614 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
615 }
616 for (i = 0; i < 8; i++) {
617 OUT_CS(rs->ip[i]);
618 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
619 }
620
621 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
622 OUT_CS(rs->count);
623 OUT_CS(rs->inst_count);
624
625 if (r300screen->caps->is_r500) {
626 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
627 } else {
628 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
629 }
630 for (i = 0; i < 8; i++) {
631 OUT_CS(rs->inst[i]);
632 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
633 }
634
635 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
636 rs->count, rs->inst_count);
637
638 END_CS;
639 }
640
641 static void r300_emit_scissor_regs(struct r300_context* r300,
642 struct r300_scissor_regs* scissor)
643 {
644 CS_LOCALS(r300);
645
646 BEGIN_CS(3);
647 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
648 OUT_CS(scissor->top_left);
649 OUT_CS(scissor->bottom_right);
650 END_CS;
651 }
652
653 void r300_emit_scissor_state(struct r300_context* r300, void* state)
654 {
655 struct r300_scissor_state* scissor = (struct r300_scissor_state*)state;
656 /* XXX argfl! */
657 if (((struct r300_rs_state*)r300->rs_state.state)->rs.scissor) {
658 r300_emit_scissor_regs(r300, &scissor->scissor);
659 } else {
660 r300_emit_scissor_regs(r300, &scissor->framebuffer);
661 }
662 }
663
664 void r300_emit_texture(struct r300_context* r300,
665 struct r300_sampler_state* sampler,
666 struct r300_texture* tex,
667 unsigned offset)
668 {
669 uint32_t filter0 = sampler->filter0;
670 uint32_t format0 = tex->state.format0;
671 unsigned min_level, max_level;
672 CS_LOCALS(r300);
673
674 /* to emulate 1D textures through 2D ones correctly */
675 if (tex->tex.target == PIPE_TEXTURE_1D) {
676 filter0 &= ~R300_TX_WRAP_T_MASK;
677 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
678 }
679
680 /* determine min/max levels */
681 /* the MAX_MIP level is the largest (finest) one */
682 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
683 min_level = MIN2(sampler->min_lod, max_level);
684 format0 |= R300_TX_NUM_LEVELS(max_level);
685 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
686
687 BEGIN_CS(16);
688 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
689 (offset << 28));
690 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
691 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
692
693 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
694 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
695 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
696 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
697 OUT_CS_RELOC(tex->buffer, 0,
698 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
699 END_CS;
700 }
701
702 static boolean r300_validate_aos(struct r300_context *r300)
703 {
704 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
705 struct pipe_vertex_element *velem = r300->vertex_element;
706 int i;
707
708 /* Check if formats and strides are aligned to the size of DWORD. */
709 for (i = 0; i < r300->vertex_element_count; i++) {
710 if (vbuf[velem[i].vertex_buffer_index].stride % 4 != 0 ||
711 util_format_get_blocksize(velem[i].src_format) % 4 != 0) {
712 return FALSE;
713 }
714 }
715 return TRUE;
716 }
717
718 void r300_emit_aos(struct r300_context* r300, unsigned offset)
719 {
720 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
721 struct pipe_vertex_element *velem = r300->vertex_element;
722 int i;
723 unsigned size1, size2, aos_count = r300->vertex_element_count;
724 unsigned packet_size = (aos_count * 3 + 1) / 2;
725 CS_LOCALS(r300);
726
727 /* XXX Move this checking to a more approriate place. */
728 if (!r300_validate_aos(r300)) {
729 /* XXX We should fallback using Draw. */
730 assert(0);
731 }
732
733 BEGIN_CS(2 + packet_size + aos_count * 2);
734 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
735 OUT_CS(aos_count);
736
737 for (i = 0; i < aos_count - 1; i += 2) {
738 vb1 = &vbuf[velem[i].vertex_buffer_index];
739 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
740 size1 = util_format_get_blocksize(velem[i].src_format);
741 size2 = util_format_get_blocksize(velem[i+1].src_format);
742
743 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
744 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
745 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
746 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
747 }
748
749 if (aos_count & 1) {
750 vb1 = &vbuf[velem[i].vertex_buffer_index];
751 size1 = util_format_get_blocksize(velem[i].src_format);
752
753 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
754 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
755 }
756
757 for (i = 0; i < aos_count; i++) {
758 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
759 RADEON_GEM_DOMAIN_GTT, 0, 0);
760 }
761 END_CS;
762 }
763
764 #if 0
765 void r300_emit_draw_packet(struct r300_context* r300)
766 {
767 CS_LOCALS(r300);
768
769 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
770 "vertex size %d\n", r300->vbo,
771 r300->vertex_info->vinfo.size);
772 /* Set the pointer to our vertex buffer. The emitted values are this:
773 * PACKET3 [3D_LOAD_VBPNTR]
774 * COUNT [1]
775 * FORMAT [size | stride << 8]
776 * OFFSET [offset into BO]
777 * VBPNTR [relocated BO]
778 */
779 BEGIN_CS(7);
780 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
781 OUT_CS(1);
782 OUT_CS(r300->vertex_info->vinfo.size |
783 (r300->vertex_info->vinfo.size << 8));
784 OUT_CS(r300->vbo_offset);
785 OUT_CS_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
786 END_CS;
787 }
788 #endif
789
790 void r300_emit_vertex_format_state(struct r300_context* r300)
791 {
792 int i;
793 CS_LOCALS(r300);
794
795 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
796
797 BEGIN_CS(26);
798 OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info->vinfo.size);
799
800 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
801 OUT_CS(r300->vertex_info->vinfo.hwfmt[0]);
802 OUT_CS(r300->vertex_info->vinfo.hwfmt[1]);
803 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
804 OUT_CS(r300->vertex_info->vinfo.hwfmt[2]);
805 OUT_CS(r300->vertex_info->vinfo.hwfmt[3]);
806 for (i = 0; i < 4; i++) {
807 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
808 r300->vertex_info->vinfo.hwfmt[i]);
809 }
810
811 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
812 for (i = 0; i < 8; i++) {
813 OUT_CS(r300->vertex_info->vap_prog_stream_cntl[i]);
814 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
815 r300->vertex_info->vap_prog_stream_cntl[i]);
816 }
817 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
818 for (i = 0; i < 8; i++) {
819 OUT_CS(r300->vertex_info->vap_prog_stream_cntl_ext[i]);
820 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
821 r300->vertex_info->vap_prog_stream_cntl_ext[i]);
822 }
823 END_CS;
824 }
825
826
827 void r300_emit_vertex_program_code(struct r300_context* r300,
828 struct r300_vertex_program_code* code)
829 {
830 int i;
831 struct r300_screen* r300screen = r300_screen(r300->context.screen);
832 unsigned instruction_count = code->length / 4;
833
834 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
835 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
836 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
837 int temp_count = MAX2(code->num_temporaries, 1);
838 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
839 vtx_mem_size / output_count, 10);
840 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
841
842 CS_LOCALS(r300);
843
844 if (!r300screen->caps->has_tcl) {
845 debug_printf("r300: Implementation error: emit_vertex_shader called,"
846 " but has_tcl is FALSE!\n");
847 return;
848 }
849
850 BEGIN_CS(9 + code->length);
851 /* R300_VAP_PVS_CODE_CNTL_0
852 * R300_VAP_PVS_CONST_CNTL
853 * R300_VAP_PVS_CODE_CNTL_1
854 * See the r5xx docs for instructions on how to use these. */
855 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
856 OUT_CS(R300_PVS_FIRST_INST(0) |
857 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
858 R300_PVS_LAST_INST(instruction_count - 1));
859 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
860 OUT_CS(instruction_count - 1);
861
862 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
863 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
864 for (i = 0; i < code->length; i++)
865 OUT_CS(code->body.d[i]);
866
867 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
868 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
869 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
870 R300_PVS_VF_MAX_VTX_NUM(12) |
871 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
872 END_CS;
873 }
874
875 void r300_emit_vertex_shader(struct r300_context* r300,
876 struct r300_vertex_shader* vs)
877 {
878 r300_emit_vertex_program_code(r300, &vs->code);
879 }
880
881 void r300_emit_vs_constant_buffer(struct r300_context* r300,
882 struct rc_constant_list* constants)
883 {
884 int i;
885 struct r300_screen* r300screen = r300_screen(r300->context.screen);
886 CS_LOCALS(r300);
887
888 if (!r300screen->caps->has_tcl) {
889 debug_printf("r300: Implementation error: emit_vertex_shader called,"
890 " but has_tcl is FALSE!\n");
891 return;
892 }
893
894 if (constants->Count == 0)
895 return;
896
897 BEGIN_CS(constants->Count * 4 + 3);
898 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
899 (r300screen->caps->is_r500 ?
900 R500_PVS_CONST_START : R300_PVS_CONST_START));
901 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
902 for (i = 0; i < constants->Count; i++) {
903 const float * data = get_shader_constant(r300,
904 &constants->Constants[i],
905 &r300->shader_constants[PIPE_SHADER_VERTEX]);
906 OUT_CS_32F(data[0]);
907 OUT_CS_32F(data[1]);
908 OUT_CS_32F(data[2]);
909 OUT_CS_32F(data[3]);
910 }
911 END_CS;
912 }
913
914 void r300_emit_viewport_state(struct r300_context* r300, void* state)
915 {
916 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
917 CS_LOCALS(r300);
918
919 if (r300->tcl_bypass) {
920 BEGIN_CS(2);
921 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
922 END_CS;
923 } else {
924 BEGIN_CS(9);
925 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
926 OUT_CS_32F(viewport->xscale);
927 OUT_CS_32F(viewport->xoffset);
928 OUT_CS_32F(viewport->yscale);
929 OUT_CS_32F(viewport->yoffset);
930 OUT_CS_32F(viewport->zscale);
931 OUT_CS_32F(viewport->zoffset);
932 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
933 END_CS;
934 }
935 }
936
937 void r300_emit_texture_count(struct r300_context* r300)
938 {
939 uint32_t tx_enable = 0;
940 int i;
941 CS_LOCALS(r300);
942
943 /* Notice that texture_count and sampler_count are just sizes
944 * of the respective arrays. We still have to check for the individual
945 * elements. */
946 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
947 if (r300->textures[i]) {
948 tx_enable |= 1 << i;
949 }
950 }
951
952 BEGIN_CS(2);
953 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
954 END_CS;
955
956 }
957
958 void r300_emit_ztop_state(struct r300_context* r300, void* state)
959 {
960 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
961 CS_LOCALS(r300);
962
963 BEGIN_CS(2);
964 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
965 END_CS;
966 }
967
968 void r300_flush_textures(struct r300_context* r300)
969 {
970 CS_LOCALS(r300);
971
972 BEGIN_CS(2);
973 OUT_CS_REG(R300_TX_INVALTAGS, 0);
974 END_CS;
975 }
976
977 static void r300_flush_pvs(struct r300_context* r300)
978 {
979 CS_LOCALS(r300);
980
981 BEGIN_CS(2);
982 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
983 END_CS;
984 }
985
986 /* Emit all dirty state. */
987 void r300_emit_dirty_state(struct r300_context* r300)
988 {
989 struct r300_screen* r300screen = r300_screen(r300->context.screen);
990 struct r300_texture* tex;
991 struct r300_atom* atom;
992 int i, dirty_tex = 0;
993 boolean invalid = FALSE;
994
995 /* Check size of CS. */
996 /* Make sure we have at least 8*1024 spare dwords. */
997 /* XXX It would be nice to know the number of dwords we really need to
998 * XXX emit. */
999 if (!r300->winsys->check_cs(r300->winsys, 8*1024)) {
1000 r300->context.flush(&r300->context, 0, NULL);
1001 }
1002
1003 if (!(r300->dirty_state)) {
1004 return;
1005 }
1006
1007 /* Clean out BOs. */
1008 r300->winsys->reset_bos(r300->winsys);
1009
1010 validate:
1011 /* Color buffers... */
1012 for (i = 0; i < r300->framebuffer_state.nr_cbufs; i++) {
1013 tex = (struct r300_texture*)r300->framebuffer_state.cbufs[i]->texture;
1014 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1015 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1016 0, RADEON_GEM_DOMAIN_VRAM)) {
1017 r300->context.flush(&r300->context, 0, NULL);
1018 goto validate;
1019 }
1020 }
1021 /* ...depth buffer... */
1022 if (r300->framebuffer_state.zsbuf) {
1023 tex = (struct r300_texture*)r300->framebuffer_state.zsbuf->texture;
1024 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1025 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1026 0, RADEON_GEM_DOMAIN_VRAM)) {
1027 r300->context.flush(&r300->context, 0, NULL);
1028 goto validate;
1029 }
1030 }
1031 /* ...textures... */
1032 for (i = 0; i < r300->texture_count; i++) {
1033 tex = r300->textures[i];
1034 if (!tex)
1035 continue;
1036 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1037 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1038 r300->context.flush(&r300->context, 0, NULL);
1039 goto validate;
1040 }
1041 }
1042 /* ...occlusion query buffer... */
1043 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1044 0, RADEON_GEM_DOMAIN_GTT)) {
1045 r300->context.flush(&r300->context, 0, NULL);
1046 goto validate;
1047 }
1048 /* ...and vertex buffer. */
1049 if (r300->vbo) {
1050 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1051 RADEON_GEM_DOMAIN_GTT, 0)) {
1052 r300->context.flush(&r300->context, 0, NULL);
1053 goto validate;
1054 }
1055 } else {
1056 /* debug_printf("No VBO while emitting dirty state!\n"); */
1057 }
1058 if (!r300->winsys->validate(r300->winsys)) {
1059 r300->context.flush(&r300->context, 0, NULL);
1060 if (invalid) {
1061 /* Well, hell. */
1062 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1063 exit(1);
1064 }
1065 invalid = TRUE;
1066 goto validate;
1067 }
1068
1069 if (r300->dirty_state & R300_NEW_QUERY) {
1070 r300_emit_query_start(r300);
1071 r300->dirty_state &= ~R300_NEW_QUERY;
1072 }
1073
1074 foreach(atom, &r300->atom_list) {
1075 if (atom->dirty) {
1076 atom->emit(r300, atom->state);
1077 atom->dirty = FALSE;
1078 }
1079 }
1080
1081 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1082 r300_emit_fragment_depth_config(r300, r300->fs);
1083 if (r300screen->caps->is_r500) {
1084 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1085 } else {
1086 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1087 }
1088 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1089 }
1090
1091 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1092 if (r300screen->caps->is_r500) {
1093 r500_emit_fs_constant_buffer(r300,
1094 &r300->fs->shader->code.constants);
1095 } else {
1096 r300_emit_fs_constant_buffer(r300,
1097 &r300->fs->shader->code.constants);
1098 }
1099 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1100 }
1101
1102 if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
1103 r300_emit_fb_state(r300, &r300->framebuffer_state);
1104 r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
1105 }
1106
1107 if (r300->dirty_state & R300_NEW_RS_BLOCK) {
1108 r300_emit_rs_block_state(r300, r300->rs_block);
1109 r300->dirty_state &= ~R300_NEW_RS_BLOCK;
1110 }
1111
1112 /* Samplers and textures are tracked separately but emitted together. */
1113 if (r300->dirty_state &
1114 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1115 r300_emit_texture_count(r300);
1116
1117 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1118 if (r300->dirty_state &
1119 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1120 if (r300->textures[i])
1121 r300_emit_texture(r300,
1122 r300->sampler_states[i],
1123 r300->textures[i],
1124 i);
1125 r300->dirty_state &=
1126 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1127 dirty_tex++;
1128 }
1129 }
1130 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1131 }
1132
1133 if (dirty_tex) {
1134 r300_flush_textures(r300);
1135 }
1136
1137 if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
1138 r300_emit_vertex_format_state(r300);
1139 r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
1140 }
1141
1142 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1143 r300_flush_pvs(r300);
1144 }
1145
1146 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1147 r300_emit_vertex_shader(r300, r300->vs);
1148 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1149 }
1150
1151 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1152 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1153 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1154 }
1155
1156 /* XXX
1157 assert(r300->dirty_state == 0);
1158 */
1159
1160 /* Finally, emit the VBO. */
1161 /* r300_emit_vertex_buffer(r300); */
1162
1163 r300->dirty_hw++;
1164 }