2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23 /* r300_emit: Functions for emitting state. */
25 #include "util/u_math.h"
27 #include "r300_context.h"
29 #include "r300_emit.h"
31 #include "r300_screen.h"
32 #include "r300_state_derived.h"
33 #include "r300_state_inlines.h"
34 #include "r300_texture.h"
37 void r300_emit_blend_state(struct r300_context
* r300
,
38 struct r300_blend_state
* blend
)
42 OUT_CS_REG_SEQ(R300_RB3D_CBLEND
, 3);
43 OUT_CS(blend
->blend_control
);
44 OUT_CS(blend
->alpha_blend_control
);
45 OUT_CS(blend
->color_channel_mask
);
46 OUT_CS_REG(R300_RB3D_ROPCNTL
, blend
->rop
);
47 OUT_CS_REG(R300_RB3D_DITHER_CTL
, blend
->dither
);
51 void r300_emit_blend_color_state(struct r300_context
* r300
,
52 struct r300_blend_color_state
* bc
)
54 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
57 if (r300screen
->caps
->is_r500
) {
59 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR
, 2);
60 OUT_CS(bc
->blend_color_red_alpha
);
61 OUT_CS(bc
->blend_color_green_blue
);
65 OUT_CS_REG(R300_RB3D_BLEND_COLOR
, bc
->blend_color
);
70 void r300_emit_clip_state(struct r300_context
* r300
,
71 struct pipe_clip_state
* clip
)
74 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
77 if (r300screen
->caps
->has_tcl
) {
78 BEGIN_CS(5 + (6 * 4));
79 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
80 (r300screen
->caps
->is_r500
?
81 R500_PVS_UCP_START
: R300_PVS_UCP_START
));
82 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, 6 * 4);
83 for (i
= 0; i
< 6; i
++) {
84 OUT_CS_32F(clip
->ucp
[i
][0]);
85 OUT_CS_32F(clip
->ucp
[i
][1]);
86 OUT_CS_32F(clip
->ucp
[i
][2]);
87 OUT_CS_32F(clip
->ucp
[i
][3]);
89 OUT_CS_REG(R300_VAP_CLIP_CNTL
, ((1 << clip
->nr
) - 1) |
90 R300_PS_UCP_MODE_CLIP_AS_TRIFAN
);
94 OUT_CS_REG(R300_VAP_CLIP_CNTL
, R300_CLIP_DISABLE
);
100 void r300_emit_dsa_state(struct r300_context
* r300
,
101 struct r300_dsa_state
* dsa
)
103 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
106 BEGIN_CS(r300screen
->caps
->is_r500
? 10 : 8);
107 OUT_CS_REG(R300_FG_ALPHA_FUNC
, dsa
->alpha_function
);
109 /* not needed since we use the 8bit alpha ref */
110 /*if (r300screen->caps->is_r500) {
111 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
114 OUT_CS_REG_SEQ(R300_ZB_CNTL
, 3);
115 OUT_CS(dsa
->z_buffer_control
);
116 OUT_CS(dsa
->z_stencil_control
);
117 OUT_CS(dsa
->stencil_ref_mask
);
118 OUT_CS_REG(R300_ZB_ZTOP
, r300
->ztop_state
.z_buffer_top
);
120 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
121 if (r300screen
->caps
->is_r500
) {
122 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF
, dsa
->stencil_ref_bf
);
127 static const float * get_shader_constant(
128 struct r300_context
* r300
,
129 struct rc_constant
* constant
,
130 struct r300_constant_buffer
* externals
)
132 static float vec
[4] = { 0.0, 0.0, 0.0, 1.0 };
133 struct pipe_texture
*tex
;
135 switch(constant
->Type
) {
136 case RC_CONSTANT_EXTERNAL
:
137 return externals
->constants
[constant
->u
.External
];
139 case RC_CONSTANT_IMMEDIATE
:
140 return constant
->u
.Immediate
;
142 case RC_CONSTANT_STATE
:
143 switch (constant
->u
.State
[0]) {
144 /* Factor for converting rectangle coords to
145 * normalized coords. Should only show up on non-r500. */
146 case RC_STATE_R300_TEXRECT_FACTOR
:
147 tex
= &r300
->textures
[constant
->u
.State
[1]]->tex
;
148 vec
[0] = 1.0 / tex
->width0
;
149 vec
[1] = 1.0 / tex
->height0
;
153 debug_printf("r300: Implementation error: "
154 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
159 debug_printf("r300: Implementation error: "
160 "Unhandled constant type %d\n", constant
->Type
);
163 /* This should either be (0, 0, 0, 1), which should be a relatively safe
164 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
169 /* Convert a normal single-precision float into the 7.16 format
170 * used by the R300 fragment shader.
172 static uint32_t pack_float24(float f
)
180 uint32_t float24
= 0;
187 mantissa
= frexpf(f
, &exponent
);
191 float24
|= (1 << 23);
192 mantissa
= mantissa
* -1.0;
194 /* Handle exponent, bias of 63 */
196 float24
|= (exponent
<< 16);
197 /* Kill 7 LSB of mantissa */
198 float24
|= (u
.u
& 0x7FFFFF) >> 7;
203 void r300_emit_fragment_program_code(struct r300_context
* r300
,
204 struct rX00_fragment_program_code
* generic_code
)
206 struct r300_fragment_program_code
* code
= &generic_code
->code
.r300
;
211 code
->alu
.length
* 4 +
212 (code
->tex
.length
? (1 + code
->tex
.length
) : 0));
214 OUT_CS_REG(R300_US_CONFIG
, code
->config
);
215 OUT_CS_REG(R300_US_PIXSIZE
, code
->pixsize
);
216 OUT_CS_REG(R300_US_CODE_OFFSET
, code
->code_offset
);
218 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0
, 4);
219 for(i
= 0; i
< 4; ++i
)
220 OUT_CS(code
->code_addr
[i
]);
222 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0
, code
->alu
.length
);
223 for (i
= 0; i
< code
->alu
.length
; i
++)
224 OUT_CS(code
->alu
.inst
[i
].rgb_inst
);
226 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0
, code
->alu
.length
);
227 for (i
= 0; i
< code
->alu
.length
; i
++)
228 OUT_CS(code
->alu
.inst
[i
].rgb_addr
);
230 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0
, code
->alu
.length
);
231 for (i
= 0; i
< code
->alu
.length
; i
++)
232 OUT_CS(code
->alu
.inst
[i
].alpha_inst
);
234 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0
, code
->alu
.length
);
235 for (i
= 0; i
< code
->alu
.length
; i
++)
236 OUT_CS(code
->alu
.inst
[i
].alpha_addr
);
238 if (code
->tex
.length
) {
239 OUT_CS_REG_SEQ(R300_US_TEX_INST_0
, code
->tex
.length
);
240 for(i
= 0; i
< code
->tex
.length
; ++i
)
241 OUT_CS(code
->tex
.inst
[i
]);
247 void r300_emit_fs_constant_buffer(struct r300_context
* r300
,
248 struct rc_constant_list
* constants
)
253 if (constants
->Count
== 0)
256 BEGIN_CS(constants
->Count
* 4 + 1);
257 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, constants
->Count
* 4);
258 for(i
= 0; i
< constants
->Count
; ++i
) {
259 const float * data
= get_shader_constant(r300
,
260 &constants
->Constants
[i
],
261 &r300
->shader_constants
[PIPE_SHADER_FRAGMENT
]);
262 OUT_CS(pack_float24(data
[0]));
263 OUT_CS(pack_float24(data
[1]));
264 OUT_CS(pack_float24(data
[2]));
265 OUT_CS(pack_float24(data
[3]));
270 void r500_emit_fragment_program_code(struct r300_context
* r300
,
271 struct rX00_fragment_program_code
* generic_code
)
273 struct r500_fragment_program_code
* code
= &generic_code
->code
.r500
;
278 ((code
->inst_end
+ 1) * 6));
279 OUT_CS_REG(R500_US_CONFIG
, 0);
280 OUT_CS_REG(R500_US_PIXSIZE
, code
->max_temp_idx
);
281 OUT_CS_REG(R500_US_CODE_RANGE
,
282 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code
->inst_end
));
283 OUT_CS_REG(R500_US_CODE_OFFSET
, 0);
284 OUT_CS_REG(R500_US_CODE_ADDR
,
285 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code
->inst_end
));
287 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_INSTR
);
288 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, (code
->inst_end
+ 1) * 6);
289 for (i
= 0; i
<= code
->inst_end
; i
++) {
290 OUT_CS(code
->inst
[i
].inst0
);
291 OUT_CS(code
->inst
[i
].inst1
);
292 OUT_CS(code
->inst
[i
].inst2
);
293 OUT_CS(code
->inst
[i
].inst3
);
294 OUT_CS(code
->inst
[i
].inst4
);
295 OUT_CS(code
->inst
[i
].inst5
);
301 void r500_emit_fs_constant_buffer(struct r300_context
* r300
,
302 struct rc_constant_list
* constants
)
307 if (constants
->Count
== 0)
310 BEGIN_CS(constants
->Count
* 4 + 3);
311 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
312 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, constants
->Count
* 4);
313 for (i
= 0; i
< constants
->Count
; i
++) {
314 const float * data
= get_shader_constant(r300
,
315 &constants
->Constants
[i
],
316 &r300
->shader_constants
[PIPE_SHADER_FRAGMENT
]);
325 void r300_emit_fb_state(struct r300_context
* r300
,
326 struct pipe_framebuffer_state
* fb
)
328 struct r300_texture
* tex
;
329 struct pipe_surface
* surf
;
333 BEGIN_CS((10 * fb
->nr_cbufs
) + (fb
->zsbuf
? 10 : 0) + 4);
334 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT
,
335 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS
|
336 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
337 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
,
338 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
339 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);
341 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
343 tex
= (struct r300_texture
*)surf
->texture
;
344 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
346 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
+ (4 * i
), 1);
347 OUT_CS_RELOC(tex
->buffer
, surf
->offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
349 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0
+ (4 * i
), 1);
350 OUT_CS_RELOC(tex
->buffer
, tex
->pitch
[surf
->level
] |
351 r300_translate_colorformat(tex
->tex
.format
), 0,
352 RADEON_GEM_DOMAIN_VRAM
, 0);
354 OUT_CS_REG(R300_US_OUT_FMT_0
+ (4 * i
),
355 r300_translate_out_fmt(surf
->format
));
360 tex
= (struct r300_texture
*)surf
->texture
;
361 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
363 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
364 OUT_CS_RELOC(tex
->buffer
, surf
->offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
366 OUT_CS_REG(R300_ZB_FORMAT
, r300_translate_zsformat(tex
->tex
.format
));
368 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
369 OUT_CS_RELOC(tex
->buffer
, tex
->pitch
[surf
->level
], 0,
370 RADEON_GEM_DOMAIN_VRAM
, 0);
376 static void r300_emit_query_start(struct r300_context
*r300
)
378 struct r300_capabilities
*caps
= r300_screen(r300
->context
.screen
)->caps
;
379 struct r300_query
*query
= r300
->query_current
;
386 if (caps
->family
== CHIP_FAMILY_RV530
) {
387 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
389 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
391 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
393 query
->begin_emitted
= TRUE
;
397 static void r300_emit_query_finish(struct r300_context
*r300
,
398 struct r300_query
*query
)
400 struct r300_capabilities
* caps
= r300_screen(r300
->context
.screen
)->caps
;
403 assert(caps
->num_frag_pipes
);
405 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
406 /* I'm not so sure I like this switch, but it's hard to be elegant
407 * when there's so many special cases...
409 * So here's the basic idea. For each pipe, enable writes to it only,
410 * then put out the relocation for ZPASS_ADDR, taking into account a
411 * 4-byte offset for each pipe. RV380 and older are special; they have
412 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
413 * so there's a chipset cap for that. */
414 switch (caps
->num_frag_pipes
) {
417 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
418 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
419 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 3),
420 0, RADEON_GEM_DOMAIN_GTT
, 0);
423 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
424 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
425 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 2),
426 0, RADEON_GEM_DOMAIN_GTT
, 0);
429 /* As mentioned above, accomodate RV380 and older. */
430 OUT_CS_REG(R300_SU_REG_DEST
,
431 1 << (caps
->high_second_pipe
? 3 : 1));
432 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
433 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 1),
434 0, RADEON_GEM_DOMAIN_GTT
, 0);
437 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
438 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
439 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 0),
440 0, RADEON_GEM_DOMAIN_GTT
, 0);
443 debug_printf("r300: Implementation error: Chipset reports %d"
444 " pixel pipes!\n", caps
->num_frag_pipes
);
448 /* And, finally, reset it to normal... */
449 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
453 static void rv530_emit_query_single(struct r300_context
*r300
,
454 struct r300_query
*query
)
459 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
460 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
461 OUT_CS_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
462 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
466 static void rv530_emit_query_double(struct r300_context
*r300
,
467 struct r300_query
*query
)
472 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
473 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
474 OUT_CS_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
475 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
476 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
477 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
478 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
482 void r300_emit_query_end(struct r300_context
* r300
)
484 struct r300_capabilities
*caps
= r300_screen(r300
->context
.screen
)->caps
;
485 struct r300_query
*query
= r300
->query_current
;
490 if (query
->begin_emitted
== FALSE
)
493 if (caps
->family
== CHIP_FAMILY_RV530
) {
494 if (caps
->num_z_pipes
== 2)
495 rv530_emit_query_double(r300
, query
);
497 rv530_emit_query_single(r300
, query
);
499 r300_emit_query_finish(r300
, query
);
502 void r300_emit_rs_state(struct r300_context
* r300
, struct r300_rs_state
* rs
)
507 OUT_CS_REG(R300_VAP_CNTL_STATUS
, rs
->vap_control_status
);
508 OUT_CS_REG(R300_GA_POINT_SIZE
, rs
->point_size
);
509 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX
, 2);
510 OUT_CS(rs
->point_minmax
);
511 OUT_CS(rs
->line_control
);
512 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE
, 6);
513 OUT_CS(rs
->depth_scale_front
);
514 OUT_CS(rs
->depth_offset_front
);
515 OUT_CS(rs
->depth_scale_back
);
516 OUT_CS(rs
->depth_offset_back
);
517 OUT_CS(rs
->polygon_offset_enable
);
518 OUT_CS(rs
->cull_mode
);
519 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG
, rs
->line_stipple_config
);
520 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE
, rs
->line_stipple_value
);
521 OUT_CS_REG(R300_GA_COLOR_CONTROL
, rs
->color_control
);
522 OUT_CS_REG(R300_GA_POLY_MODE
, rs
->polygon_mode
);
526 void r300_emit_rs_block_state(struct r300_context
* r300
,
527 struct r300_rs_block
* rs
)
530 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
533 DBG(r300
, DBG_DRAW
, "r300: RS emit:\n");
536 if (r300screen
->caps
->is_r500
) {
537 OUT_CS_REG_SEQ(R500_RS_IP_0
, 8);
539 OUT_CS_REG_SEQ(R300_RS_IP_0
, 8);
541 for (i
= 0; i
< 8; i
++) {
543 DBG(r300
, DBG_DRAW
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
546 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
548 OUT_CS(rs
->inst_count
);
550 if (r300screen
->caps
->is_r500
) {
551 OUT_CS_REG_SEQ(R500_RS_INST_0
, 8);
553 OUT_CS_REG_SEQ(R300_RS_INST_0
, 8);
555 for (i
= 0; i
< 8; i
++) {
557 DBG(r300
, DBG_DRAW
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
560 DBG(r300
, DBG_DRAW
, " : count: 0x%08x inst_count: 0x%08x\n",
561 rs
->count
, rs
->inst_count
);
566 void r300_emit_scissor_state(struct r300_context
* r300
,
567 struct r300_scissor_state
* scissor
)
572 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
573 OUT_CS(scissor
->scissor_top_left
);
574 OUT_CS(scissor
->scissor_bottom_right
);
578 void r300_emit_texture(struct r300_context
* r300
,
579 struct r300_sampler_state
* sampler
,
580 struct r300_texture
* tex
,
583 uint32_t filter0
= sampler
->filter0
;
584 uint32_t format0
= tex
->state
.format0
;
585 unsigned min_level
, max_level
;
588 /* to emulate 1D textures through 2D ones correctly */
589 if (tex
->tex
.target
== PIPE_TEXTURE_1D
) {
590 filter0
&= ~R300_TX_WRAP_T_MASK
;
591 filter0
|= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE
);
594 /* determine min/max levels */
595 /* the MAX_MIP level is the largest (finest) one */
596 max_level
= MIN2(sampler
->max_lod
, tex
->tex
.last_level
);
597 min_level
= MIN2(sampler
->min_lod
, max_level
);
598 format0
|= R300_TX_NUM_LEVELS(max_level
);
599 filter0
|= R300_TX_MAX_MIP_LEVEL(min_level
);
602 OUT_CS_REG(R300_TX_FILTER0_0
+ (offset
* 4), filter0
|
604 OUT_CS_REG(R300_TX_FILTER1_0
+ (offset
* 4), sampler
->filter1
);
605 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (offset
* 4), sampler
->border_color
);
607 OUT_CS_REG(R300_TX_FORMAT0_0
+ (offset
* 4), format0
);
608 OUT_CS_REG(R300_TX_FORMAT1_0
+ (offset
* 4), tex
->state
.format1
);
609 OUT_CS_REG(R300_TX_FORMAT2_0
+ (offset
* 4), tex
->state
.format2
);
610 OUT_CS_REG_SEQ(R300_TX_OFFSET_0
+ (offset
* 4), 1);
611 OUT_CS_RELOC(tex
->buffer
, 0,
612 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0, 0);
616 /* XXX I can't read this and that's not good */
617 void r300_emit_aos(struct r300_context
* r300
, unsigned offset
)
619 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
620 struct pipe_vertex_element
*velem
= r300
->vertex_element
;
623 unsigned aos_count
= r300
->vertex_element_count
;
625 unsigned packet_size
= (aos_count
* 3 + 1) / 2;
626 BEGIN_CS(2 + packet_size
+ aos_count
* 2);
627 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
629 for (i
= 0; i
< aos_count
- 1; i
+= 2) {
630 int buf_num1
= velem
[i
].vertex_buffer_index
;
631 int buf_num2
= velem
[i
+1].vertex_buffer_index
;
632 assert(vbuf
[buf_num1
].stride
% 4 == 0 && pf_get_blocksize(velem
[i
].src_format
) % 4 == 0);
633 assert(vbuf
[buf_num2
].stride
% 4 == 0 && pf_get_blocksize(velem
[i
+1].src_format
) % 4 == 0);
634 OUT_CS((pf_get_blocksize(velem
[i
].src_format
) >> 2) | (vbuf
[buf_num1
].stride
<< 6) |
635 (pf_get_blocksize(velem
[i
+1].src_format
) << 14) | (vbuf
[buf_num2
].stride
<< 22));
636 OUT_CS(vbuf
[buf_num1
].buffer_offset
+ velem
[i
].src_offset
+
637 offset
* vbuf
[buf_num1
].stride
);
638 OUT_CS(vbuf
[buf_num2
].buffer_offset
+ velem
[i
+1].src_offset
+
639 offset
* vbuf
[buf_num2
].stride
);
642 int buf_num
= velem
[i
].vertex_buffer_index
;
643 assert(vbuf
[buf_num
].stride
% 4 == 0 && pf_get_blocksize(velem
[i
].src_format
) % 4 == 0);
644 OUT_CS((pf_get_blocksize(velem
[i
].src_format
) >> 2) | (vbuf
[buf_num
].stride
<< 6));
645 OUT_CS(vbuf
[buf_num
].buffer_offset
+ velem
[i
].src_offset
+
646 offset
* vbuf
[buf_num
].stride
);
649 /* XXX bare CS reloc */
650 for (i
= 0; i
< aos_count
; i
++) {
651 cs_winsys
->write_cs_reloc(cs_winsys
,
652 vbuf
[velem
[i
].vertex_buffer_index
].buffer
,
653 RADEON_GEM_DOMAIN_GTT
,
661 void r300_emit_draw_packet(struct r300_context
* r300
)
665 DBG(r300
, DBG_DRAW
, "r300: Preparing vertex buffer %p for render, "
666 "vertex size %d\n", r300
->vbo
,
667 r300
->vertex_info
->vinfo
.size
);
668 /* Set the pointer to our vertex buffer. The emitted values are this:
669 * PACKET3 [3D_LOAD_VBPNTR]
671 * FORMAT [size | stride << 8]
672 * OFFSET [offset into BO]
673 * VBPNTR [relocated BO]
676 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
678 OUT_CS(r300
->vertex_info
->vinfo
.size
|
679 (r300
->vertex_info
->vinfo
.size
<< 8));
680 OUT_CS(r300
->vbo_offset
);
681 OUT_CS_RELOC(r300
->vbo
, 0, RADEON_GEM_DOMAIN_GTT
, 0, 0);
686 void r300_emit_vertex_format_state(struct r300_context
* r300
)
691 DBG(r300
, DBG_DRAW
, "r300: VAP/PSC emit:\n");
694 OUT_CS_REG(R300_VAP_VTX_SIZE
, r300
->vertex_info
->vinfo
.size
);
696 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
697 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[0]);
698 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[1]);
699 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
700 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[2]);
701 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[3]);
702 for (i
= 0; i
< 4; i
++) {
703 DBG(r300
, DBG_DRAW
, " : hwfmt%d: 0x%08x\n", i
,
704 r300
->vertex_info
->vinfo
.hwfmt
[i
]);
707 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, 8);
708 for (i
= 0; i
< 8; i
++) {
709 OUT_CS(r300
->vertex_info
->vap_prog_stream_cntl
[i
]);
710 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl%d: 0x%08x\n", i
,
711 r300
->vertex_info
->vap_prog_stream_cntl
[i
]);
713 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, 8);
714 for (i
= 0; i
< 8; i
++) {
715 OUT_CS(r300
->vertex_info
->vap_prog_stream_cntl_ext
[i
]);
716 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
717 r300
->vertex_info
->vap_prog_stream_cntl_ext
[i
]);
723 void r300_emit_vertex_program_code(struct r300_context
* r300
,
724 struct r300_vertex_program_code
* code
)
727 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
728 unsigned instruction_count
= code
->length
/ 4;
730 int vtx_mem_size
= r300screen
->caps
->is_r500
? 128 : 72;
731 int input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
732 int output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
733 int temp_count
= MAX2(code
->num_temporaries
, 1);
734 int pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
735 vtx_mem_size
/ output_count
, 10);
736 int pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 6);
740 if (!r300screen
->caps
->has_tcl
) {
741 debug_printf("r300: Implementation error: emit_vertex_shader called,"
742 " but has_tcl is FALSE!\n");
746 BEGIN_CS(9 + code
->length
);
747 /* R300_VAP_PVS_CODE_CNTL_0
748 * R300_VAP_PVS_CONST_CNTL
749 * R300_VAP_PVS_CODE_CNTL_1
750 * See the r5xx docs for instructions on how to use these. */
751 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0
, 3);
752 OUT_CS(R300_PVS_FIRST_INST(0) |
753 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
754 R300_PVS_LAST_INST(instruction_count
- 1));
755 OUT_CS(R300_PVS_MAX_CONST_ADDR(code
->constants
.Count
- 1));
756 OUT_CS(instruction_count
- 1);
758 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
759 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
760 for (i
= 0; i
< code
->length
; i
++)
761 OUT_CS(code
->body
.d
[i
]);
763 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
764 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
765 R300_PVS_NUM_FPUS(r300screen
->caps
->num_vert_fpus
) |
766 R300_PVS_VF_MAX_VTX_NUM(12) |
767 (r300screen
->caps
->is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
771 void r300_emit_vertex_shader(struct r300_context
* r300
,
772 struct r300_vertex_shader
* vs
)
774 r300_emit_vertex_program_code(r300
, &vs
->code
);
777 void r300_emit_vs_constant_buffer(struct r300_context
* r300
,
778 struct rc_constant_list
* constants
)
781 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
784 if (!r300screen
->caps
->has_tcl
) {
785 debug_printf("r300: Implementation error: emit_vertex_shader called,"
786 " but has_tcl is FALSE!\n");
790 if (constants
->Count
== 0)
793 BEGIN_CS(constants
->Count
* 4 + 3);
794 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
795 (r300screen
->caps
->is_r500
?
796 R500_PVS_CONST_START
: R300_PVS_CONST_START
));
797 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, constants
->Count
* 4);
798 for (i
= 0; i
< constants
->Count
; i
++) {
799 const float * data
= get_shader_constant(r300
,
800 &constants
->Constants
[i
],
801 &r300
->shader_constants
[PIPE_SHADER_VERTEX
]);
810 void r300_emit_viewport_state(struct r300_context
* r300
,
811 struct r300_viewport_state
* viewport
)
816 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
817 OUT_CS_32F(viewport
->xscale
);
818 OUT_CS_32F(viewport
->xoffset
);
819 OUT_CS_32F(viewport
->yscale
);
820 OUT_CS_32F(viewport
->yoffset
);
821 OUT_CS_32F(viewport
->zscale
);
822 OUT_CS_32F(viewport
->zoffset
);
824 if (r300
->rs_state
->enable_vte
) {
825 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
827 OUT_CS_REG(R300_VAP_VTE_CNTL
, 0);
832 void r300_emit_texture_count(struct r300_context
* r300
)
837 OUT_CS_REG(R300_TX_ENABLE
, (1 << r300
->texture_count
) - 1);
842 void r300_flush_textures(struct r300_context
* r300
)
847 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
851 static void r300_flush_pvs(struct r300_context
* r300
)
856 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
860 /* Emit all dirty state. */
861 void r300_emit_dirty_state(struct r300_context
* r300
)
863 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
864 struct r300_texture
* tex
;
865 int i
, dirty_tex
= 0;
866 boolean invalid
= FALSE
;
868 if (!(r300
->dirty_state
)) {
872 /* Check size of CS. */
873 /* Make sure we have at least 8*1024 spare dwords. */
874 /* XXX It would be nice to know the number of dwords we really need to
876 if (!r300
->winsys
->check_cs(r300
->winsys
, 8*1024)) {
877 r300
->context
.flush(&r300
->context
, 0, NULL
);
881 r300
->winsys
->reset_bos(r300
->winsys
);
884 /* Color buffers... */
885 for (i
= 0; i
< r300
->framebuffer_state
.nr_cbufs
; i
++) {
886 tex
= (struct r300_texture
*)r300
->framebuffer_state
.cbufs
[i
]->texture
;
887 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
888 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
889 0, RADEON_GEM_DOMAIN_VRAM
)) {
890 r300
->context
.flush(&r300
->context
, 0, NULL
);
894 /* ...depth buffer... */
895 if (r300
->framebuffer_state
.zsbuf
) {
896 tex
= (struct r300_texture
*)r300
->framebuffer_state
.zsbuf
->texture
;
897 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
898 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
899 0, RADEON_GEM_DOMAIN_VRAM
)) {
900 r300
->context
.flush(&r300
->context
, 0, NULL
);
905 for (i
= 0; i
< r300
->texture_count
; i
++) {
906 tex
= r300
->textures
[i
];
909 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
910 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0)) {
911 r300
->context
.flush(&r300
->context
, 0, NULL
);
915 /* ...occlusion query buffer... */
916 if (!r300
->winsys
->add_buffer(r300
->winsys
, r300
->oqbo
,
917 0, RADEON_GEM_DOMAIN_GTT
)) {
918 r300
->context
.flush(&r300
->context
, 0, NULL
);
921 /* ...and vertex buffer. */
923 if (!r300
->winsys
->add_buffer(r300
->winsys
, r300
->vbo
,
924 RADEON_GEM_DOMAIN_GTT
, 0)) {
925 r300
->context
.flush(&r300
->context
, 0, NULL
);
929 // debug_printf("No VBO while emitting dirty state!\n");
931 if (!r300
->winsys
->validate(r300
->winsys
)) {
932 r300
->context
.flush(&r300
->context
, 0, NULL
);
935 debug_printf("r300: Stuck in validation loop, gonna quit now.");
942 if (r300
->dirty_state
& R300_NEW_QUERY
) {
943 r300_emit_query_start(r300
);
944 r300
->dirty_state
&= ~R300_NEW_QUERY
;
947 if (r300
->dirty_state
& R300_NEW_BLEND
) {
948 r300_emit_blend_state(r300
, r300
->blend_state
);
949 r300
->dirty_state
&= ~R300_NEW_BLEND
;
952 if (r300
->dirty_state
& R300_NEW_BLEND_COLOR
) {
953 r300_emit_blend_color_state(r300
, r300
->blend_color_state
);
954 r300
->dirty_state
&= ~R300_NEW_BLEND_COLOR
;
957 if (r300
->dirty_state
& R300_NEW_CLIP
) {
958 r300_emit_clip_state(r300
, &r300
->clip_state
);
959 r300
->dirty_state
&= ~R300_NEW_CLIP
;
962 if (r300
->dirty_state
& R300_NEW_DSA
) {
963 r300_emit_dsa_state(r300
, r300
->dsa_state
);
964 r300
->dirty_state
&= ~R300_NEW_DSA
;
967 if (r300
->dirty_state
& R300_NEW_FRAGMENT_SHADER
) {
968 if (r300screen
->caps
->is_r500
) {
969 r500_emit_fragment_program_code(r300
, &r300
->fs
->code
);
971 r300_emit_fragment_program_code(r300
, &r300
->fs
->code
);
973 r300
->dirty_state
&= ~R300_NEW_FRAGMENT_SHADER
;
976 if (r300
->dirty_state
& R300_NEW_FRAGMENT_SHADER_CONSTANTS
) {
977 if (r300screen
->caps
->is_r500
) {
978 r500_emit_fs_constant_buffer(r300
, &r300
->fs
->code
.constants
);
980 r300_emit_fs_constant_buffer(r300
, &r300
->fs
->code
.constants
);
982 r300
->dirty_state
&= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS
;
985 if (r300
->dirty_state
& R300_NEW_FRAMEBUFFERS
) {
986 r300_emit_fb_state(r300
, &r300
->framebuffer_state
);
987 r300
->dirty_state
&= ~R300_NEW_FRAMEBUFFERS
;
990 if (r300
->dirty_state
& R300_NEW_RASTERIZER
) {
991 r300_emit_rs_state(r300
, r300
->rs_state
);
992 r300
->dirty_state
&= ~R300_NEW_RASTERIZER
;
995 if (r300
->dirty_state
& R300_NEW_RS_BLOCK
) {
996 r300_emit_rs_block_state(r300
, r300
->rs_block
);
997 r300
->dirty_state
&= ~R300_NEW_RS_BLOCK
;
1000 if (r300
->dirty_state
& R300_NEW_SCISSOR
) {
1001 r300_emit_scissor_state(r300
, r300
->scissor_state
);
1002 r300
->dirty_state
&= ~R300_NEW_SCISSOR
;
1005 /* Samplers and textures are tracked separately but emitted together. */
1006 if (r300
->dirty_state
&
1007 (R300_ANY_NEW_SAMPLERS
| R300_ANY_NEW_TEXTURES
)) {
1008 r300_emit_texture_count(r300
);
1010 for (i
= 0; i
< MIN2(r300
->sampler_count
, r300
->texture_count
); i
++) {
1011 if (r300
->dirty_state
&
1012 ((R300_NEW_SAMPLER
<< i
) | (R300_NEW_TEXTURE
<< i
))) {
1013 if (r300
->textures
[i
])
1014 r300_emit_texture(r300
,
1015 r300
->sampler_states
[i
],
1018 r300
->dirty_state
&=
1019 ~((R300_NEW_SAMPLER
<< i
) | (R300_NEW_TEXTURE
<< i
));
1023 r300
->dirty_state
&= ~(R300_ANY_NEW_SAMPLERS
| R300_ANY_NEW_TEXTURES
);
1026 if (r300
->dirty_state
& R300_NEW_VIEWPORT
) {
1027 r300_emit_viewport_state(r300
, r300
->viewport_state
);
1028 r300
->dirty_state
&= ~R300_NEW_VIEWPORT
;
1032 r300_flush_textures(r300
);
1035 if (r300
->dirty_state
& R300_NEW_VERTEX_FORMAT
) {
1036 r300_emit_vertex_format_state(r300
);
1037 r300
->dirty_state
&= ~R300_NEW_VERTEX_FORMAT
;
1040 if (r300
->dirty_state
& (R300_NEW_VERTEX_SHADER
| R300_NEW_VERTEX_SHADER_CONSTANTS
)) {
1041 r300_flush_pvs(r300
);
1044 if (r300
->dirty_state
& R300_NEW_VERTEX_SHADER
) {
1045 r300_emit_vertex_shader(r300
, r300
->vs
);
1046 r300
->dirty_state
&= ~R300_NEW_VERTEX_SHADER
;
1049 if (r300
->dirty_state
& R300_NEW_VERTEX_SHADER_CONSTANTS
) {
1050 r300_emit_vs_constant_buffer(r300
, &r300
->vs
->code
.constants
);
1051 r300
->dirty_state
&= ~R300_NEW_VERTEX_SHADER_CONSTANTS
;
1055 assert(r300->dirty_state == 0);
1058 /* Finally, emit the VBO. */
1059 //r300_emit_vertex_buffer(r300);