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r300g: Atomize rasterizer.
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_state_derived.h"
36 #include "r300_state_inlines.h"
37 #include "r300_texture.h"
38 #include "r300_vs.h"
39
40 void r300_emit_blend_state(struct r300_context* r300, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 CS_LOCALS(r300);
44 BEGIN_CS(8);
45 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
46 if (r300->framebuffer_state.nr_cbufs) {
47 OUT_CS(blend->blend_control);
48 OUT_CS(blend->alpha_blend_control);
49 OUT_CS(blend->color_channel_mask);
50 } else {
51 OUT_CS(0);
52 OUT_CS(0);
53 OUT_CS(0);
54 /* XXX also disable fastfill here once it's supported */
55 }
56 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
57 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
58 END_CS;
59 }
60
61 void r300_emit_blend_color_state(struct r300_context* r300, void* state)
62 {
63 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
64 struct r300_screen* r300screen = r300_screen(r300->context.screen);
65 CS_LOCALS(r300);
66
67 if (r300screen->caps->is_r500) {
68 BEGIN_CS(3);
69 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
70 OUT_CS(bc->blend_color_red_alpha);
71 OUT_CS(bc->blend_color_green_blue);
72 END_CS;
73 } else {
74 BEGIN_CS(2);
75 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
76 END_CS;
77 }
78 }
79
80 void r300_emit_clip_state(struct r300_context* r300, void* state)
81 {
82 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
83 int i;
84 struct r300_screen* r300screen = r300_screen(r300->context.screen);
85 CS_LOCALS(r300);
86
87 if (r300screen->caps->has_tcl) {
88 BEGIN_CS(5 + (6 * 4));
89 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
90 (r300screen->caps->is_r500 ?
91 R500_PVS_UCP_START : R300_PVS_UCP_START));
92 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
93 for (i = 0; i < 6; i++) {
94 OUT_CS_32F(clip->ucp[i][0]);
95 OUT_CS_32F(clip->ucp[i][1]);
96 OUT_CS_32F(clip->ucp[i][2]);
97 OUT_CS_32F(clip->ucp[i][3]);
98 }
99 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
100 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
101 END_CS;
102 } else {
103 BEGIN_CS(2);
104 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
105 END_CS;
106 }
107
108 }
109
110 void r300_emit_dsa_state(struct r300_context* r300, void* state)
111 {
112 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
113 struct r300_screen* r300screen = r300_screen(r300->context.screen);
114 CS_LOCALS(r300);
115
116 BEGIN_CS(r300screen->caps->is_r500 ? 8 : 6);
117 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
118
119 /* not needed since we use the 8bit alpha ref */
120 /*if (r300screen->caps->is_r500) {
121 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
122 }*/
123
124 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
125
126 if (r300->framebuffer_state.zsbuf) {
127 OUT_CS(dsa->z_buffer_control);
128 OUT_CS(dsa->z_stencil_control);
129 } else {
130 OUT_CS(0);
131 OUT_CS(0);
132 }
133
134 OUT_CS(dsa->stencil_ref_mask);
135
136 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
137 if (r300screen->caps->is_r500) {
138 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
139 }
140 END_CS;
141 }
142
143 static const float * get_shader_constant(
144 struct r300_context * r300,
145 struct rc_constant * constant,
146 struct r300_constant_buffer * externals)
147 {
148 struct r300_viewport_state* viewport =
149 (struct r300_viewport_state*)r300->viewport_state;
150 boolean vte_enabled = viewport->vte_control & ~R300_VTX_W0_FMT;
151 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
152 struct pipe_texture *tex;
153
154 switch(constant->Type) {
155 case RC_CONSTANT_EXTERNAL:
156 return externals->constants[constant->u.External];
157
158 case RC_CONSTANT_IMMEDIATE:
159 return constant->u.Immediate;
160
161 case RC_CONSTANT_STATE:
162 switch (constant->u.State[0]) {
163 /* Factor for converting rectangle coords to
164 * normalized coords. Should only show up on non-r500. */
165 case RC_STATE_R300_TEXRECT_FACTOR:
166 tex = &r300->textures[constant->u.State[1]]->tex;
167 vec[0] = 1.0 / tex->width0;
168 vec[1] = 1.0 / tex->height0;
169 break;
170
171 /* Texture compare-fail value. */
172 /* XXX Since Gallium doesn't support GL_ARB_shadow_ambient,
173 * this is always (0,0,0,0), right? */
174 case RC_STATE_SHADOW_AMBIENT:
175 vec[3] = 0;
176 break;
177
178 case RC_STATE_R300_VIEWPORT_SCALE:
179 /* XXX argfl stop crossing state */
180 if (vte_enabled) {
181 vec[0] = viewport->xscale;
182 vec[1] = viewport->yscale;
183 vec[2] = viewport->zscale;
184 } else {
185 vec[0] = 1;
186 vec[1] = 1;
187 vec[2] = 1;
188 }
189 break;
190
191 case RC_STATE_R300_VIEWPORT_OFFSET:
192 if (vte_enabled) {
193 vec[0] = viewport->xoffset;
194 vec[1] = viewport->yoffset;
195 vec[2] = viewport->zoffset;
196 } else {
197 /* Zeros. */
198 }
199 break;
200
201 default:
202 debug_printf("r300: Implementation error: "
203 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
204 }
205 break;
206
207 default:
208 debug_printf("r300: Implementation error: "
209 "Unhandled constant type %d\n", constant->Type);
210 }
211
212 /* This should either be (0, 0, 0, 1), which should be a relatively safe
213 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
214 * state factors. */
215 return vec;
216 }
217
218 /* Convert a normal single-precision float into the 7.16 format
219 * used by the R300 fragment shader.
220 */
221 static uint32_t pack_float24(float f)
222 {
223 union {
224 float fl;
225 uint32_t u;
226 } u;
227 float mantissa;
228 int exponent;
229 uint32_t float24 = 0;
230
231 if (f == 0.0)
232 return 0;
233
234 u.fl = f;
235
236 mantissa = frexpf(f, &exponent);
237
238 /* Handle -ve */
239 if (mantissa < 0) {
240 float24 |= (1 << 23);
241 mantissa = mantissa * -1.0;
242 }
243 /* Handle exponent, bias of 63 */
244 exponent += 62;
245 float24 |= (exponent << 16);
246 /* Kill 7 LSB of mantissa */
247 float24 |= (u.u & 0x7FFFFF) >> 7;
248
249 return float24;
250 }
251
252 void r300_emit_fragment_program_code(struct r300_context* r300,
253 struct rX00_fragment_program_code* generic_code)
254 {
255 struct r300_fragment_program_code * code = &generic_code->code.r300;
256 int i;
257 CS_LOCALS(r300);
258
259 BEGIN_CS(15 +
260 code->alu.length * 4 +
261 (code->tex.length ? (1 + code->tex.length) : 0));
262
263 OUT_CS_REG(R300_US_CONFIG, code->config);
264 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
265 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
266
267 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
268 for(i = 0; i < 4; ++i)
269 OUT_CS(code->code_addr[i]);
270
271 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
272 for (i = 0; i < code->alu.length; i++)
273 OUT_CS(code->alu.inst[i].rgb_inst);
274
275 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
276 for (i = 0; i < code->alu.length; i++)
277 OUT_CS(code->alu.inst[i].rgb_addr);
278
279 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
280 for (i = 0; i < code->alu.length; i++)
281 OUT_CS(code->alu.inst[i].alpha_inst);
282
283 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
284 for (i = 0; i < code->alu.length; i++)
285 OUT_CS(code->alu.inst[i].alpha_addr);
286
287 if (code->tex.length) {
288 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
289 for(i = 0; i < code->tex.length; ++i)
290 OUT_CS(code->tex.inst[i]);
291 }
292
293 END_CS;
294 }
295
296 void r300_emit_fs_constant_buffer(struct r300_context* r300,
297 struct rc_constant_list* constants)
298 {
299 int i;
300 CS_LOCALS(r300);
301
302 if (constants->Count == 0)
303 return;
304
305 BEGIN_CS(constants->Count * 4 + 1);
306 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
307 for(i = 0; i < constants->Count; ++i) {
308 const float * data = get_shader_constant(r300,
309 &constants->Constants[i],
310 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
311 OUT_CS(pack_float24(data[0]));
312 OUT_CS(pack_float24(data[1]));
313 OUT_CS(pack_float24(data[2]));
314 OUT_CS(pack_float24(data[3]));
315 }
316 END_CS;
317 }
318
319 static void r300_emit_fragment_depth_config(struct r300_context* r300,
320 struct r300_fragment_shader* fs)
321 {
322 CS_LOCALS(r300);
323
324 BEGIN_CS(4);
325 if (r300_fragment_shader_writes_depth(fs)) {
326 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
327 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
328 } else {
329 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
330 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
331 }
332 END_CS;
333 }
334
335 void r500_emit_fragment_program_code(struct r300_context* r300,
336 struct rX00_fragment_program_code* generic_code)
337 {
338 struct r500_fragment_program_code * code = &generic_code->code.r500;
339 int i;
340 CS_LOCALS(r300);
341
342 BEGIN_CS(13 +
343 ((code->inst_end + 1) * 6));
344 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
345 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
346 OUT_CS_REG(R500_US_CODE_RANGE,
347 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
348 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
349 OUT_CS_REG(R500_US_CODE_ADDR,
350 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
351
352 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
353 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
354 for (i = 0; i <= code->inst_end; i++) {
355 OUT_CS(code->inst[i].inst0);
356 OUT_CS(code->inst[i].inst1);
357 OUT_CS(code->inst[i].inst2);
358 OUT_CS(code->inst[i].inst3);
359 OUT_CS(code->inst[i].inst4);
360 OUT_CS(code->inst[i].inst5);
361 }
362
363 END_CS;
364 }
365
366 void r500_emit_fs_constant_buffer(struct r300_context* r300,
367 struct rc_constant_list* constants)
368 {
369 int i;
370 CS_LOCALS(r300);
371
372 if (constants->Count == 0)
373 return;
374
375 BEGIN_CS(constants->Count * 4 + 3);
376 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
377 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
378 for (i = 0; i < constants->Count; i++) {
379 const float * data = get_shader_constant(r300,
380 &constants->Constants[i],
381 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
382 OUT_CS_32F(data[0]);
383 OUT_CS_32F(data[1]);
384 OUT_CS_32F(data[2]);
385 OUT_CS_32F(data[3]);
386 }
387 END_CS;
388 }
389
390 void r300_emit_fb_state(struct r300_context* r300,
391 struct pipe_framebuffer_state* fb)
392 {
393 struct r300_texture* tex;
394 struct pipe_surface* surf;
395 int i;
396 CS_LOCALS(r300);
397
398 /* Shouldn't fail unless there is a bug in the state tracker. */
399 assert(fb->nr_cbufs <= 4);
400
401 BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
402 (fb->zsbuf ? 10 : 0) + 6);
403
404 /* Flush and free renderbuffer caches. */
405 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
406 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
407 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
408 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
409 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
410 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
411
412 /* Set the number of colorbuffers. */
413 OUT_CS_REG(R300_RB3D_CCTL, R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
414
415 /* Set up colorbuffers. */
416 for (i = 0; i < fb->nr_cbufs; i++) {
417 surf = fb->cbufs[i];
418 tex = (struct r300_texture*)surf->texture;
419 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
420
421 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
422 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
423
424 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
425 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
426 r300_translate_colorformat(tex->tex.format), 0,
427 RADEON_GEM_DOMAIN_VRAM, 0);
428
429 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
430 r300_translate_out_fmt(surf->format));
431 }
432
433 /* Disable unused colorbuffers. */
434 for (; i < 4; i++) {
435 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
436 }
437
438 /* Set up a zbuffer. */
439 if (fb->zsbuf) {
440 surf = fb->zsbuf;
441 tex = (struct r300_texture*)surf->texture;
442 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
443
444 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
445 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
446
447 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
448
449 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
450 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level], 0,
451 RADEON_GEM_DOMAIN_VRAM, 0);
452 }
453
454 END_CS;
455 }
456
457 static void r300_emit_query_start(struct r300_context *r300)
458 {
459 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
460 struct r300_query *query = r300->query_current;
461 CS_LOCALS(r300);
462
463 if (!query)
464 return;
465
466 BEGIN_CS(4);
467 if (caps->family == CHIP_FAMILY_RV530) {
468 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
469 } else {
470 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
471 }
472 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
473 END_CS;
474 query->begin_emitted = TRUE;
475 }
476
477
478 static void r300_emit_query_finish(struct r300_context *r300,
479 struct r300_query *query)
480 {
481 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
482 CS_LOCALS(r300);
483
484 assert(caps->num_frag_pipes);
485
486 BEGIN_CS(6 * caps->num_frag_pipes + 2);
487 /* I'm not so sure I like this switch, but it's hard to be elegant
488 * when there's so many special cases...
489 *
490 * So here's the basic idea. For each pipe, enable writes to it only,
491 * then put out the relocation for ZPASS_ADDR, taking into account a
492 * 4-byte offset for each pipe. RV380 and older are special; they have
493 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
494 * so there's a chipset cap for that. */
495 switch (caps->num_frag_pipes) {
496 case 4:
497 /* pipe 3 only */
498 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
499 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
500 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
501 0, RADEON_GEM_DOMAIN_GTT, 0);
502 case 3:
503 /* pipe 2 only */
504 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
505 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
506 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
507 0, RADEON_GEM_DOMAIN_GTT, 0);
508 case 2:
509 /* pipe 1 only */
510 /* As mentioned above, accomodate RV380 and older. */
511 OUT_CS_REG(R300_SU_REG_DEST,
512 1 << (caps->high_second_pipe ? 3 : 1));
513 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
514 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
515 0, RADEON_GEM_DOMAIN_GTT, 0);
516 case 1:
517 /* pipe 0 only */
518 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
519 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
520 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
521 0, RADEON_GEM_DOMAIN_GTT, 0);
522 break;
523 default:
524 debug_printf("r300: Implementation error: Chipset reports %d"
525 " pixel pipes!\n", caps->num_frag_pipes);
526 assert(0);
527 }
528
529 /* And, finally, reset it to normal... */
530 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
531 END_CS;
532 }
533
534 static void rv530_emit_query_single(struct r300_context *r300,
535 struct r300_query *query)
536 {
537 CS_LOCALS(r300);
538
539 BEGIN_CS(8);
540 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
541 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
542 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
543 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
544 END_CS;
545 }
546
547 static void rv530_emit_query_double(struct r300_context *r300,
548 struct r300_query *query)
549 {
550 CS_LOCALS(r300);
551
552 BEGIN_CS(14);
553 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
554 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
555 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
556 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
557 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
558 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
559 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
560 END_CS;
561 }
562
563 void r300_emit_query_end(struct r300_context* r300)
564 {
565 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
566 struct r300_query *query = r300->query_current;
567
568 if (!query)
569 return;
570
571 if (query->begin_emitted == FALSE)
572 return;
573
574 if (caps->family == CHIP_FAMILY_RV530) {
575 if (caps->num_z_pipes == 2)
576 rv530_emit_query_double(r300, query);
577 else
578 rv530_emit_query_single(r300, query);
579 } else
580 r300_emit_query_finish(r300, query);
581 }
582
583 void r300_emit_rs_state(struct r300_context* r300, void* state)
584 {
585 struct r300_rs_state* rs = (struct r300_rs_state*)state;
586 CS_LOCALS(r300);
587
588 BEGIN_CS(22);
589 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
590 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
591 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
592 OUT_CS(rs->point_minmax);
593 OUT_CS(rs->line_control);
594 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
595 OUT_CS(rs->depth_scale_front);
596 OUT_CS(rs->depth_offset_front);
597 OUT_CS(rs->depth_scale_back);
598 OUT_CS(rs->depth_offset_back);
599 OUT_CS(rs->polygon_offset_enable);
600 OUT_CS(rs->cull_mode);
601 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
602 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
603 OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
604 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
605 END_CS;
606 }
607
608 void r300_emit_rs_block_state(struct r300_context* r300,
609 struct r300_rs_block* rs)
610 {
611 int i;
612 struct r300_screen* r300screen = r300_screen(r300->context.screen);
613 CS_LOCALS(r300);
614
615 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
616
617 BEGIN_CS(21);
618 if (r300screen->caps->is_r500) {
619 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
620 } else {
621 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
622 }
623 for (i = 0; i < 8; i++) {
624 OUT_CS(rs->ip[i]);
625 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
626 }
627
628 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
629 OUT_CS(rs->count);
630 OUT_CS(rs->inst_count);
631
632 if (r300screen->caps->is_r500) {
633 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
634 } else {
635 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
636 }
637 for (i = 0; i < 8; i++) {
638 OUT_CS(rs->inst[i]);
639 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
640 }
641
642 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
643 rs->count, rs->inst_count);
644
645 END_CS;
646 }
647
648 static void r300_emit_scissor_regs(struct r300_context* r300,
649 struct r300_scissor_regs* scissor)
650 {
651 CS_LOCALS(r300);
652
653 BEGIN_CS(3);
654 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
655 OUT_CS(scissor->top_left);
656 OUT_CS(scissor->bottom_right);
657 END_CS;
658 }
659
660 void r300_emit_scissor_state(struct r300_context* r300,
661 struct r300_scissor_state* scissor)
662 {
663 /* XXX argfl! */
664 if (((struct r300_rs_state*)r300->rs_state.state)->rs.scissor) {
665 r300_emit_scissor_regs(r300, &scissor->scissor);
666 } else {
667 r300_emit_scissor_regs(r300, &scissor->framebuffer);
668 }
669 }
670
671 void r300_emit_texture(struct r300_context* r300,
672 struct r300_sampler_state* sampler,
673 struct r300_texture* tex,
674 unsigned offset)
675 {
676 uint32_t filter0 = sampler->filter0;
677 uint32_t format0 = tex->state.format0;
678 unsigned min_level, max_level;
679 CS_LOCALS(r300);
680
681 /* to emulate 1D textures through 2D ones correctly */
682 if (tex->tex.target == PIPE_TEXTURE_1D) {
683 filter0 &= ~R300_TX_WRAP_T_MASK;
684 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
685 }
686
687 /* determine min/max levels */
688 /* the MAX_MIP level is the largest (finest) one */
689 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
690 min_level = MIN2(sampler->min_lod, max_level);
691 format0 |= R300_TX_NUM_LEVELS(max_level);
692 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
693
694 BEGIN_CS(16);
695 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
696 (offset << 28));
697 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
698 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
699
700 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
701 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
702 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
703 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
704 OUT_CS_RELOC(tex->buffer, 0,
705 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
706 END_CS;
707 }
708
709 static boolean r300_validate_aos(struct r300_context *r300)
710 {
711 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
712 struct pipe_vertex_element *velem = r300->vertex_element;
713 int i;
714
715 /* Check if formats and strides are aligned to the size of DWORD. */
716 for (i = 0; i < r300->vertex_element_count; i++) {
717 if (vbuf[velem[i].vertex_buffer_index].stride % 4 != 0 ||
718 util_format_get_blocksize(velem[i].src_format) % 4 != 0) {
719 return FALSE;
720 }
721 }
722 return TRUE;
723 }
724
725 void r300_emit_aos(struct r300_context* r300, unsigned offset)
726 {
727 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
728 struct pipe_vertex_element *velem = r300->vertex_element;
729 int i;
730 unsigned size1, size2, aos_count = r300->vertex_element_count;
731 unsigned packet_size = (aos_count * 3 + 1) / 2;
732 CS_LOCALS(r300);
733
734 /* XXX Move this checking to a more approriate place. */
735 if (!r300_validate_aos(r300)) {
736 /* XXX We should fallback using Draw. */
737 assert(0);
738 }
739
740 BEGIN_CS(2 + packet_size + aos_count * 2);
741 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
742 OUT_CS(aos_count);
743
744 for (i = 0; i < aos_count - 1; i += 2) {
745 vb1 = &vbuf[velem[i].vertex_buffer_index];
746 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
747 size1 = util_format_get_blocksize(velem[i].src_format);
748 size2 = util_format_get_blocksize(velem[i+1].src_format);
749
750 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
751 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
752 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
753 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
754 }
755
756 if (aos_count & 1) {
757 vb1 = &vbuf[velem[i].vertex_buffer_index];
758 size1 = util_format_get_blocksize(velem[i].src_format);
759
760 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
761 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
762 }
763
764 for (i = 0; i < aos_count; i++) {
765 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
766 RADEON_GEM_DOMAIN_GTT, 0, 0);
767 }
768 END_CS;
769 }
770
771 #if 0
772 void r300_emit_draw_packet(struct r300_context* r300)
773 {
774 CS_LOCALS(r300);
775
776 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
777 "vertex size %d\n", r300->vbo,
778 r300->vertex_info->vinfo.size);
779 /* Set the pointer to our vertex buffer. The emitted values are this:
780 * PACKET3 [3D_LOAD_VBPNTR]
781 * COUNT [1]
782 * FORMAT [size | stride << 8]
783 * OFFSET [offset into BO]
784 * VBPNTR [relocated BO]
785 */
786 BEGIN_CS(7);
787 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
788 OUT_CS(1);
789 OUT_CS(r300->vertex_info->vinfo.size |
790 (r300->vertex_info->vinfo.size << 8));
791 OUT_CS(r300->vbo_offset);
792 OUT_CS_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
793 END_CS;
794 }
795 #endif
796
797 void r300_emit_vertex_format_state(struct r300_context* r300)
798 {
799 int i;
800 CS_LOCALS(r300);
801
802 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
803
804 BEGIN_CS(26);
805 OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info->vinfo.size);
806
807 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
808 OUT_CS(r300->vertex_info->vinfo.hwfmt[0]);
809 OUT_CS(r300->vertex_info->vinfo.hwfmt[1]);
810 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
811 OUT_CS(r300->vertex_info->vinfo.hwfmt[2]);
812 OUT_CS(r300->vertex_info->vinfo.hwfmt[3]);
813 for (i = 0; i < 4; i++) {
814 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
815 r300->vertex_info->vinfo.hwfmt[i]);
816 }
817
818 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
819 for (i = 0; i < 8; i++) {
820 OUT_CS(r300->vertex_info->vap_prog_stream_cntl[i]);
821 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
822 r300->vertex_info->vap_prog_stream_cntl[i]);
823 }
824 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
825 for (i = 0; i < 8; i++) {
826 OUT_CS(r300->vertex_info->vap_prog_stream_cntl_ext[i]);
827 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
828 r300->vertex_info->vap_prog_stream_cntl_ext[i]);
829 }
830 END_CS;
831 }
832
833
834 void r300_emit_vertex_program_code(struct r300_context* r300,
835 struct r300_vertex_program_code* code)
836 {
837 int i;
838 struct r300_screen* r300screen = r300_screen(r300->context.screen);
839 unsigned instruction_count = code->length / 4;
840
841 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
842 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
843 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
844 int temp_count = MAX2(code->num_temporaries, 1);
845 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
846 vtx_mem_size / output_count, 10);
847 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
848
849 CS_LOCALS(r300);
850
851 if (!r300screen->caps->has_tcl) {
852 debug_printf("r300: Implementation error: emit_vertex_shader called,"
853 " but has_tcl is FALSE!\n");
854 return;
855 }
856
857 BEGIN_CS(9 + code->length);
858 /* R300_VAP_PVS_CODE_CNTL_0
859 * R300_VAP_PVS_CONST_CNTL
860 * R300_VAP_PVS_CODE_CNTL_1
861 * See the r5xx docs for instructions on how to use these. */
862 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
863 OUT_CS(R300_PVS_FIRST_INST(0) |
864 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
865 R300_PVS_LAST_INST(instruction_count - 1));
866 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
867 OUT_CS(instruction_count - 1);
868
869 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
870 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
871 for (i = 0; i < code->length; i++)
872 OUT_CS(code->body.d[i]);
873
874 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
875 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
876 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
877 R300_PVS_VF_MAX_VTX_NUM(12) |
878 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
879 END_CS;
880 }
881
882 void r300_emit_vertex_shader(struct r300_context* r300,
883 struct r300_vertex_shader* vs)
884 {
885 r300_emit_vertex_program_code(r300, &vs->code);
886 }
887
888 void r300_emit_vs_constant_buffer(struct r300_context* r300,
889 struct rc_constant_list* constants)
890 {
891 int i;
892 struct r300_screen* r300screen = r300_screen(r300->context.screen);
893 CS_LOCALS(r300);
894
895 if (!r300screen->caps->has_tcl) {
896 debug_printf("r300: Implementation error: emit_vertex_shader called,"
897 " but has_tcl is FALSE!\n");
898 return;
899 }
900
901 if (constants->Count == 0)
902 return;
903
904 BEGIN_CS(constants->Count * 4 + 3);
905 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
906 (r300screen->caps->is_r500 ?
907 R500_PVS_CONST_START : R300_PVS_CONST_START));
908 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
909 for (i = 0; i < constants->Count; i++) {
910 const float * data = get_shader_constant(r300,
911 &constants->Constants[i],
912 &r300->shader_constants[PIPE_SHADER_VERTEX]);
913 OUT_CS_32F(data[0]);
914 OUT_CS_32F(data[1]);
915 OUT_CS_32F(data[2]);
916 OUT_CS_32F(data[3]);
917 }
918 END_CS;
919 }
920
921 void r300_emit_viewport_state(struct r300_context* r300,
922 struct r300_viewport_state* viewport)
923 {
924 CS_LOCALS(r300);
925
926 BEGIN_CS(9);
927 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
928 OUT_CS_32F(viewport->xscale);
929 OUT_CS_32F(viewport->xoffset);
930 OUT_CS_32F(viewport->yscale);
931 OUT_CS_32F(viewport->yoffset);
932 OUT_CS_32F(viewport->zscale);
933 OUT_CS_32F(viewport->zoffset);
934
935 /* XXX words fail me. */
936 if (((struct r300_rs_state*)r300->rs_state.state)->enable_vte) {
937 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
938 } else {
939 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
940 }
941 END_CS;
942 }
943
944 void r300_emit_texture_count(struct r300_context* r300)
945 {
946 uint32_t tx_enable = 0;
947 int i;
948 CS_LOCALS(r300);
949
950 /* Notice that texture_count and sampler_count are just sizes
951 * of the respective arrays. We still have to check for the individual
952 * elements. */
953 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
954 if (r300->textures[i]) {
955 tx_enable |= 1 << i;
956 }
957 }
958
959 BEGIN_CS(2);
960 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
961 END_CS;
962
963 }
964
965 void r300_emit_ztop_state(struct r300_context* r300, void* state)
966 {
967 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
968 CS_LOCALS(r300);
969
970 BEGIN_CS(2);
971 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
972 END_CS;
973 }
974
975 void r300_flush_textures(struct r300_context* r300)
976 {
977 CS_LOCALS(r300);
978
979 BEGIN_CS(2);
980 OUT_CS_REG(R300_TX_INVALTAGS, 0);
981 END_CS;
982 }
983
984 static void r300_flush_pvs(struct r300_context* r300)
985 {
986 CS_LOCALS(r300);
987
988 BEGIN_CS(2);
989 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
990 END_CS;
991 }
992
993 /* Emit all dirty state. */
994 void r300_emit_dirty_state(struct r300_context* r300)
995 {
996 struct r300_screen* r300screen = r300_screen(r300->context.screen);
997 struct r300_texture* tex;
998 struct r300_atom* atom;
999 int i, dirty_tex = 0;
1000 boolean invalid = FALSE;
1001
1002 /* Check size of CS. */
1003 /* Make sure we have at least 8*1024 spare dwords. */
1004 /* XXX It would be nice to know the number of dwords we really need to
1005 * XXX emit. */
1006 if (!r300->winsys->check_cs(r300->winsys, 8*1024)) {
1007 r300->context.flush(&r300->context, 0, NULL);
1008 }
1009
1010 /* Clean out BOs. */
1011 r300->winsys->reset_bos(r300->winsys);
1012
1013 validate:
1014 /* Color buffers... */
1015 for (i = 0; i < r300->framebuffer_state.nr_cbufs; i++) {
1016 tex = (struct r300_texture*)r300->framebuffer_state.cbufs[i]->texture;
1017 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1018 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1019 0, RADEON_GEM_DOMAIN_VRAM)) {
1020 r300->context.flush(&r300->context, 0, NULL);
1021 goto validate;
1022 }
1023 }
1024 /* ...depth buffer... */
1025 if (r300->framebuffer_state.zsbuf) {
1026 tex = (struct r300_texture*)r300->framebuffer_state.zsbuf->texture;
1027 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1028 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1029 0, RADEON_GEM_DOMAIN_VRAM)) {
1030 r300->context.flush(&r300->context, 0, NULL);
1031 goto validate;
1032 }
1033 }
1034 /* ...textures... */
1035 for (i = 0; i < r300->texture_count; i++) {
1036 tex = r300->textures[i];
1037 if (!tex)
1038 continue;
1039 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1040 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1041 r300->context.flush(&r300->context, 0, NULL);
1042 goto validate;
1043 }
1044 }
1045 /* ...occlusion query buffer... */
1046 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1047 0, RADEON_GEM_DOMAIN_GTT)) {
1048 r300->context.flush(&r300->context, 0, NULL);
1049 goto validate;
1050 }
1051 /* ...and vertex buffer. */
1052 if (r300->vbo) {
1053 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1054 RADEON_GEM_DOMAIN_GTT, 0)) {
1055 r300->context.flush(&r300->context, 0, NULL);
1056 goto validate;
1057 }
1058 } else {
1059 /* debug_printf("No VBO while emitting dirty state!\n"); */
1060 }
1061 if (!r300->winsys->validate(r300->winsys)) {
1062 r300->context.flush(&r300->context, 0, NULL);
1063 if (invalid) {
1064 /* Well, hell. */
1065 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1066 exit(1);
1067 }
1068 invalid = TRUE;
1069 goto validate;
1070 }
1071
1072 if (r300->dirty_state & R300_NEW_QUERY) {
1073 r300_emit_query_start(r300);
1074 r300->dirty_state &= ~R300_NEW_QUERY;
1075 }
1076
1077 foreach(atom, &r300->atom_list) {
1078 if (atom->dirty) {
1079 atom->emit(r300, atom->state);
1080 atom->dirty = FALSE;
1081 }
1082 }
1083
1084 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1085 r300_emit_fragment_depth_config(r300, r300->fs);
1086 if (r300screen->caps->is_r500) {
1087 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1088 } else {
1089 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1090 }
1091 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1092 }
1093
1094 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1095 if (r300screen->caps->is_r500) {
1096 r500_emit_fs_constant_buffer(r300,
1097 &r300->fs->shader->code.constants);
1098 } else {
1099 r300_emit_fs_constant_buffer(r300,
1100 &r300->fs->shader->code.constants);
1101 }
1102 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1103 }
1104
1105 if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
1106 r300_emit_fb_state(r300, &r300->framebuffer_state);
1107 r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
1108 }
1109
1110 if (r300->dirty_state & R300_NEW_RS_BLOCK) {
1111 r300_emit_rs_block_state(r300, r300->rs_block);
1112 r300->dirty_state &= ~R300_NEW_RS_BLOCK;
1113 }
1114
1115 if (r300->dirty_state & R300_NEW_SCISSOR) {
1116 r300_emit_scissor_state(r300, r300->scissor_state);
1117 r300->dirty_state &= ~R300_NEW_SCISSOR;
1118 }
1119
1120 /* Samplers and textures are tracked separately but emitted together. */
1121 if (r300->dirty_state &
1122 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1123 r300_emit_texture_count(r300);
1124
1125 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1126 if (r300->dirty_state &
1127 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1128 if (r300->textures[i])
1129 r300_emit_texture(r300,
1130 r300->sampler_states[i],
1131 r300->textures[i],
1132 i);
1133 r300->dirty_state &=
1134 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1135 dirty_tex++;
1136 }
1137 }
1138 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1139 }
1140
1141 if (r300->dirty_state & R300_NEW_VIEWPORT) {
1142 r300_emit_viewport_state(r300, r300->viewport_state);
1143 r300->dirty_state &= ~R300_NEW_VIEWPORT;
1144 }
1145
1146 if (dirty_tex) {
1147 r300_flush_textures(r300);
1148 }
1149
1150 if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
1151 r300_emit_vertex_format_state(r300);
1152 r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
1153 }
1154
1155 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1156 r300_flush_pvs(r300);
1157 }
1158
1159 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1160 r300_emit_vertex_shader(r300, r300->vs);
1161 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1162 }
1163
1164 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1165 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1166 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1167 }
1168
1169 /* XXX
1170 assert(r300->dirty_state == 0);
1171 */
1172
1173 /* Finally, emit the VBO. */
1174 /* r300_emit_vertex_buffer(r300); */
1175
1176 r300->dirty_hw++;
1177 }