2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
30 #include "r300_context.h"
32 #include "r300_emit.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
38 void r300_emit_blend_state(struct r300_context
* r300
,
39 unsigned size
, void* state
)
41 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
42 struct pipe_framebuffer_state
* fb
=
43 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
47 OUT_CS_REG(R300_RB3D_ROPCNTL
, blend
->rop
);
48 OUT_CS_REG_SEQ(R300_RB3D_CBLEND
, 3);
50 OUT_CS(blend
->blend_control
);
51 OUT_CS(blend
->alpha_blend_control
);
52 OUT_CS(blend
->color_channel_mask
);
57 /* XXX also disable fastfill here once it's supported */
59 OUT_CS_REG(R300_RB3D_DITHER_CTL
, blend
->dither
);
63 void r300_emit_blend_color_state(struct r300_context
* r300
,
64 unsigned size
, void* state
)
66 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
69 if (r300
->screen
->caps
.is_r500
) {
71 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR
, 2);
72 OUT_CS(bc
->blend_color_red_alpha
);
73 OUT_CS(bc
->blend_color_green_blue
);
77 OUT_CS_REG(R300_RB3D_BLEND_COLOR
, bc
->blend_color
);
82 void r300_emit_clip_state(struct r300_context
* r300
,
83 unsigned size
, void* state
)
85 struct pipe_clip_state
* clip
= (struct pipe_clip_state
*)state
;
89 if (r300
->screen
->caps
.has_tcl
) {
91 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
92 (r300
->screen
->caps
.is_r500
?
93 R500_PVS_UCP_START
: R300_PVS_UCP_START
));
94 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, 6 * 4);
95 for (i
= 0; i
< 6; i
++) {
96 OUT_CS_32F(clip
->ucp
[i
][0]);
97 OUT_CS_32F(clip
->ucp
[i
][1]);
98 OUT_CS_32F(clip
->ucp
[i
][2]);
99 OUT_CS_32F(clip
->ucp
[i
][3]);
101 OUT_CS_REG(R300_VAP_CLIP_CNTL
, ((1 << clip
->nr
) - 1) |
102 R300_PS_UCP_MODE_CLIP_AS_TRIFAN
);
106 OUT_CS_REG(R300_VAP_CLIP_CNTL
, R300_CLIP_DISABLE
);
112 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
114 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
115 struct pipe_framebuffer_state
* fb
=
116 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
117 struct pipe_stencil_ref stencil_ref
= r300
->stencil_ref
;
121 OUT_CS_REG(R300_FG_ALPHA_FUNC
, dsa
->alpha_function
);
122 OUT_CS_REG_SEQ(R300_ZB_CNTL
, 3);
125 OUT_CS(dsa
->z_buffer_control
);
126 OUT_CS(dsa
->z_stencil_control
);
132 OUT_CS(dsa
->stencil_ref_mask
| stencil_ref
.ref_value
[0]);
134 if (r300
->screen
->caps
.is_r500
) {
135 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF
, dsa
->stencil_ref_bf
| stencil_ref
.ref_value
[1]);
140 static const float * get_shader_constant(
141 struct r300_context
* r300
,
142 struct rc_constant
* constant
,
143 struct r300_constant_buffer
* externals
)
145 struct r300_viewport_state
* viewport
= r300
->viewport_state
.state
;
146 struct r300_textures_state
* texstate
= r300
->textures_state
.state
;
147 static float vec
[4] = { 0.0, 0.0, 0.0, 1.0 };
148 struct pipe_resource
*tex
;
150 switch(constant
->Type
) {
151 case RC_CONSTANT_EXTERNAL
:
152 return externals
->constants
[constant
->u
.External
];
154 case RC_CONSTANT_IMMEDIATE
:
155 return constant
->u
.Immediate
;
157 case RC_CONSTANT_STATE
:
158 switch (constant
->u
.State
[0]) {
159 /* Factor for converting rectangle coords to
160 * normalized coords. Should only show up on non-r500. */
161 case RC_STATE_R300_TEXRECT_FACTOR
:
162 tex
= texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
;
163 vec
[0] = 1.0 / tex
->width0
;
164 vec
[1] = 1.0 / tex
->height0
;
167 /* Texture compare-fail value. Shouldn't ever show up, but if
168 * it does, we'll be ready. */
169 case RC_STATE_SHADOW_AMBIENT
:
173 case RC_STATE_R300_VIEWPORT_SCALE
:
174 vec
[0] = viewport
->xscale
;
175 vec
[1] = viewport
->yscale
;
176 vec
[2] = viewport
->zscale
;
179 case RC_STATE_R300_VIEWPORT_OFFSET
:
180 vec
[0] = viewport
->xoffset
;
181 vec
[1] = viewport
->yoffset
;
182 vec
[2] = viewport
->zoffset
;
186 fprintf(stderr
, "r300: Implementation error: "
187 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
192 fprintf(stderr
, "r300: Implementation error: "
193 "Unhandled constant type %d\n", constant
->Type
);
196 /* This should either be (0, 0, 0, 1), which should be a relatively safe
197 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
202 /* Convert a normal single-precision float into the 7.16 format
203 * used by the R300 fragment shader.
205 static uint32_t pack_float24(float f
)
213 uint32_t float24
= 0;
220 mantissa
= frexpf(f
, &exponent
);
224 float24
|= (1 << 23);
225 mantissa
= mantissa
* -1.0;
227 /* Handle exponent, bias of 63 */
229 float24
|= (exponent
<< 16);
230 /* Kill 7 LSB of mantissa */
231 float24
|= (u
.u
& 0x7FFFFF) >> 7;
236 void r300_emit_fragment_program_code(struct r300_context
* r300
,
237 struct rX00_fragment_program_code
* generic_code
)
239 struct r300_fragment_program_code
* code
= &generic_code
->code
.r300
;
244 code
->alu
.length
* 4 +
245 (code
->tex
.length
? (1 + code
->tex
.length
) : 0));
247 OUT_CS_REG(R300_US_CONFIG
, code
->config
);
248 OUT_CS_REG(R300_US_PIXSIZE
, code
->pixsize
);
249 OUT_CS_REG(R300_US_CODE_OFFSET
, code
->code_offset
);
251 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0
, 4);
252 for(i
= 0; i
< 4; ++i
)
253 OUT_CS(code
->code_addr
[i
]);
255 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0
, code
->alu
.length
);
256 for (i
= 0; i
< code
->alu
.length
; i
++)
257 OUT_CS(code
->alu
.inst
[i
].rgb_inst
);
259 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0
, code
->alu
.length
);
260 for (i
= 0; i
< code
->alu
.length
; i
++)
261 OUT_CS(code
->alu
.inst
[i
].rgb_addr
);
263 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0
, code
->alu
.length
);
264 for (i
= 0; i
< code
->alu
.length
; i
++)
265 OUT_CS(code
->alu
.inst
[i
].alpha_inst
);
267 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0
, code
->alu
.length
);
268 for (i
= 0; i
< code
->alu
.length
; i
++)
269 OUT_CS(code
->alu
.inst
[i
].alpha_addr
);
271 if (code
->tex
.length
) {
272 OUT_CS_REG_SEQ(R300_US_TEX_INST_0
, code
->tex
.length
);
273 for(i
= 0; i
< code
->tex
.length
; ++i
)
274 OUT_CS(code
->tex
.inst
[i
]);
280 void r300_emit_fs_constant_buffer(struct r300_context
* r300
,
281 struct rc_constant_list
* constants
)
286 if (constants
->Count
== 0)
289 BEGIN_CS(constants
->Count
* 4 + 1);
290 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, constants
->Count
* 4);
291 for(i
= 0; i
< constants
->Count
; ++i
) {
292 const float * data
= get_shader_constant(r300
,
293 &constants
->Constants
[i
],
294 &r300
->shader_constants
[PIPE_SHADER_FRAGMENT
]);
295 OUT_CS(pack_float24(data
[0]));
296 OUT_CS(pack_float24(data
[1]));
297 OUT_CS(pack_float24(data
[2]));
298 OUT_CS(pack_float24(data
[3]));
303 static void r300_emit_fragment_depth_config(struct r300_context
* r300
,
304 struct r300_fragment_shader
* fs
)
309 if (r300_fragment_shader_writes_depth(fs
)) {
310 OUT_CS_REG(R300_FG_DEPTH_SRC
, R300_FG_DEPTH_SRC_SHADER
);
311 OUT_CS_REG(R300_US_W_FMT
, R300_W_FMT_W24
| R300_W_SRC_US
);
313 OUT_CS_REG(R300_FG_DEPTH_SRC
, R300_FG_DEPTH_SRC_SCAN
);
314 OUT_CS_REG(R300_US_W_FMT
, R300_W_FMT_W0
| R300_W_SRC_US
);
319 void r500_emit_fragment_program_code(struct r300_context
* r300
,
320 struct rX00_fragment_program_code
* generic_code
)
322 struct r500_fragment_program_code
* code
= &generic_code
->code
.r500
;
327 ((code
->inst_end
+ 1) * 6));
328 OUT_CS_REG(R500_US_CONFIG
, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO
);
329 OUT_CS_REG(R500_US_PIXSIZE
, code
->max_temp_idx
);
330 OUT_CS_REG(R500_US_CODE_RANGE
,
331 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code
->inst_end
));
332 OUT_CS_REG(R500_US_CODE_OFFSET
, 0);
333 OUT_CS_REG(R500_US_CODE_ADDR
,
334 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code
->inst_end
));
336 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_INSTR
);
337 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, (code
->inst_end
+ 1) * 6);
338 for (i
= 0; i
<= code
->inst_end
; i
++) {
339 OUT_CS(code
->inst
[i
].inst0
);
340 OUT_CS(code
->inst
[i
].inst1
);
341 OUT_CS(code
->inst
[i
].inst2
);
342 OUT_CS(code
->inst
[i
].inst3
);
343 OUT_CS(code
->inst
[i
].inst4
);
344 OUT_CS(code
->inst
[i
].inst5
);
350 void r500_emit_fs_constant_buffer(struct r300_context
* r300
,
351 struct rc_constant_list
* constants
)
356 if (constants
->Count
== 0)
359 BEGIN_CS(constants
->Count
* 4 + 3);
360 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
361 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, constants
->Count
* 4);
362 for (i
= 0; i
< constants
->Count
; i
++) {
363 const float * data
= get_shader_constant(r300
,
364 &constants
->Constants
[i
],
365 &r300
->shader_constants
[PIPE_SHADER_FRAGMENT
]);
374 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
376 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
377 struct r300_texture
* tex
;
378 struct pipe_surface
* surf
;
384 /* Flush and free renderbuffer caches. */
385 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT
,
386 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS
|
387 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
388 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
,
389 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
390 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);
392 /* Set the number of colorbuffers. */
393 if (fb
->nr_cbufs
> 1) {
394 if (r300
->screen
->caps
.is_r500
) {
395 OUT_CS_REG(R300_RB3D_CCTL
,
396 R300_RB3D_CCTL_NUM_MULTIWRITES(fb
->nr_cbufs
) |
397 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
);
399 OUT_CS_REG(R300_RB3D_CCTL
,
400 R300_RB3D_CCTL_NUM_MULTIWRITES(fb
->nr_cbufs
));
403 OUT_CS_REG(R300_RB3D_CCTL
, 0x0);
406 /* Set up colorbuffers. */
407 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
409 tex
= r300_texture(surf
->texture
);
410 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
412 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
+ (4 * i
), 1);
413 OUT_CS_TEX_RELOC(tex
, surf
->offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
415 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0
+ (4 * i
), 1);
416 OUT_CS_TEX_RELOC(tex
, tex
->fb_state
.colorpitch
[surf
->level
],
417 0, RADEON_GEM_DOMAIN_VRAM
, 0);
419 OUT_CS_REG(R300_US_OUT_FMT_0
+ (4 * i
), tex
->fb_state
.us_out_fmt
);
422 OUT_CS_REG(R300_US_OUT_FMT_0
+ (4 * i
), R300_US_OUT_FMT_UNUSED
);
425 /* Set up a zbuffer. */
428 tex
= r300_texture(surf
->texture
);
429 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
431 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
432 OUT_CS_TEX_RELOC(tex
, surf
->offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
434 OUT_CS_REG(R300_ZB_FORMAT
, tex
->fb_state
.zb_format
);
436 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
437 OUT_CS_TEX_RELOC(tex
, tex
->fb_state
.depthpitch
[surf
->level
],
438 0, RADEON_GEM_DOMAIN_VRAM
, 0);
441 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
442 if (r300
->screen
->caps
.is_r500
) {
444 OUT_CS(((fb
->width
- 1) << R300_SCISSORS_X_SHIFT
) |
445 ((fb
->height
- 1) << R300_SCISSORS_Y_SHIFT
));
447 OUT_CS((1440 << R300_SCISSORS_X_SHIFT
) |
448 (1440 << R300_SCISSORS_Y_SHIFT
));
449 OUT_CS(((fb
->width
+ 1440-1) << R300_SCISSORS_X_SHIFT
) |
450 ((fb
->height
+ 1440-1) << R300_SCISSORS_Y_SHIFT
));
452 OUT_CS_REG(R300_GA_POINT_MINMAX
,
453 (MAX2(fb
->width
, fb
->height
) * 6) << R300_GA_POINT_MINMAX_MAX_SHIFT
);
457 void r300_emit_query_start(struct r300_context
*r300
)
459 struct r300_query
*query
= r300
->query_current
;
466 if (r300
->screen
->caps
.family
== CHIP_FAMILY_RV530
) {
467 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
469 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
471 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
473 query
->begin_emitted
= TRUE
;
477 static void r300_emit_query_finish(struct r300_context
*r300
,
478 struct r300_query
*query
)
480 struct r300_capabilities
* caps
= &r300
->screen
->caps
;
483 assert(caps
->num_frag_pipes
);
485 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
486 /* I'm not so sure I like this switch, but it's hard to be elegant
487 * when there's so many special cases...
489 * So here's the basic idea. For each pipe, enable writes to it only,
490 * then put out the relocation for ZPASS_ADDR, taking into account a
491 * 4-byte offset for each pipe. RV380 and older are special; they have
492 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
493 * so there's a chipset cap for that. */
494 switch (caps
->num_frag_pipes
) {
497 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
498 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
499 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 3),
500 0, RADEON_GEM_DOMAIN_GTT
, 0);
503 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
504 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
505 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 2),
506 0, RADEON_GEM_DOMAIN_GTT
, 0);
509 /* As mentioned above, accomodate RV380 and older. */
510 OUT_CS_REG(R300_SU_REG_DEST
,
511 1 << (caps
->high_second_pipe
? 3 : 1));
512 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
513 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 1),
514 0, RADEON_GEM_DOMAIN_GTT
, 0);
517 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
518 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
519 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 0),
520 0, RADEON_GEM_DOMAIN_GTT
, 0);
523 fprintf(stderr
, "r300: Implementation error: Chipset reports %d"
524 " pixel pipes!\n", caps
->num_frag_pipes
);
528 /* And, finally, reset it to normal... */
529 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
533 static void rv530_emit_query_single(struct r300_context
*r300
,
534 struct r300_query
*query
)
539 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
540 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
541 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
542 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
546 static void rv530_emit_query_double(struct r300_context
*r300
,
547 struct r300_query
*query
)
552 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
553 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
554 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
555 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
556 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
557 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
558 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
562 void r300_emit_query_end(struct r300_context
* r300
)
564 struct r300_capabilities
*caps
= &r300
->screen
->caps
;
565 struct r300_query
*query
= r300
->query_current
;
570 if (query
->begin_emitted
== FALSE
)
573 if (caps
->family
== CHIP_FAMILY_RV530
) {
574 if (caps
->num_z_pipes
== 2)
575 rv530_emit_query_double(r300
, query
);
577 rv530_emit_query_single(r300
, query
);
579 r300_emit_query_finish(r300
, query
);
582 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
584 struct r300_rs_state
* rs
= (struct r300_rs_state
*)state
;
589 OUT_CS_REG(R300_VAP_CNTL_STATUS
, rs
->vap_control_status
);
591 OUT_CS_REG(R300_GB_AA_CONFIG
, rs
->antialiasing_config
);
593 OUT_CS_REG(R300_GA_POINT_SIZE
, rs
->point_size
);
594 OUT_CS_REG(R300_GA_LINE_CNTL
, rs
->line_control
);
596 if (rs
->polygon_offset_enable
) {
597 scale
= rs
->depth_scale
* 12;
598 offset
= rs
->depth_offset
;
600 switch (r300
->zbuffer_bpp
) {
609 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
616 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE
, 2);
617 OUT_CS(rs
->polygon_offset_enable
);
618 OUT_CS(rs
->cull_mode
);
619 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG
, rs
->line_stipple_config
);
620 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE
, rs
->line_stipple_value
);
621 OUT_CS_REG(R300_GA_POLY_MODE
, rs
->polygon_mode
);
622 OUT_CS_REG(R300_SC_CLIP_RULE
, rs
->clip_rule
);
626 void r300_emit_rs_block_state(struct r300_context
* r300
,
627 unsigned size
, void* state
)
629 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
631 /* It's the same for both INST and IP tables */
632 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
635 DBG(r300
, DBG_DRAW
, "r300: RS emit:\n");
638 if (r300
->screen
->caps
.is_r500
) {
639 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
641 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
643 for (i
= 0; i
< count
; i
++) {
645 DBG(r300
, DBG_DRAW
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
648 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
650 OUT_CS(rs
->inst_count
);
652 if (r300
->screen
->caps
.is_r500
) {
653 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
655 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
657 for (i
= 0; i
< count
; i
++) {
659 DBG(r300
, DBG_DRAW
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
662 DBG(r300
, DBG_DRAW
, " : count: 0x%08x inst_count: 0x%08x\n",
663 rs
->count
, rs
->inst_count
);
668 void r300_emit_scissor_state(struct r300_context
* r300
,
669 unsigned size
, void* state
)
671 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
675 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0
, 2);
676 if (r300
->screen
->caps
.is_r500
) {
677 OUT_CS((scissor
->minx
<< R300_CLIPRECT_X_SHIFT
) |
678 (scissor
->miny
<< R300_CLIPRECT_Y_SHIFT
));
679 OUT_CS(((scissor
->maxx
- 1) << R300_CLIPRECT_X_SHIFT
) |
680 ((scissor
->maxy
- 1) << R300_CLIPRECT_Y_SHIFT
));
682 OUT_CS(((scissor
->minx
+ 1440) << R300_CLIPRECT_X_SHIFT
) |
683 ((scissor
->miny
+ 1440) << R300_CLIPRECT_Y_SHIFT
));
684 OUT_CS(((scissor
->maxx
+ 1440-1) << R300_CLIPRECT_X_SHIFT
) |
685 ((scissor
->maxy
+ 1440-1) << R300_CLIPRECT_Y_SHIFT
));
690 void r300_emit_textures_state(struct r300_context
*r300
,
691 unsigned size
, void *state
)
693 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
694 struct r300_texture_sampler_state
*texstate
;
699 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
701 for (i
= 0; i
< allstate
->count
; i
++) {
702 if ((1 << i
) & allstate
->tx_enable
) {
703 texstate
= &allstate
->regs
[i
];
705 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter0
);
706 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter1
);
707 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
708 texstate
->border_color
);
710 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
.format0
);
711 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
.format1
);
712 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
.format2
);
714 OUT_CS_REG_SEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
715 OUT_CS_TEX_RELOC(r300_texture(allstate
->sampler_views
[i
]->base
.texture
),
716 texstate
->format
.tile_config
,
717 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0, 0);
723 void r300_emit_aos(struct r300_context
* r300
, unsigned offset
)
725 struct pipe_vertex_buffer
*vb1
, *vb2
, *vbuf
= r300
->vertex_buffer
;
726 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
728 unsigned size1
, size2
, aos_count
= r300
->velems
->count
;
729 unsigned packet_size
= (aos_count
* 3 + 1) / 2;
732 BEGIN_CS(2 + packet_size
+ aos_count
* 2);
733 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
736 for (i
= 0; i
< aos_count
- 1; i
+= 2) {
737 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
738 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
739 size1
= util_format_get_blocksize(velem
[i
].src_format
);
740 size2
= util_format_get_blocksize(velem
[i
+1].src_format
);
742 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
743 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
744 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
745 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
749 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
750 size1
= util_format_get_blocksize(velem
[i
].src_format
);
752 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
753 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
756 for (i
= 0; i
< aos_count
; i
++) {
757 OUT_CS_BUF_RELOC_NO_OFFSET(vbuf
[velem
[i
].vertex_buffer_index
].buffer
,
758 RADEON_GEM_DOMAIN_GTT
, 0, 0);
763 void r300_emit_vertex_buffer(struct r300_context
* r300
)
767 DBG(r300
, DBG_DRAW
, "r300: Preparing vertex buffer %p for render, "
768 "vertex size %d\n", r300
->vbo
,
769 r300
->vertex_info
.size
);
770 /* Set the pointer to our vertex buffer. The emitted values are this:
771 * PACKET3 [3D_LOAD_VBPNTR]
773 * FORMAT [size | stride << 8]
774 * OFFSET [offset into BO]
775 * VBPNTR [relocated BO]
778 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
780 OUT_CS(r300
->vertex_info
.size
|
781 (r300
->vertex_info
.size
<< 8));
782 OUT_CS(r300
->vbo_offset
);
783 OUT_CS_BUF_RELOC(r300
->vbo
, 0, RADEON_GEM_DOMAIN_GTT
, 0, 0);
787 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
788 unsigned size
, void* state
)
790 struct r300_vertex_stream_state
*streams
=
791 (struct r300_vertex_stream_state
*)state
;
795 DBG(r300
, DBG_DRAW
, "r300: PSC emit:\n");
798 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
799 for (i
= 0; i
< streams
->count
; i
++) {
800 OUT_CS(streams
->vap_prog_stream_cntl
[i
]);
801 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl%d: 0x%08x\n", i
,
802 streams
->vap_prog_stream_cntl
[i
]);
804 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
805 for (i
= 0; i
< streams
->count
; i
++) {
806 OUT_CS(streams
->vap_prog_stream_cntl_ext
[i
]);
807 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
808 streams
->vap_prog_stream_cntl_ext
[i
]);
813 void r300_emit_vap_output_state(struct r300_context
* r300
,
814 unsigned size
, void* state
)
816 struct r300_vap_output_state
*vap_out_state
=
817 (struct r300_vap_output_state
*)state
;
820 DBG(r300
, DBG_DRAW
, "r300: VAP emit:\n");
823 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
824 OUT_CS(vap_out_state
->vap_vtx_state_cntl
);
825 OUT_CS(vap_out_state
->vap_vsm_vtx_assm
);
826 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
827 OUT_CS(vap_out_state
->vap_out_vtx_fmt
[0]);
828 OUT_CS(vap_out_state
->vap_out_vtx_fmt
[1]);
832 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
837 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
841 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
843 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
844 struct r300_vertex_program_code
* code
= &vs
->code
;
845 struct r300_screen
* r300screen
= r300
->screen
;
846 unsigned instruction_count
= code
->length
/ 4;
849 unsigned vtx_mem_size
= r300screen
->caps
.is_r500
? 128 : 72;
850 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
851 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
852 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
854 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
855 vtx_mem_size
/ output_count
, 10);
856 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 6);
861 /* R300_VAP_PVS_CODE_CNTL_0
862 * R300_VAP_PVS_CONST_CNTL
863 * R300_VAP_PVS_CODE_CNTL_1
864 * See the r5xx docs for instructions on how to use these. */
865 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0
, 3);
866 OUT_CS(R300_PVS_FIRST_INST(0) |
867 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
868 R300_PVS_LAST_INST(instruction_count
- 1));
869 OUT_CS(R300_PVS_MAX_CONST_ADDR(code
->constants
.Count
- 1));
870 OUT_CS(instruction_count
- 1);
872 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
873 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
874 for (i
= 0; i
< code
->length
; i
++) {
875 OUT_CS(code
->body
.d
[i
]);
878 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
879 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
880 R300_PVS_NUM_FPUS(r300screen
->caps
.num_vert_fpus
) |
881 R300_PVS_VF_MAX_VTX_NUM(12) |
882 (r300screen
->caps
.is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
886 void r300_emit_vs_constant_buffer(struct r300_context
* r300
,
887 struct rc_constant_list
* constants
)
892 BEGIN_CS(constants
->Count
* 4 + 3);
893 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
894 (r300
->screen
->caps
.is_r500
?
895 R500_PVS_CONST_START
: R300_PVS_CONST_START
));
896 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, constants
->Count
* 4);
897 for (i
= 0; i
< constants
->Count
; i
++) {
898 const float *data
= get_shader_constant(r300
,
899 &constants
->Constants
[i
],
900 &r300
->shader_constants
[PIPE_SHADER_VERTEX
]);
909 void r300_emit_viewport_state(struct r300_context
* r300
,
910 unsigned size
, void* state
)
912 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
916 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
917 OUT_CS_32F(viewport
->xscale
);
918 OUT_CS_32F(viewport
->xoffset
);
919 OUT_CS_32F(viewport
->yscale
);
920 OUT_CS_32F(viewport
->yoffset
);
921 OUT_CS_32F(viewport
->zscale
);
922 OUT_CS_32F(viewport
->zoffset
);
923 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
927 void r300_emit_ztop_state(struct r300_context
* r300
,
928 unsigned size
, void* state
)
930 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
934 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
938 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
943 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
947 void r300_emit_buffer_validate(struct r300_context
*r300
,
948 boolean do_validate_vertex_buffers
,
949 struct pipe_resource
*index_buffer
)
951 struct pipe_framebuffer_state
* fb
=
952 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
953 struct r300_textures_state
*texstate
=
954 (struct r300_textures_state
*)r300
->textures_state
.state
;
955 struct r300_texture
* tex
;
956 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
957 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
958 struct pipe_resource
*pbuf
;
960 boolean invalid
= FALSE
;
962 /* upload buffers first */
963 if (r300
->any_user_vbs
) {
964 r300_upload_user_buffers(r300
);
965 r300
->any_user_vbs
= false;
969 r300
->rws
->reset_bos(r300
->rws
);
972 /* Color buffers... */
973 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
974 tex
= r300_texture(fb
->cbufs
[i
]->texture
);
975 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
976 if (!r300_add_texture(r300
->rws
, tex
,
977 0, RADEON_GEM_DOMAIN_VRAM
)) {
978 r300
->context
.flush(&r300
->context
, 0, NULL
);
982 /* ...depth buffer... */
984 tex
= r300_texture(fb
->zsbuf
->texture
);
985 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
986 if (!r300_add_texture(r300
->rws
, tex
,
987 0, RADEON_GEM_DOMAIN_VRAM
)) {
988 r300
->context
.flush(&r300
->context
, 0, NULL
);
993 for (i
= 0; i
< texstate
->count
; i
++) {
994 if (!(texstate
->tx_enable
& (1 << i
))) {
998 tex
= r300_texture(texstate
->sampler_views
[i
]->base
.texture
);
999 if (!r300_add_texture(r300
->rws
, tex
,
1000 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0)) {
1001 r300
->context
.flush(&r300
->context
, 0, NULL
);
1005 /* ...occlusion query buffer... */
1006 if (r300
->dirty_state
& R300_NEW_QUERY
) {
1007 if (!r300_add_buffer(r300
->rws
, r300
->oqbo
,
1008 0, RADEON_GEM_DOMAIN_GTT
)) {
1009 r300
->context
.flush(&r300
->context
, 0, NULL
);
1013 /* ...vertex buffer for SWTCL path... */
1015 if (!r300_add_buffer(r300
->rws
, r300
->vbo
,
1016 RADEON_GEM_DOMAIN_GTT
, 0)) {
1017 r300
->context
.flush(&r300
->context
, 0, NULL
);
1021 /* ...vertex buffers for HWTCL path... */
1022 if (do_validate_vertex_buffers
) {
1023 for (i
= 0; i
< r300
->velems
->count
; i
++) {
1024 pbuf
= vbuf
[velem
[i
].vertex_buffer_index
].buffer
;
1026 if (!r300_add_buffer(r300
->rws
, pbuf
,
1027 RADEON_GEM_DOMAIN_GTT
, 0)) {
1028 r300
->context
.flush(&r300
->context
, 0, NULL
);
1033 /* ...and index buffer for HWTCL path. */
1035 if (!r300_add_buffer(r300
->rws
, index_buffer
,
1036 RADEON_GEM_DOMAIN_GTT
, 0)) {
1037 r300
->context
.flush(&r300
->context
, 0, NULL
);
1041 if (!r300
->rws
->validate(r300
->rws
)) {
1042 r300
->context
.flush(&r300
->context
, 0, NULL
);
1045 fprintf(stderr
, "r300: Stuck in validation loop, gonna quit now.\n");
1053 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
1055 struct r300_atom
* atom
;
1056 unsigned dwords
= 0;
1058 foreach(atom
, &r300
->atom_list
) {
1059 if (atom
->dirty
|| atom
->always_dirty
) {
1060 dwords
+= atom
->size
;
1064 /* XXX This is the compensation for the non-atomized states. */
1070 /* Emit all dirty state. */
1071 void r300_emit_dirty_state(struct r300_context
* r300
)
1073 struct r300_screen
* r300screen
= r300
->screen
;
1074 struct r300_atom
* atom
;
1076 if (r300
->dirty_state
& R300_NEW_QUERY
) {
1077 r300_emit_query_start(r300
);
1078 r300
->dirty_state
&= ~R300_NEW_QUERY
;
1081 foreach(atom
, &r300
->atom_list
) {
1082 if (atom
->dirty
|| atom
->always_dirty
) {
1083 atom
->emit(r300
, atom
->size
, atom
->state
);
1084 atom
->dirty
= FALSE
;
1088 if (r300
->dirty_state
& R300_NEW_FRAGMENT_SHADER
) {
1089 r300_emit_fragment_depth_config(r300
, r300
->fs
);
1090 if (r300screen
->caps
.is_r500
) {
1091 r500_emit_fragment_program_code(r300
, &r300
->fs
->shader
->code
);
1093 r300_emit_fragment_program_code(r300
, &r300
->fs
->shader
->code
);
1095 r300
->dirty_state
&= ~R300_NEW_FRAGMENT_SHADER
;
1098 if (r300
->dirty_state
& R300_NEW_FRAGMENT_SHADER_CONSTANTS
) {
1099 if (r300screen
->caps
.is_r500
) {
1100 r500_emit_fs_constant_buffer(r300
,
1101 &r300
->fs
->shader
->code
.constants
);
1103 r300_emit_fs_constant_buffer(r300
,
1104 &r300
->fs
->shader
->code
.constants
);
1106 r300
->dirty_state
&= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS
;
1109 if (r300
->dirty_state
& R300_NEW_VERTEX_SHADER_CONSTANTS
) {
1110 struct r300_vertex_shader
* vs
= r300
->vs_state
.state
;
1111 if (vs
->code
.constants
.Count
) {
1112 r300_emit_vs_constant_buffer(r300
, &vs
->code
.constants
);
1114 r300
->dirty_state
&= ~R300_NEW_VERTEX_SHADER_CONSTANTS
;
1118 assert(r300->dirty_state == 0);
1121 /* Emit the VBO for SWTCL. */
1122 if (!r300screen
->caps
.has_tcl
) {
1123 r300_emit_vertex_buffer(r300
);