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r300g: Start using atoms.
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_state_derived.h"
36 #include "r300_state_inlines.h"
37 #include "r300_texture.h"
38 #include "r300_vs.h"
39
40 void r300_emit_blend_state(struct r300_context* r300, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 CS_LOCALS(r300);
44 BEGIN_CS(8);
45 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
46 if (r300->framebuffer_state.nr_cbufs) {
47 OUT_CS(blend->blend_control);
48 OUT_CS(blend->alpha_blend_control);
49 OUT_CS(blend->color_channel_mask);
50 } else {
51 OUT_CS(0);
52 OUT_CS(0);
53 OUT_CS(0);
54 /* XXX also disable fastfill here once it's supported */
55 }
56 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
57 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
58 END_CS;
59 }
60
61 void r300_emit_blend_color_state(struct r300_context* r300,
62 struct r300_blend_color_state* bc)
63 {
64 struct r300_screen* r300screen = r300_screen(r300->context.screen);
65 CS_LOCALS(r300);
66
67 if (r300screen->caps->is_r500) {
68 BEGIN_CS(3);
69 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
70 OUT_CS(bc->blend_color_red_alpha);
71 OUT_CS(bc->blend_color_green_blue);
72 END_CS;
73 } else {
74 BEGIN_CS(2);
75 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
76 END_CS;
77 }
78 }
79
80 void r300_emit_clip_state(struct r300_context* r300,
81 struct pipe_clip_state* clip)
82 {
83 int i;
84 struct r300_screen* r300screen = r300_screen(r300->context.screen);
85 CS_LOCALS(r300);
86
87 if (r300screen->caps->has_tcl) {
88 BEGIN_CS(5 + (6 * 4));
89 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
90 (r300screen->caps->is_r500 ?
91 R500_PVS_UCP_START : R300_PVS_UCP_START));
92 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
93 for (i = 0; i < 6; i++) {
94 OUT_CS_32F(clip->ucp[i][0]);
95 OUT_CS_32F(clip->ucp[i][1]);
96 OUT_CS_32F(clip->ucp[i][2]);
97 OUT_CS_32F(clip->ucp[i][3]);
98 }
99 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
100 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
101 END_CS;
102 } else {
103 BEGIN_CS(2);
104 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
105 END_CS;
106 }
107
108 }
109
110 void r300_emit_dsa_state(struct r300_context* r300,
111 struct r300_dsa_state* dsa)
112 {
113 struct r300_screen* r300screen = r300_screen(r300->context.screen);
114 CS_LOCALS(r300);
115
116 BEGIN_CS(r300screen->caps->is_r500 ? 10 : 8);
117 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
118
119 /* not needed since we use the 8bit alpha ref */
120 /*if (r300screen->caps->is_r500) {
121 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
122 }*/
123
124 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
125
126 if (r300->framebuffer_state.zsbuf) {
127 OUT_CS(dsa->z_buffer_control);
128 OUT_CS(dsa->z_stencil_control);
129 } else {
130 OUT_CS(0);
131 OUT_CS(0);
132 }
133
134 OUT_CS(dsa->stencil_ref_mask);
135 OUT_CS_REG(R300_ZB_ZTOP, r300->ztop_state.z_buffer_top);
136
137 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
138 if (r300screen->caps->is_r500) {
139 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
140 }
141 END_CS;
142 }
143
144 static const float * get_shader_constant(
145 struct r300_context * r300,
146 struct rc_constant * constant,
147 struct r300_constant_buffer * externals)
148 {
149 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
150 struct pipe_texture *tex;
151
152 switch(constant->Type) {
153 case RC_CONSTANT_EXTERNAL:
154 return externals->constants[constant->u.External];
155
156 case RC_CONSTANT_IMMEDIATE:
157 return constant->u.Immediate;
158
159 case RC_CONSTANT_STATE:
160 switch (constant->u.State[0]) {
161 /* Factor for converting rectangle coords to
162 * normalized coords. Should only show up on non-r500. */
163 case RC_STATE_R300_TEXRECT_FACTOR:
164 tex = &r300->textures[constant->u.State[1]]->tex;
165 vec[0] = 1.0 / tex->width0;
166 vec[1] = 1.0 / tex->height0;
167 break;
168
169 /* Texture compare-fail value. */
170 /* XXX Since Gallium doesn't support GL_ARB_shadow_ambient,
171 * this is always (0,0,0,0). */
172 case RC_STATE_SHADOW_AMBIENT:
173 vec[3] = 0;
174 break;
175
176 case RC_STATE_R300_VIEWPORT_SCALE:
177 if (r300->rs_state->enable_vte) {
178 vec[0] = r300->viewport_state->xscale;
179 vec[1] = r300->viewport_state->yscale;
180 vec[2] = r300->viewport_state->zscale;
181 } else {
182 vec[0] = 1;
183 vec[1] = 1;
184 vec[2] = 1;
185 }
186 break;
187
188 case RC_STATE_R300_VIEWPORT_OFFSET:
189 if (r300->rs_state->enable_vte) {
190 vec[0] = r300->viewport_state->xoffset;
191 vec[1] = r300->viewport_state->yoffset;
192 vec[2] = r300->viewport_state->zoffset;
193 } else {
194 /* Zeros. */
195 }
196 break;
197
198 default:
199 debug_printf("r300: Implementation error: "
200 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
201 }
202 break;
203
204 default:
205 debug_printf("r300: Implementation error: "
206 "Unhandled constant type %d\n", constant->Type);
207 }
208
209 /* This should either be (0, 0, 0, 1), which should be a relatively safe
210 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
211 * state factors. */
212 return vec;
213 }
214
215 /* Convert a normal single-precision float into the 7.16 format
216 * used by the R300 fragment shader.
217 */
218 static uint32_t pack_float24(float f)
219 {
220 union {
221 float fl;
222 uint32_t u;
223 } u;
224 float mantissa;
225 int exponent;
226 uint32_t float24 = 0;
227
228 if (f == 0.0)
229 return 0;
230
231 u.fl = f;
232
233 mantissa = frexpf(f, &exponent);
234
235 /* Handle -ve */
236 if (mantissa < 0) {
237 float24 |= (1 << 23);
238 mantissa = mantissa * -1.0;
239 }
240 /* Handle exponent, bias of 63 */
241 exponent += 62;
242 float24 |= (exponent << 16);
243 /* Kill 7 LSB of mantissa */
244 float24 |= (u.u & 0x7FFFFF) >> 7;
245
246 return float24;
247 }
248
249 void r300_emit_fragment_program_code(struct r300_context* r300,
250 struct rX00_fragment_program_code* generic_code)
251 {
252 struct r300_fragment_program_code * code = &generic_code->code.r300;
253 int i;
254 CS_LOCALS(r300);
255
256 BEGIN_CS(15 +
257 code->alu.length * 4 +
258 (code->tex.length ? (1 + code->tex.length) : 0));
259
260 OUT_CS_REG(R300_US_CONFIG, code->config);
261 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
262 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
263
264 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
265 for(i = 0; i < 4; ++i)
266 OUT_CS(code->code_addr[i]);
267
268 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
269 for (i = 0; i < code->alu.length; i++)
270 OUT_CS(code->alu.inst[i].rgb_inst);
271
272 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
273 for (i = 0; i < code->alu.length; i++)
274 OUT_CS(code->alu.inst[i].rgb_addr);
275
276 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
277 for (i = 0; i < code->alu.length; i++)
278 OUT_CS(code->alu.inst[i].alpha_inst);
279
280 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
281 for (i = 0; i < code->alu.length; i++)
282 OUT_CS(code->alu.inst[i].alpha_addr);
283
284 if (code->tex.length) {
285 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
286 for(i = 0; i < code->tex.length; ++i)
287 OUT_CS(code->tex.inst[i]);
288 }
289
290 END_CS;
291 }
292
293 void r300_emit_fs_constant_buffer(struct r300_context* r300,
294 struct rc_constant_list* constants)
295 {
296 int i;
297 CS_LOCALS(r300);
298
299 if (constants->Count == 0)
300 return;
301
302 BEGIN_CS(constants->Count * 4 + 1);
303 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
304 for(i = 0; i < constants->Count; ++i) {
305 const float * data = get_shader_constant(r300,
306 &constants->Constants[i],
307 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
308 OUT_CS(pack_float24(data[0]));
309 OUT_CS(pack_float24(data[1]));
310 OUT_CS(pack_float24(data[2]));
311 OUT_CS(pack_float24(data[3]));
312 }
313 END_CS;
314 }
315
316 static void r300_emit_fragment_depth_config(struct r300_context* r300,
317 struct r300_fragment_shader* fs)
318 {
319 CS_LOCALS(r300);
320
321 BEGIN_CS(4);
322 if (r300_fragment_shader_writes_depth(fs)) {
323 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
324 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
325 } else {
326 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
327 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
328 }
329 END_CS;
330 }
331
332 void r500_emit_fragment_program_code(struct r300_context* r300,
333 struct rX00_fragment_program_code* generic_code)
334 {
335 struct r500_fragment_program_code * code = &generic_code->code.r500;
336 int i;
337 CS_LOCALS(r300);
338
339 BEGIN_CS(13 +
340 ((code->inst_end + 1) * 6));
341 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
342 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
343 OUT_CS_REG(R500_US_CODE_RANGE,
344 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
345 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
346 OUT_CS_REG(R500_US_CODE_ADDR,
347 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
348
349 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
350 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
351 for (i = 0; i <= code->inst_end; i++) {
352 OUT_CS(code->inst[i].inst0);
353 OUT_CS(code->inst[i].inst1);
354 OUT_CS(code->inst[i].inst2);
355 OUT_CS(code->inst[i].inst3);
356 OUT_CS(code->inst[i].inst4);
357 OUT_CS(code->inst[i].inst5);
358 }
359
360 END_CS;
361 }
362
363 void r500_emit_fs_constant_buffer(struct r300_context* r300,
364 struct rc_constant_list* constants)
365 {
366 int i;
367 CS_LOCALS(r300);
368
369 if (constants->Count == 0)
370 return;
371
372 BEGIN_CS(constants->Count * 4 + 3);
373 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
374 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
375 for (i = 0; i < constants->Count; i++) {
376 const float * data = get_shader_constant(r300,
377 &constants->Constants[i],
378 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
379 OUT_CS_32F(data[0]);
380 OUT_CS_32F(data[1]);
381 OUT_CS_32F(data[2]);
382 OUT_CS_32F(data[3]);
383 }
384 END_CS;
385 }
386
387 void r300_emit_fb_state(struct r300_context* r300,
388 struct pipe_framebuffer_state* fb)
389 {
390 struct r300_texture* tex;
391 struct pipe_surface* surf;
392 int i;
393 CS_LOCALS(r300);
394
395 /* Shouldn't fail unless there is a bug in the state tracker. */
396 assert(fb->nr_cbufs <= 4);
397
398 BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
399 (fb->zsbuf ? 10 : 0) + 6);
400
401 /* Flush and free renderbuffer caches. */
402 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
403 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
404 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
405 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
406 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
407 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
408
409 /* Set the number of colorbuffers. */
410 OUT_CS_REG(R300_RB3D_CCTL, R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
411
412 /* Set up colorbuffers. */
413 for (i = 0; i < fb->nr_cbufs; i++) {
414 surf = fb->cbufs[i];
415 tex = (struct r300_texture*)surf->texture;
416 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
417
418 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
419 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
420
421 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
422 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
423 r300_translate_colorformat(tex->tex.format), 0,
424 RADEON_GEM_DOMAIN_VRAM, 0);
425
426 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
427 r300_translate_out_fmt(surf->format));
428 }
429
430 /* Disable unused colorbuffers. */
431 for (; i < 4; i++) {
432 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
433 }
434
435 /* Set up a zbuffer. */
436 if (fb->zsbuf) {
437 surf = fb->zsbuf;
438 tex = (struct r300_texture*)surf->texture;
439 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
440
441 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
442 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
443
444 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
445
446 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
447 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level], 0,
448 RADEON_GEM_DOMAIN_VRAM, 0);
449 }
450
451 END_CS;
452 }
453
454 static void r300_emit_query_start(struct r300_context *r300)
455 {
456 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
457 struct r300_query *query = r300->query_current;
458 CS_LOCALS(r300);
459
460 if (!query)
461 return;
462
463 BEGIN_CS(4);
464 if (caps->family == CHIP_FAMILY_RV530) {
465 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
466 } else {
467 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
468 }
469 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
470 END_CS;
471 query->begin_emitted = TRUE;
472 }
473
474
475 static void r300_emit_query_finish(struct r300_context *r300,
476 struct r300_query *query)
477 {
478 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
479 CS_LOCALS(r300);
480
481 assert(caps->num_frag_pipes);
482
483 BEGIN_CS(6 * caps->num_frag_pipes + 2);
484 /* I'm not so sure I like this switch, but it's hard to be elegant
485 * when there's so many special cases...
486 *
487 * So here's the basic idea. For each pipe, enable writes to it only,
488 * then put out the relocation for ZPASS_ADDR, taking into account a
489 * 4-byte offset for each pipe. RV380 and older are special; they have
490 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
491 * so there's a chipset cap for that. */
492 switch (caps->num_frag_pipes) {
493 case 4:
494 /* pipe 3 only */
495 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
496 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
497 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
498 0, RADEON_GEM_DOMAIN_GTT, 0);
499 case 3:
500 /* pipe 2 only */
501 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
502 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
503 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
504 0, RADEON_GEM_DOMAIN_GTT, 0);
505 case 2:
506 /* pipe 1 only */
507 /* As mentioned above, accomodate RV380 and older. */
508 OUT_CS_REG(R300_SU_REG_DEST,
509 1 << (caps->high_second_pipe ? 3 : 1));
510 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
511 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
512 0, RADEON_GEM_DOMAIN_GTT, 0);
513 case 1:
514 /* pipe 0 only */
515 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
516 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
517 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
518 0, RADEON_GEM_DOMAIN_GTT, 0);
519 break;
520 default:
521 debug_printf("r300: Implementation error: Chipset reports %d"
522 " pixel pipes!\n", caps->num_frag_pipes);
523 assert(0);
524 }
525
526 /* And, finally, reset it to normal... */
527 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
528 END_CS;
529 }
530
531 static void rv530_emit_query_single(struct r300_context *r300,
532 struct r300_query *query)
533 {
534 CS_LOCALS(r300);
535
536 BEGIN_CS(8);
537 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
538 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
539 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
540 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
541 END_CS;
542 }
543
544 static void rv530_emit_query_double(struct r300_context *r300,
545 struct r300_query *query)
546 {
547 CS_LOCALS(r300);
548
549 BEGIN_CS(14);
550 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
551 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
552 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
553 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
554 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
555 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
556 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
557 END_CS;
558 }
559
560 void r300_emit_query_end(struct r300_context* r300)
561 {
562 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
563 struct r300_query *query = r300->query_current;
564
565 if (!query)
566 return;
567
568 if (query->begin_emitted == FALSE)
569 return;
570
571 if (caps->family == CHIP_FAMILY_RV530) {
572 if (caps->num_z_pipes == 2)
573 rv530_emit_query_double(r300, query);
574 else
575 rv530_emit_query_single(r300, query);
576 } else
577 r300_emit_query_finish(r300, query);
578 }
579
580 void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs)
581 {
582 CS_LOCALS(r300);
583
584 BEGIN_CS(22);
585 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
586 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
587 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
588 OUT_CS(rs->point_minmax);
589 OUT_CS(rs->line_control);
590 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
591 OUT_CS(rs->depth_scale_front);
592 OUT_CS(rs->depth_offset_front);
593 OUT_CS(rs->depth_scale_back);
594 OUT_CS(rs->depth_offset_back);
595 OUT_CS(rs->polygon_offset_enable);
596 OUT_CS(rs->cull_mode);
597 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
598 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
599 OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
600 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
601 END_CS;
602 }
603
604 void r300_emit_rs_block_state(struct r300_context* r300,
605 struct r300_rs_block* rs)
606 {
607 int i;
608 struct r300_screen* r300screen = r300_screen(r300->context.screen);
609 CS_LOCALS(r300);
610
611 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
612
613 BEGIN_CS(21);
614 if (r300screen->caps->is_r500) {
615 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
616 } else {
617 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
618 }
619 for (i = 0; i < 8; i++) {
620 OUT_CS(rs->ip[i]);
621 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
622 }
623
624 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
625 OUT_CS(rs->count);
626 OUT_CS(rs->inst_count);
627
628 if (r300screen->caps->is_r500) {
629 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
630 } else {
631 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
632 }
633 for (i = 0; i < 8; i++) {
634 OUT_CS(rs->inst[i]);
635 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
636 }
637
638 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
639 rs->count, rs->inst_count);
640
641 END_CS;
642 }
643
644 static void r300_emit_scissor_regs(struct r300_context* r300,
645 struct r300_scissor_regs* scissor)
646 {
647 CS_LOCALS(r300);
648
649 BEGIN_CS(3);
650 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
651 OUT_CS(scissor->top_left);
652 OUT_CS(scissor->bottom_right);
653 END_CS;
654 }
655
656 void r300_emit_scissor_state(struct r300_context* r300,
657 struct r300_scissor_state* scissor)
658 {
659 if (r300->rs_state->rs.scissor) {
660 r300_emit_scissor_regs(r300, &scissor->scissor);
661 } else {
662 r300_emit_scissor_regs(r300, &scissor->framebuffer);
663 }
664 }
665
666 void r300_emit_texture(struct r300_context* r300,
667 struct r300_sampler_state* sampler,
668 struct r300_texture* tex,
669 unsigned offset)
670 {
671 uint32_t filter0 = sampler->filter0;
672 uint32_t format0 = tex->state.format0;
673 unsigned min_level, max_level;
674 CS_LOCALS(r300);
675
676 /* to emulate 1D textures through 2D ones correctly */
677 if (tex->tex.target == PIPE_TEXTURE_1D) {
678 filter0 &= ~R300_TX_WRAP_T_MASK;
679 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
680 }
681
682 /* determine min/max levels */
683 /* the MAX_MIP level is the largest (finest) one */
684 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
685 min_level = MIN2(sampler->min_lod, max_level);
686 format0 |= R300_TX_NUM_LEVELS(max_level);
687 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
688
689 BEGIN_CS(16);
690 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
691 (offset << 28));
692 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
693 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
694
695 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
696 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
697 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
698 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
699 OUT_CS_RELOC(tex->buffer, 0,
700 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
701 END_CS;
702 }
703
704 static boolean r300_validate_aos(struct r300_context *r300)
705 {
706 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
707 struct pipe_vertex_element *velem = r300->vertex_element;
708 int i;
709
710 /* Check if formats and strides are aligned to the size of DWORD. */
711 for (i = 0; i < r300->vertex_element_count; i++) {
712 if (vbuf[velem[i].vertex_buffer_index].stride % 4 != 0 ||
713 util_format_get_blocksize(velem[i].src_format) % 4 != 0) {
714 return FALSE;
715 }
716 }
717 return TRUE;
718 }
719
720 void r300_emit_aos(struct r300_context* r300, unsigned offset)
721 {
722 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
723 struct pipe_vertex_element *velem = r300->vertex_element;
724 int i;
725 unsigned size1, size2, aos_count = r300->vertex_element_count;
726 unsigned packet_size = (aos_count * 3 + 1) / 2;
727 CS_LOCALS(r300);
728
729 /* XXX Move this checking to a more approriate place. */
730 if (!r300_validate_aos(r300)) {
731 /* XXX We should fallback using Draw. */
732 assert(0);
733 }
734
735 BEGIN_CS(2 + packet_size + aos_count * 2);
736 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
737 OUT_CS(aos_count);
738
739 for (i = 0; i < aos_count - 1; i += 2) {
740 vb1 = &vbuf[velem[i].vertex_buffer_index];
741 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
742 size1 = util_format_get_blocksize(velem[i].src_format);
743 size2 = util_format_get_blocksize(velem[i+1].src_format);
744
745 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
746 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
747 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
748 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
749 }
750
751 if (aos_count & 1) {
752 vb1 = &vbuf[velem[i].vertex_buffer_index];
753 size1 = util_format_get_blocksize(velem[i].src_format);
754
755 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
756 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
757 }
758
759 for (i = 0; i < aos_count; i++) {
760 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
761 RADEON_GEM_DOMAIN_GTT, 0, 0);
762 }
763 END_CS;
764 }
765
766 #if 0
767 void r300_emit_draw_packet(struct r300_context* r300)
768 {
769 CS_LOCALS(r300);
770
771 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
772 "vertex size %d\n", r300->vbo,
773 r300->vertex_info->vinfo.size);
774 /* Set the pointer to our vertex buffer. The emitted values are this:
775 * PACKET3 [3D_LOAD_VBPNTR]
776 * COUNT [1]
777 * FORMAT [size | stride << 8]
778 * OFFSET [offset into BO]
779 * VBPNTR [relocated BO]
780 */
781 BEGIN_CS(7);
782 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
783 OUT_CS(1);
784 OUT_CS(r300->vertex_info->vinfo.size |
785 (r300->vertex_info->vinfo.size << 8));
786 OUT_CS(r300->vbo_offset);
787 OUT_CS_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
788 END_CS;
789 }
790 #endif
791
792 void r300_emit_vertex_format_state(struct r300_context* r300)
793 {
794 int i;
795 CS_LOCALS(r300);
796
797 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
798
799 BEGIN_CS(26);
800 OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info->vinfo.size);
801
802 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
803 OUT_CS(r300->vertex_info->vinfo.hwfmt[0]);
804 OUT_CS(r300->vertex_info->vinfo.hwfmt[1]);
805 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
806 OUT_CS(r300->vertex_info->vinfo.hwfmt[2]);
807 OUT_CS(r300->vertex_info->vinfo.hwfmt[3]);
808 for (i = 0; i < 4; i++) {
809 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
810 r300->vertex_info->vinfo.hwfmt[i]);
811 }
812
813 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
814 for (i = 0; i < 8; i++) {
815 OUT_CS(r300->vertex_info->vap_prog_stream_cntl[i]);
816 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
817 r300->vertex_info->vap_prog_stream_cntl[i]);
818 }
819 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
820 for (i = 0; i < 8; i++) {
821 OUT_CS(r300->vertex_info->vap_prog_stream_cntl_ext[i]);
822 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
823 r300->vertex_info->vap_prog_stream_cntl_ext[i]);
824 }
825 END_CS;
826 }
827
828
829 void r300_emit_vertex_program_code(struct r300_context* r300,
830 struct r300_vertex_program_code* code)
831 {
832 int i;
833 struct r300_screen* r300screen = r300_screen(r300->context.screen);
834 unsigned instruction_count = code->length / 4;
835
836 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
837 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
838 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
839 int temp_count = MAX2(code->num_temporaries, 1);
840 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
841 vtx_mem_size / output_count, 10);
842 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
843
844 CS_LOCALS(r300);
845
846 if (!r300screen->caps->has_tcl) {
847 debug_printf("r300: Implementation error: emit_vertex_shader called,"
848 " but has_tcl is FALSE!\n");
849 return;
850 }
851
852 BEGIN_CS(9 + code->length);
853 /* R300_VAP_PVS_CODE_CNTL_0
854 * R300_VAP_PVS_CONST_CNTL
855 * R300_VAP_PVS_CODE_CNTL_1
856 * See the r5xx docs for instructions on how to use these. */
857 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
858 OUT_CS(R300_PVS_FIRST_INST(0) |
859 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
860 R300_PVS_LAST_INST(instruction_count - 1));
861 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
862 OUT_CS(instruction_count - 1);
863
864 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
865 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
866 for (i = 0; i < code->length; i++)
867 OUT_CS(code->body.d[i]);
868
869 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
870 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
871 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
872 R300_PVS_VF_MAX_VTX_NUM(12) |
873 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
874 END_CS;
875 }
876
877 void r300_emit_vertex_shader(struct r300_context* r300,
878 struct r300_vertex_shader* vs)
879 {
880 r300_emit_vertex_program_code(r300, &vs->code);
881 }
882
883 void r300_emit_vs_constant_buffer(struct r300_context* r300,
884 struct rc_constant_list* constants)
885 {
886 int i;
887 struct r300_screen* r300screen = r300_screen(r300->context.screen);
888 CS_LOCALS(r300);
889
890 if (!r300screen->caps->has_tcl) {
891 debug_printf("r300: Implementation error: emit_vertex_shader called,"
892 " but has_tcl is FALSE!\n");
893 return;
894 }
895
896 if (constants->Count == 0)
897 return;
898
899 BEGIN_CS(constants->Count * 4 + 3);
900 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
901 (r300screen->caps->is_r500 ?
902 R500_PVS_CONST_START : R300_PVS_CONST_START));
903 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
904 for (i = 0; i < constants->Count; i++) {
905 const float * data = get_shader_constant(r300,
906 &constants->Constants[i],
907 &r300->shader_constants[PIPE_SHADER_VERTEX]);
908 OUT_CS_32F(data[0]);
909 OUT_CS_32F(data[1]);
910 OUT_CS_32F(data[2]);
911 OUT_CS_32F(data[3]);
912 }
913 END_CS;
914 }
915
916 void r300_emit_viewport_state(struct r300_context* r300,
917 struct r300_viewport_state* viewport)
918 {
919 CS_LOCALS(r300);
920
921 BEGIN_CS(9);
922 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
923 OUT_CS_32F(viewport->xscale);
924 OUT_CS_32F(viewport->xoffset);
925 OUT_CS_32F(viewport->yscale);
926 OUT_CS_32F(viewport->yoffset);
927 OUT_CS_32F(viewport->zscale);
928 OUT_CS_32F(viewport->zoffset);
929
930 if (r300->rs_state->enable_vte) {
931 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
932 } else {
933 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
934 }
935 END_CS;
936 }
937
938 void r300_emit_texture_count(struct r300_context* r300)
939 {
940 uint32_t tx_enable = 0;
941 int i;
942 CS_LOCALS(r300);
943
944 /* Notice that texture_count and sampler_count are just sizes
945 * of the respective arrays. We still have to check for the individual
946 * elements. */
947 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
948 if (r300->textures[i]) {
949 tx_enable |= 1 << i;
950 }
951 }
952
953 BEGIN_CS(2);
954 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
955 END_CS;
956
957 }
958
959 void r300_flush_textures(struct r300_context* r300)
960 {
961 CS_LOCALS(r300);
962
963 BEGIN_CS(2);
964 OUT_CS_REG(R300_TX_INVALTAGS, 0);
965 END_CS;
966 }
967
968 static void r300_flush_pvs(struct r300_context* r300)
969 {
970 CS_LOCALS(r300);
971
972 BEGIN_CS(2);
973 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
974 END_CS;
975 }
976
977 /* Emit all dirty state. */
978 void r300_emit_dirty_state(struct r300_context* r300)
979 {
980 struct r300_screen* r300screen = r300_screen(r300->context.screen);
981 struct r300_texture* tex;
982 struct r300_atom* atom;
983 int i, dirty_tex = 0;
984 boolean invalid = FALSE;
985
986 if (!(r300->dirty_state)) {
987 return;
988 }
989
990 /* Check size of CS. */
991 /* Make sure we have at least 8*1024 spare dwords. */
992 /* XXX It would be nice to know the number of dwords we really need to
993 * XXX emit. */
994 if (!r300->winsys->check_cs(r300->winsys, 8*1024)) {
995 r300->context.flush(&r300->context, 0, NULL);
996 }
997
998 /* Clean out BOs. */
999 r300->winsys->reset_bos(r300->winsys);
1000
1001 validate:
1002 /* Color buffers... */
1003 for (i = 0; i < r300->framebuffer_state.nr_cbufs; i++) {
1004 tex = (struct r300_texture*)r300->framebuffer_state.cbufs[i]->texture;
1005 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1006 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1007 0, RADEON_GEM_DOMAIN_VRAM)) {
1008 r300->context.flush(&r300->context, 0, NULL);
1009 goto validate;
1010 }
1011 }
1012 /* ...depth buffer... */
1013 if (r300->framebuffer_state.zsbuf) {
1014 tex = (struct r300_texture*)r300->framebuffer_state.zsbuf->texture;
1015 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1016 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1017 0, RADEON_GEM_DOMAIN_VRAM)) {
1018 r300->context.flush(&r300->context, 0, NULL);
1019 goto validate;
1020 }
1021 }
1022 /* ...textures... */
1023 for (i = 0; i < r300->texture_count; i++) {
1024 tex = r300->textures[i];
1025 if (!tex)
1026 continue;
1027 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1028 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1029 r300->context.flush(&r300->context, 0, NULL);
1030 goto validate;
1031 }
1032 }
1033 /* ...occlusion query buffer... */
1034 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1035 0, RADEON_GEM_DOMAIN_GTT)) {
1036 r300->context.flush(&r300->context, 0, NULL);
1037 goto validate;
1038 }
1039 /* ...and vertex buffer. */
1040 if (r300->vbo) {
1041 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1042 RADEON_GEM_DOMAIN_GTT, 0)) {
1043 r300->context.flush(&r300->context, 0, NULL);
1044 goto validate;
1045 }
1046 } else {
1047 /* debug_printf("No VBO while emitting dirty state!\n"); */
1048 }
1049 if (!r300->winsys->validate(r300->winsys)) {
1050 r300->context.flush(&r300->context, 0, NULL);
1051 if (invalid) {
1052 /* Well, hell. */
1053 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1054 exit(1);
1055 }
1056 invalid = TRUE;
1057 goto validate;
1058 }
1059
1060 if (r300->dirty_state & R300_NEW_QUERY) {
1061 r300_emit_query_start(r300);
1062 r300->dirty_state &= ~R300_NEW_QUERY;
1063 }
1064
1065 foreach(atom, &r300->atom_list) {
1066 if (atom->dirty) {
1067 atom->emit(r300, atom->state);
1068 atom->dirty = FALSE;
1069 }
1070 }
1071
1072 if (r300->dirty_state & R300_NEW_BLEND_COLOR) {
1073 r300_emit_blend_color_state(r300, r300->blend_color_state);
1074 r300->dirty_state &= ~R300_NEW_BLEND_COLOR;
1075 }
1076
1077 if (r300->dirty_state & R300_NEW_CLIP) {
1078 r300_emit_clip_state(r300, &r300->clip_state);
1079 r300->dirty_state &= ~R300_NEW_CLIP;
1080 }
1081
1082 if (r300->dirty_state & R300_NEW_DSA) {
1083 r300_emit_dsa_state(r300, r300->dsa_state);
1084 r300->dirty_state &= ~R300_NEW_DSA;
1085 }
1086
1087 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1088 r300_emit_fragment_depth_config(r300, r300->fs);
1089 if (r300screen->caps->is_r500) {
1090 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1091 } else {
1092 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1093 }
1094 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1095 }
1096
1097 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1098 if (r300screen->caps->is_r500) {
1099 r500_emit_fs_constant_buffer(r300,
1100 &r300->fs->shader->code.constants);
1101 } else {
1102 r300_emit_fs_constant_buffer(r300,
1103 &r300->fs->shader->code.constants);
1104 }
1105 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1106 }
1107
1108 if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
1109 r300_emit_fb_state(r300, &r300->framebuffer_state);
1110 r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
1111 }
1112
1113 if (r300->dirty_state & R300_NEW_RASTERIZER) {
1114 r300_emit_rs_state(r300, r300->rs_state);
1115 r300->dirty_state &= ~R300_NEW_RASTERIZER;
1116 }
1117
1118 if (r300->dirty_state & R300_NEW_RS_BLOCK) {
1119 r300_emit_rs_block_state(r300, r300->rs_block);
1120 r300->dirty_state &= ~R300_NEW_RS_BLOCK;
1121 }
1122
1123 if (r300->dirty_state & R300_NEW_SCISSOR) {
1124 r300_emit_scissor_state(r300, r300->scissor_state);
1125 r300->dirty_state &= ~R300_NEW_SCISSOR;
1126 }
1127
1128 /* Samplers and textures are tracked separately but emitted together. */
1129 if (r300->dirty_state &
1130 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1131 r300_emit_texture_count(r300);
1132
1133 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1134 if (r300->dirty_state &
1135 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1136 if (r300->textures[i])
1137 r300_emit_texture(r300,
1138 r300->sampler_states[i],
1139 r300->textures[i],
1140 i);
1141 r300->dirty_state &=
1142 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1143 dirty_tex++;
1144 }
1145 }
1146 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1147 }
1148
1149 if (r300->dirty_state & R300_NEW_VIEWPORT) {
1150 r300_emit_viewport_state(r300, r300->viewport_state);
1151 r300->dirty_state &= ~R300_NEW_VIEWPORT;
1152 }
1153
1154 if (dirty_tex) {
1155 r300_flush_textures(r300);
1156 }
1157
1158 if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
1159 r300_emit_vertex_format_state(r300);
1160 r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
1161 }
1162
1163 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1164 r300_flush_pvs(r300);
1165 }
1166
1167 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1168 r300_emit_vertex_shader(r300, r300->vs);
1169 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1170 }
1171
1172 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1173 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1174 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1175 }
1176
1177 /* XXX
1178 assert(r300->dirty_state == 0);
1179 */
1180
1181 /* Finally, emit the VBO. */
1182 /* r300_emit_vertex_buffer(r300); */
1183
1184 r300->dirty_hw++;
1185 }