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[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 /* r300_emit: Functions for emitting state. */
24
25 #include "util/u_math.h"
26
27 #include "r300_context.h"
28 #include "r300_cs.h"
29 #include "r300_emit.h"
30 #include "r300_fs.h"
31 #include "r300_screen.h"
32 #include "r300_state_derived.h"
33 #include "r300_state_inlines.h"
34 #include "r300_texture.h"
35 #include "r300_vs.h"
36
37 void r300_emit_blend_state(struct r300_context* r300,
38 struct r300_blend_state* blend)
39 {
40 CS_LOCALS(r300);
41 BEGIN_CS(8);
42 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
43 OUT_CS(blend->blend_control);
44 OUT_CS(blend->alpha_blend_control);
45 OUT_CS(blend->color_channel_mask);
46 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
47 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
48 END_CS;
49 }
50
51 void r300_emit_blend_color_state(struct r300_context* r300,
52 struct r300_blend_color_state* bc)
53 {
54 struct r300_screen* r300screen = r300_screen(r300->context.screen);
55 CS_LOCALS(r300);
56
57 if (r300screen->caps->is_r500) {
58 BEGIN_CS(3);
59 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
60 OUT_CS(bc->blend_color_red_alpha);
61 OUT_CS(bc->blend_color_green_blue);
62 END_CS;
63 } else {
64 BEGIN_CS(2);
65 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
66 END_CS;
67 }
68 }
69
70 void r300_emit_clip_state(struct r300_context* r300,
71 struct pipe_clip_state* clip)
72 {
73 int i;
74 struct r300_screen* r300screen = r300_screen(r300->context.screen);
75 CS_LOCALS(r300);
76
77 if (r300screen->caps->has_tcl) {
78 BEGIN_CS(5 + (6 * 4));
79 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
80 (r300screen->caps->is_r500 ?
81 R500_PVS_UCP_START : R300_PVS_UCP_START));
82 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
83 for (i = 0; i < 6; i++) {
84 OUT_CS_32F(clip->ucp[i][0]);
85 OUT_CS_32F(clip->ucp[i][1]);
86 OUT_CS_32F(clip->ucp[i][2]);
87 OUT_CS_32F(clip->ucp[i][3]);
88 }
89 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
90 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
91 END_CS;
92 } else {
93 BEGIN_CS(2);
94 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
95 END_CS;
96 }
97
98 }
99
100 void r300_emit_dsa_state(struct r300_context* r300,
101 struct r300_dsa_state* dsa)
102 {
103 struct r300_screen* r300screen = r300_screen(r300->context.screen);
104 CS_LOCALS(r300);
105
106 BEGIN_CS(r300screen->caps->is_r500 ? 10 : 8);
107 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
108
109 /* not needed since we use the 8bit alpha ref */
110 /*if (r300screen->caps->is_r500) {
111 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
112 }*/
113
114 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
115 OUT_CS(dsa->z_buffer_control);
116 OUT_CS(dsa->z_stencil_control);
117 OUT_CS(dsa->stencil_ref_mask);
118 OUT_CS_REG(R300_ZB_ZTOP, r300->ztop_state.z_buffer_top);
119
120 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
121 if (r300screen->caps->is_r500) {
122 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
123 }
124 END_CS;
125 }
126
127 static const float * get_shader_constant(
128 struct r300_context * r300,
129 struct rc_constant * constant,
130 struct r300_constant_buffer * externals)
131 {
132 static const float zero[4] = { 0.0, 0.0, 0.0, 0.0 };
133 switch(constant->Type) {
134 case RC_CONSTANT_EXTERNAL:
135 return externals->constants[constant->u.External];
136
137 case RC_CONSTANT_IMMEDIATE:
138 return constant->u.Immediate;
139
140 default:
141 debug_printf("r300: Implementation error: Unhandled constant type %i\n",
142 constant->Type);
143 return zero;
144 }
145 }
146
147 /* Convert a normal single-precision float into the 7.16 format
148 * used by the R300 fragment shader.
149 */
150 static uint32_t pack_float24(float f)
151 {
152 union {
153 float fl;
154 uint32_t u;
155 } u;
156 float mantissa;
157 int exponent;
158 uint32_t float24 = 0;
159
160 if (f == 0.0)
161 return 0;
162
163 u.fl = f;
164
165 mantissa = frexpf(f, &exponent);
166
167 /* Handle -ve */
168 if (mantissa < 0) {
169 float24 |= (1 << 23);
170 mantissa = mantissa * -1.0;
171 }
172 /* Handle exponent, bias of 63 */
173 exponent += 62;
174 float24 |= (exponent << 16);
175 /* Kill 7 LSB of mantissa */
176 float24 |= (u.u & 0x7FFFFF) >> 7;
177
178 return float24;
179 }
180
181 void r300_emit_fragment_program_code(struct r300_context* r300,
182 struct rX00_fragment_program_code* generic_code)
183 {
184 struct r300_fragment_program_code * code = &generic_code->code.r300;
185 int i;
186 CS_LOCALS(r300);
187
188 BEGIN_CS(15 +
189 code->alu.length * 4 +
190 (code->tex.length ? (1 + code->tex.length) : 0));
191
192 OUT_CS_REG(R300_US_CONFIG, code->config);
193 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
194 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
195
196 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
197 for(i = 0; i < 4; ++i)
198 OUT_CS(code->code_addr[i]);
199
200 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
201 for (i = 0; i < code->alu.length; i++)
202 OUT_CS(code->alu.inst[i].rgb_inst);
203
204 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
205 for (i = 0; i < code->alu.length; i++)
206 OUT_CS(code->alu.inst[i].rgb_addr);
207
208 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
209 for (i = 0; i < code->alu.length; i++)
210 OUT_CS(code->alu.inst[i].alpha_inst);
211
212 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
213 for (i = 0; i < code->alu.length; i++)
214 OUT_CS(code->alu.inst[i].alpha_addr);
215
216 if (code->tex.length) {
217 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
218 for(i = 0; i < code->tex.length; ++i)
219 OUT_CS(code->tex.inst[i]);
220 }
221
222 END_CS;
223 }
224
225 void r300_emit_fs_constant_buffer(struct r300_context* r300,
226 struct rc_constant_list* constants)
227 {
228 int i;
229 CS_LOCALS(r300);
230
231 if (constants->Count == 0)
232 return;
233
234 BEGIN_CS(constants->Count * 4 + 1);
235 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
236 for(i = 0; i < constants->Count; ++i) {
237 const float * data = get_shader_constant(r300,
238 &constants->Constants[i],
239 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
240 OUT_CS(pack_float24(data[0]));
241 OUT_CS(pack_float24(data[1]));
242 OUT_CS(pack_float24(data[2]));
243 OUT_CS(pack_float24(data[3]));
244 }
245 END_CS;
246 }
247
248 void r500_emit_fragment_program_code(struct r300_context* r300,
249 struct rX00_fragment_program_code* generic_code)
250 {
251 struct r500_fragment_program_code * code = &generic_code->code.r500;
252 int i;
253 CS_LOCALS(r300);
254
255 BEGIN_CS(13 +
256 ((code->inst_end + 1) * 6));
257 OUT_CS_REG(R500_US_CONFIG, 0);
258 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
259 OUT_CS_REG(R500_US_CODE_RANGE,
260 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
261 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
262 OUT_CS_REG(R500_US_CODE_ADDR,
263 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
264
265 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
266 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
267 for (i = 0; i <= code->inst_end; i++) {
268 OUT_CS(code->inst[i].inst0);
269 OUT_CS(code->inst[i].inst1);
270 OUT_CS(code->inst[i].inst2);
271 OUT_CS(code->inst[i].inst3);
272 OUT_CS(code->inst[i].inst4);
273 OUT_CS(code->inst[i].inst5);
274 }
275
276 END_CS;
277 }
278
279 void r500_emit_fs_constant_buffer(struct r300_context* r300,
280 struct rc_constant_list* constants)
281 {
282 int i;
283 CS_LOCALS(r300);
284
285 if (constants->Count == 0)
286 return;
287
288 BEGIN_CS(constants->Count * 4 + 3);
289 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
290 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
291 for (i = 0; i < constants->Count; i++) {
292 const float * data = get_shader_constant(r300,
293 &constants->Constants[i],
294 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
295 OUT_CS_32F(data[0]);
296 OUT_CS_32F(data[1]);
297 OUT_CS_32F(data[2]);
298 OUT_CS_32F(data[3]);
299 }
300 END_CS;
301 }
302
303 void r300_emit_fb_state(struct r300_context* r300,
304 struct pipe_framebuffer_state* fb)
305 {
306 struct r300_texture* tex;
307 struct pipe_surface* surf;
308 int i;
309 CS_LOCALS(r300);
310
311 BEGIN_CS((10 * fb->nr_cbufs) + (fb->zsbuf ? 10 : 0) + 4);
312 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
313 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
314 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
315 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
316 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
317 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
318
319 for (i = 0; i < fb->nr_cbufs; i++) {
320 surf = fb->cbufs[i];
321 tex = (struct r300_texture*)surf->texture;
322 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
323
324 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
325 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
326
327 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
328 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
329 r300_translate_colorformat(tex->tex.format), 0,
330 RADEON_GEM_DOMAIN_VRAM, 0);
331
332 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
333 r300_translate_out_fmt(surf->format));
334 }
335
336 if (fb->zsbuf) {
337 surf = fb->zsbuf;
338 tex = (struct r300_texture*)surf->texture;
339 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
340
341 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
342 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
343
344 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
345
346 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
347 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level], 0,
348 RADEON_GEM_DOMAIN_VRAM, 0);
349 }
350
351 END_CS;
352 }
353
354 static void r300_emit_query_start(struct r300_context *r300)
355 {
356 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
357 struct r300_query *query = r300->query_current;
358 CS_LOCALS(r300);
359
360 if (!query)
361 return;
362
363 /* XXX This will almost certainly not return good results
364 * for overlapping queries. */
365 BEGIN_CS(4);
366 if (caps->family == CHIP_FAMILY_RV530) {
367 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
368 } else {
369 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
370 }
371 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
372 END_CS;
373 query->begin_emitted = TRUE;
374 }
375
376
377 static void r300_emit_query_finish(struct r300_context *r300,
378 struct r300_query *query)
379 {
380 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
381 CS_LOCALS(r300);
382
383 assert(caps->num_frag_pipes);
384
385 BEGIN_CS(6 * caps->num_frag_pipes + 2);
386 /* I'm not so sure I like this switch, but it's hard to be elegant
387 * when there's so many special cases...
388 *
389 * So here's the basic idea. For each pipe, enable writes to it only,
390 * then put out the relocation for ZPASS_ADDR, taking into account a
391 * 4-byte offset for each pipe. RV380 and older are special; they have
392 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
393 * so there's a chipset cap for that. */
394 switch (caps->num_frag_pipes) {
395 case 4:
396 /* pipe 3 only */
397 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
398 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
399 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
400 0, RADEON_GEM_DOMAIN_GTT, 0);
401 case 3:
402 /* pipe 2 only */
403 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
404 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
405 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
406 0, RADEON_GEM_DOMAIN_GTT, 0);
407 case 2:
408 /* pipe 1 only */
409 /* As mentioned above, accomodate RV380 and older. */
410 OUT_CS_REG(R300_SU_REG_DEST,
411 1 << (caps->high_second_pipe ? 3 : 1));
412 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
413 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
414 0, RADEON_GEM_DOMAIN_GTT, 0);
415 case 1:
416 /* pipe 0 only */
417 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
418 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
419 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
420 0, RADEON_GEM_DOMAIN_GTT, 0);
421 break;
422 default:
423 debug_printf("r300: Implementation error: Chipset reports %d"
424 " pixel pipes!\n", caps->num_frag_pipes);
425 assert(0);
426 }
427
428 /* And, finally, reset it to normal... */
429 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
430 END_CS;
431 }
432
433 static void rv530_emit_query_single(struct r300_context *r300,
434 struct r300_query *query)
435 {
436 CS_LOCALS(r300);
437
438 BEGIN_CS(8);
439 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
440 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
441 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
442 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
443 END_CS;
444 }
445
446 static void rv530_emit_query_double(struct r300_context *r300,
447 struct r300_query *query)
448 {
449 CS_LOCALS(r300);
450
451 BEGIN_CS(14);
452 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
453 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
454 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
455 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
456 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
457 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
458 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
459 END_CS;
460 }
461
462 void r300_emit_query_end(struct r300_context* r300)
463 {
464 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
465 struct r300_query *query = r300->query_current;
466
467 if (!query)
468 return;
469
470 if (query->begin_emitted == FALSE)
471 return;
472
473 if (caps->family == CHIP_FAMILY_RV530) {
474 if (caps->num_z_pipes == 2)
475 rv530_emit_query_double(r300, query);
476 else
477 rv530_emit_query_single(r300, query);
478 } else
479 r300_emit_query_finish(r300, query);
480 }
481
482 void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs)
483 {
484 CS_LOCALS(r300);
485
486 BEGIN_CS(22);
487 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
488 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
489 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
490 OUT_CS(rs->point_minmax);
491 OUT_CS(rs->line_control);
492 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
493 OUT_CS(rs->depth_scale_front);
494 OUT_CS(rs->depth_offset_front);
495 OUT_CS(rs->depth_scale_back);
496 OUT_CS(rs->depth_offset_back);
497 OUT_CS(rs->polygon_offset_enable);
498 OUT_CS(rs->cull_mode);
499 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
500 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
501 OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
502 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
503 END_CS;
504 }
505
506 void r300_emit_rs_block_state(struct r300_context* r300,
507 struct r300_rs_block* rs)
508 {
509 int i;
510 struct r300_screen* r300screen = r300_screen(r300->context.screen);
511 CS_LOCALS(r300);
512
513 BEGIN_CS(21);
514 if (r300screen->caps->is_r500) {
515 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
516 } else {
517 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
518 }
519 for (i = 0; i < 8; i++) {
520 OUT_CS(rs->ip[i]);
521 /* debug_printf("ip %d: 0x%08x\n", i, rs->ip[i]); */
522 }
523
524 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
525 OUT_CS(rs->count);
526 OUT_CS(rs->inst_count);
527
528 if (r300screen->caps->is_r500) {
529 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
530 } else {
531 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
532 }
533 for (i = 0; i < 8; i++) {
534 OUT_CS(rs->inst[i]);
535 /* debug_printf("inst %d: 0x%08x\n", i, rs->inst[i]); */
536 }
537
538 /* debug_printf("count: 0x%08x inst_count: 0x%08x\n", rs->count,
539 * rs->inst_count); */
540
541 END_CS;
542 }
543
544 void r300_emit_scissor_state(struct r300_context* r300,
545 struct r300_scissor_state* scissor)
546 {
547 CS_LOCALS(r300);
548
549 BEGIN_CS(3);
550 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
551 OUT_CS(scissor->scissor_top_left);
552 OUT_CS(scissor->scissor_bottom_right);
553 END_CS;
554 }
555
556 void r300_emit_texture(struct r300_context* r300,
557 struct r300_sampler_state* sampler,
558 struct r300_texture* tex,
559 unsigned offset)
560 {
561 uint32_t filter0 = sampler->filter0;
562 CS_LOCALS(r300);
563
564 /* to emulate 1D textures through 2D ones correctly */
565 if (tex->tex.target == PIPE_TEXTURE_1D) {
566 filter0 &= ~R300_TX_WRAP_T_MASK;
567 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
568 }
569
570 BEGIN_CS(16);
571 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
572 (offset << 28));
573 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
574 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
575
576 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), tex->state.format0);
577 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
578 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
579 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
580 OUT_CS_RELOC(tex->buffer, 0,
581 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
582 END_CS;
583 }
584
585 void r300_emit_aos(struct r300_context* r300, unsigned offset)
586 {
587 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
588 struct pipe_vertex_element *velem = r300->vertex_element;
589 CS_LOCALS(r300);
590 int i;
591 unsigned packet_size = (r300->aos_count * 3 + 1) / 2;
592 BEGIN_CS(2 + packet_size + r300->aos_count * 2);
593 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
594 OUT_CS(r300->aos_count);
595 for (i = 0; i < r300->aos_count - 1; i += 2) {
596 int buf_num1 = velem[i].vertex_buffer_index;
597 int buf_num2 = velem[i+1].vertex_buffer_index;
598 assert(vbuf[buf_num1].stride % 4 == 0 && pf_get_size(velem[i].src_format) % 4 == 0);
599 assert(vbuf[buf_num2].stride % 4 == 0 && pf_get_size(velem[i+1].src_format) % 4 == 0);
600 OUT_CS((pf_get_size(velem[i].src_format) >> 2) | (vbuf[buf_num1].stride << 6) |
601 (pf_get_size(velem[i+1].src_format) << 14) | (vbuf[buf_num2].stride << 22));
602 OUT_CS(vbuf[buf_num1].buffer_offset + velem[i].src_offset +
603 offset * vbuf[buf_num1].stride);
604 OUT_CS(vbuf[buf_num2].buffer_offset + velem[i+1].src_offset +
605 offset * vbuf[buf_num2].stride);
606 }
607 if (r300->aos_count & 1) {
608 int buf_num = velem[i].vertex_buffer_index;
609 assert(vbuf[buf_num].stride % 4 == 0 && pf_get_size(velem[i].src_format) % 4 == 0);
610 OUT_CS((pf_get_size(velem[i].src_format) >> 2) | (vbuf[buf_num].stride << 6));
611 OUT_CS(vbuf[buf_num].buffer_offset + velem[i].src_offset +
612 offset * vbuf[buf_num].stride);
613 }
614
615 for (i = 0; i < r300->aos_count; i++) {
616 cs_winsys->write_cs_reloc(cs_winsys,
617 vbuf[velem[i].vertex_buffer_index].buffer,
618 RADEON_GEM_DOMAIN_GTT,
619 0,
620 0);
621 cs_count -= 2;
622 }
623 END_CS;
624 }
625 #if 0
626 void r300_emit_draw_packet(struct r300_context* r300)
627 {
628 CS_LOCALS(r300);
629
630 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
631 "vertex size %d\n", r300->vbo,
632 r300->vertex_info->vinfo.size);
633 /* Set the pointer to our vertex buffer. The emitted values are this:
634 * PACKET3 [3D_LOAD_VBPNTR]
635 * COUNT [1]
636 * FORMAT [size | stride << 8]
637 * OFFSET [offset into BO]
638 * VBPNTR [relocated BO]
639 */
640 BEGIN_CS(7);
641 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
642 OUT_CS(1);
643 OUT_CS(r300->vertex_info->vinfo.size |
644 (r300->vertex_info->vinfo.size << 8));
645 OUT_CS(r300->vbo_offset);
646 OUT_CS_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
647 END_CS;
648 }
649 #endif
650 void r300_emit_draw_arrays(struct r300_context *r300,
651 unsigned count)
652 {
653 CS_LOCALS(r300);
654 assert(count < 65536);
655
656 BEGIN_CS(4);
657 OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, count);
658 OUT_CS_PKT3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
659 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (count << 16) |
660 r300->hw_prim);
661 END_CS;
662 }
663
664 void r300_emit_draw_elements(struct r300_context *r300,
665 struct pipe_buffer* indexBuffer,
666 unsigned indexSize,
667 unsigned minIndex,
668 unsigned maxIndex,
669 unsigned start,
670 unsigned count)
671 {
672 CS_LOCALS(r300);
673 assert(indexSize == 4 || indexSize == 2);
674 assert(count < 65536);
675 assert((start * indexSize) % 4 == 0);
676
677 uint32_t size_dwords;
678 uint32_t skip_dwords = indexSize * start / sizeof(uint32_t);
679 assert(skip_dwords == 0);
680
681 BEGIN_CS(10);
682 OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, maxIndex);
683 OUT_CS_PKT3(R300_PACKET3_3D_DRAW_INDX_2, 0);
684 if (indexSize == 4) {
685 size_dwords = count + start;
686 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | (count << 16) |
687 R300_VAP_VF_CNTL__INDEX_SIZE_32bit | r300->hw_prim);
688 } else {
689 size_dwords = (count + start + 1) / 2;
690 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_INDICES |
691 (count << 16) | r300->hw_prim);
692 }
693
694 OUT_CS_PKT3(R300_PACKET3_INDX_BUFFER, 2);
695 OUT_CS(R300_INDX_BUFFER_ONE_REG_WR | (R300_VAP_PORT_IDX0 >> 2) |
696 (0 << R300_INDX_BUFFER_SKIP_SHIFT));
697 OUT_CS(skip_dwords);
698 OUT_CS(size_dwords);
699 cs_winsys->write_cs_reloc(cs_winsys,
700 indexBuffer,
701 RADEON_GEM_DOMAIN_GTT,
702 0,
703 0);
704 cs_count -= 2;
705
706 END_CS;
707 }
708
709 void r300_emit_vertex_format_state(struct r300_context* r300)
710 {
711 int i;
712 CS_LOCALS(r300);
713
714 BEGIN_CS(26);
715 OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info->vinfo.size);
716
717 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
718 OUT_CS(r300->vertex_info->vinfo.hwfmt[0]);
719 OUT_CS(r300->vertex_info->vinfo.hwfmt[1]);
720 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
721 OUT_CS(r300->vertex_info->vinfo.hwfmt[2]);
722 OUT_CS(r300->vertex_info->vinfo.hwfmt[3]);
723 /* for (i = 0; i < 4; i++) {
724 * debug_printf("hwfmt%d: 0x%08x\n", i,
725 * r300->vertex_info->vinfo.hwfmt[i]);
726 * } */
727
728 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
729 for (i = 0; i < 8; i++) {
730 OUT_CS(r300->vertex_info->vap_prog_stream_cntl[i]);
731 /* debug_printf("prog_stream_cntl%d: 0x%08x\n", i,
732 * r300->vertex_info->vap_prog_stream_cntl[i]); */
733 }
734 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
735 for (i = 0; i < 8; i++) {
736 OUT_CS(r300->vertex_info->vap_prog_stream_cntl_ext[i]);
737 /* debug_printf("prog_stream_cntl_ext%d: 0x%08x\n", i,
738 * r300->vertex_info->vap_prog_stream_cntl_ext[i]); */
739 }
740 END_CS;
741 }
742
743 void r300_emit_vertex_program_code(struct r300_context* r300,
744 struct r300_vertex_program_code* code)
745 {
746 int i;
747 struct r300_screen* r300screen = r300_screen(r300->context.screen);
748 unsigned instruction_count = code->length / 4;
749 CS_LOCALS(r300);
750
751 if (!r300screen->caps->has_tcl) {
752 debug_printf("r300: Implementation error: emit_vertex_shader called,"
753 " but has_tcl is FALSE!\n");
754 return;
755 }
756
757 BEGIN_CS(9 + code->length);
758 /* R300_VAP_PVS_CODE_CNTL_0
759 * R300_VAP_PVS_CONST_CNTL
760 * R300_VAP_PVS_CODE_CNTL_1
761 * See the r5xx docs for instructions on how to use these.
762 * XXX these could be optimized to select better values... */
763 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
764 OUT_CS(R300_PVS_FIRST_INST(0) |
765 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
766 R300_PVS_LAST_INST(instruction_count - 1));
767 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
768 OUT_CS(instruction_count - 1);
769
770 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
771 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
772 for (i = 0; i < code->length; i++)
773 OUT_CS(code->body.d[i]);
774
775 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(10) |
776 R300_PVS_NUM_CNTLRS(5) |
777 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
778 R300_PVS_VF_MAX_VTX_NUM(12));
779 END_CS;
780 }
781
782 void r300_emit_vertex_shader(struct r300_context* r300,
783 struct r300_vertex_shader* vs)
784 {
785 r300_emit_vertex_program_code(r300, &vs->code);
786 }
787
788 void r300_emit_vs_constant_buffer(struct r300_context* r300,
789 struct rc_constant_list* constants)
790 {
791 int i;
792 struct r300_screen* r300screen = r300_screen(r300->context.screen);
793 CS_LOCALS(r300);
794
795 if (!r300screen->caps->has_tcl) {
796 debug_printf("r300: Implementation error: emit_vertex_shader called,"
797 " but has_tcl is FALSE!\n");
798 return;
799 }
800
801 if (constants->Count == 0)
802 return;
803
804 BEGIN_CS(constants->Count * 4 + 3);
805 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
806 (r300screen->caps->is_r500 ?
807 R500_PVS_CONST_START : R300_PVS_CONST_START));
808 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
809 for (i = 0; i < constants->Count; i++) {
810 const float * data = get_shader_constant(r300,
811 &constants->Constants[i],
812 &r300->shader_constants[PIPE_SHADER_VERTEX]);
813 OUT_CS_32F(data[0]);
814 OUT_CS_32F(data[1]);
815 OUT_CS_32F(data[2]);
816 OUT_CS_32F(data[3]);
817 }
818 END_CS;
819 }
820
821 void r300_emit_viewport_state(struct r300_context* r300,
822 struct r300_viewport_state* viewport)
823 {
824 CS_LOCALS(r300);
825
826 BEGIN_CS(9);
827 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
828 OUT_CS_32F(viewport->xscale);
829 OUT_CS_32F(viewport->xoffset);
830 OUT_CS_32F(viewport->yscale);
831 OUT_CS_32F(viewport->yoffset);
832 OUT_CS_32F(viewport->zscale);
833 OUT_CS_32F(viewport->zoffset);
834
835 if (r300->rs_state->enable_vte) {
836 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
837 } else {
838 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
839 }
840 END_CS;
841 }
842
843 void r300_flush_textures(struct r300_context* r300)
844 {
845 CS_LOCALS(r300);
846
847 BEGIN_CS(4);
848 OUT_CS_REG(R300_TX_INVALTAGS, 0);
849 OUT_CS_REG(R300_TX_ENABLE, (1 << r300->texture_count) - 1);
850 END_CS;
851 }
852
853 static void r300_flush_pvs(struct r300_context* r300)
854 {
855 CS_LOCALS(r300);
856
857 BEGIN_CS(2);
858 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
859 END_CS;
860 }
861
862 /* Emit all dirty state. */
863 void r300_emit_dirty_state(struct r300_context* r300)
864 {
865 struct r300_screen* r300screen = r300_screen(r300->context.screen);
866 struct r300_texture* tex;
867 int i, dirty_tex = 0;
868 boolean invalid = FALSE;
869
870 if (!(r300->dirty_state)) {
871 return;
872 }
873
874 /* Clean out BOs. */
875 r300->winsys->reset_bos(r300->winsys);
876
877 /* XXX check size */
878 validate:
879 /* Color buffers... */
880 for (i = 0; i < r300->framebuffer_state.nr_cbufs; i++) {
881 tex = (struct r300_texture*)r300->framebuffer_state.cbufs[i]->texture;
882 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
883 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
884 0, RADEON_GEM_DOMAIN_VRAM)) {
885 r300->context.flush(&r300->context, 0, NULL);
886 goto validate;
887 }
888 }
889 /* ...depth buffer... */
890 if (r300->framebuffer_state.zsbuf) {
891 tex = (struct r300_texture*)r300->framebuffer_state.zsbuf->texture;
892 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
893 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
894 0, RADEON_GEM_DOMAIN_VRAM)) {
895 r300->context.flush(&r300->context, 0, NULL);
896 goto validate;
897 }
898 }
899 /* ...textures... */
900 for (i = 0; i < r300->texture_count; i++) {
901 tex = r300->textures[i];
902 if (!tex)
903 continue;
904 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
905 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
906 r300->context.flush(&r300->context, 0, NULL);
907 goto validate;
908 }
909 }
910 /* ...occlusion query buffer... */
911 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
912 0, RADEON_GEM_DOMAIN_GTT)) {
913 r300->context.flush(&r300->context, 0, NULL);
914 goto validate;
915 }
916 /* ...and vertex buffer. */
917 if (r300->vbo) {
918 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
919 RADEON_GEM_DOMAIN_GTT, 0)) {
920 r300->context.flush(&r300->context, 0, NULL);
921 goto validate;
922 }
923 } else {
924 // debug_printf("No VBO while emitting dirty state!\n");
925 }
926 if (!r300->winsys->validate(r300->winsys)) {
927 r300->context.flush(&r300->context, 0, NULL);
928 if (invalid) {
929 /* Well, hell. */
930 debug_printf("r300: Stuck in validation loop, gonna quit now.");
931 exit(1);
932 }
933 invalid = TRUE;
934 goto validate;
935 }
936
937 if (r300->dirty_state & R300_NEW_QUERY) {
938 r300_emit_query_start(r300);
939 r300->dirty_state &= ~R300_NEW_QUERY;
940 }
941
942 if (r300->dirty_state & R300_NEW_BLEND) {
943 r300_emit_blend_state(r300, r300->blend_state);
944 r300->dirty_state &= ~R300_NEW_BLEND;
945 }
946
947 if (r300->dirty_state & R300_NEW_BLEND_COLOR) {
948 r300_emit_blend_color_state(r300, r300->blend_color_state);
949 r300->dirty_state &= ~R300_NEW_BLEND_COLOR;
950 }
951
952 if (r300->dirty_state & R300_NEW_CLIP) {
953 r300_emit_clip_state(r300, &r300->clip_state);
954 r300->dirty_state &= ~R300_NEW_CLIP;
955 }
956
957 if (r300->dirty_state & R300_NEW_DSA) {
958 r300_emit_dsa_state(r300, r300->dsa_state);
959 r300->dirty_state &= ~R300_NEW_DSA;
960 }
961
962 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
963 if (r300screen->caps->is_r500) {
964 r500_emit_fragment_program_code(r300, &r300->fs->code);
965 } else {
966 r300_emit_fragment_program_code(r300, &r300->fs->code);
967 }
968 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
969 }
970
971 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
972 if (r300screen->caps->is_r500) {
973 r500_emit_fs_constant_buffer(r300, &r300->fs->code.constants);
974 } else {
975 r300_emit_fs_constant_buffer(r300, &r300->fs->code.constants);
976 }
977 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
978 }
979
980 if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
981 r300_emit_fb_state(r300, &r300->framebuffer_state);
982 r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
983 }
984
985 if (r300->dirty_state & R300_NEW_RASTERIZER) {
986 r300_emit_rs_state(r300, r300->rs_state);
987 r300->dirty_state &= ~R300_NEW_RASTERIZER;
988 }
989
990 if (r300->dirty_state & R300_NEW_RS_BLOCK) {
991 r300_emit_rs_block_state(r300, r300->rs_block);
992 r300->dirty_state &= ~R300_NEW_RS_BLOCK;
993 }
994
995 if (r300->dirty_state & R300_NEW_SCISSOR) {
996 r300_emit_scissor_state(r300, r300->scissor_state);
997 r300->dirty_state &= ~R300_NEW_SCISSOR;
998 }
999
1000 /* Samplers and textures are tracked separately but emitted together. */
1001 if (r300->dirty_state &
1002 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1003 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1004 if (r300->dirty_state &
1005 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1006 if (r300->textures[i])
1007 r300_emit_texture(r300,
1008 r300->sampler_states[i],
1009 r300->textures[i],
1010 i);
1011 r300->dirty_state &=
1012 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1013 dirty_tex++;
1014 }
1015 }
1016 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1017 }
1018
1019 if (r300->dirty_state & R300_NEW_VIEWPORT) {
1020 r300_emit_viewport_state(r300, r300->viewport_state);
1021 r300->dirty_state &= ~R300_NEW_VIEWPORT;
1022 }
1023
1024 if (dirty_tex) {
1025 r300_flush_textures(r300);
1026 }
1027
1028 if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
1029 r300_emit_vertex_format_state(r300);
1030 r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
1031 }
1032
1033 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1034 r300_flush_pvs(r300);
1035 }
1036
1037 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1038 r300_emit_vertex_shader(r300, r300->vs);
1039 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1040 }
1041
1042 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1043 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1044 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1045 }
1046
1047 /* XXX
1048 assert(r300->dirty_state == 0);
1049 */
1050
1051 /* Finally, emit the VBO. */
1052 //r300_emit_vertex_buffer(r300);
1053
1054 r300->dirty_hw++;
1055 }