2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
30 #include "r300_context.h"
33 #include "r300_emit.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
39 void r300_emit_blend_state(struct r300_context
* r300
,
40 unsigned size
, void* state
)
42 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
43 struct pipe_framebuffer_state
* fb
=
44 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
45 struct pipe_surface
*cb
;
48 cb
= fb
->nr_cbufs
? r300_get_nonnull_cb(fb
, 0) : NULL
;
51 if (cb
->format
== PIPE_FORMAT_R16G16B16A16_FLOAT
) {
52 WRITE_CS_TABLE(blend
->cb_noclamp
, size
);
53 } else if (cb
->format
== PIPE_FORMAT_R16G16B16X16_FLOAT
) {
54 WRITE_CS_TABLE(blend
->cb_noclamp_noalpha
, size
);
56 unsigned swz
= r300_surface(cb
)->colormask_swizzle
;
57 WRITE_CS_TABLE(blend
->cb_clamp
[swz
], size
);
60 WRITE_CS_TABLE(blend
->cb_no_readwrite
, size
);
64 void r300_emit_blend_color_state(struct r300_context
* r300
,
65 unsigned size
, void* state
)
67 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
70 WRITE_CS_TABLE(bc
->cb
, size
);
73 void r300_emit_clip_state(struct r300_context
* r300
,
74 unsigned size
, void* state
)
76 struct r300_clip_state
* clip
= (struct r300_clip_state
*)state
;
79 WRITE_CS_TABLE(clip
->cb
, size
);
82 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
84 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
85 struct pipe_framebuffer_state
* fb
=
86 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
87 boolean is_r500
= r300
->screen
->caps
.is_r500
;
89 uint32_t alpha_func
= dsa
->alpha_function
;
91 /* Choose the alpha ref value between 8-bit (FG_ALPHA_FUNC.AM_VAL) and
92 * 16-bit (FG_ALPHA_VALUE). */
93 if (is_r500
&& (alpha_func
& R300_FG_ALPHA_FUNC_ENABLE
)) {
94 struct pipe_surface
*cb
= fb
->nr_cbufs
? r300_get_nonnull_cb(fb
, 0) : NULL
;
97 (cb
->format
== PIPE_FORMAT_R16G16B16A16_FLOAT
||
98 cb
->format
== PIPE_FORMAT_R16G16B16X16_FLOAT
)) {
99 alpha_func
|= R500_FG_ALPHA_FUNC_FP16_ENABLE
;
101 alpha_func
|= R500_FG_ALPHA_FUNC_8BIT
;
105 /* Setup alpha-to-coverage. */
106 if (r300
->alpha_to_coverage
&& r300
->msaa_enable
) {
107 /* Always set 3/6, it improves precision even for 2x and 4x MSAA. */
108 alpha_func
|= R300_FG_ALPHA_FUNC_MASK_ENABLE
|
109 R300_FG_ALPHA_FUNC_CFG_3_OF_6
;
113 OUT_CS_REG(R300_FG_ALPHA_FUNC
, alpha_func
);
114 OUT_CS_TABLE(fb
->zsbuf
? &dsa
->cb_begin
: dsa
->cb_zb_no_readwrite
, size
-2);
118 static void get_rc_constant_state(
120 struct r300_context
* r300
,
121 struct rc_constant
* constant
)
123 struct r300_textures_state
* texstate
= r300
->textures_state
.state
;
124 struct r300_resource
*tex
;
126 assert(constant
->Type
== RC_CONSTANT_STATE
);
128 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
129 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
132 switch (constant
->u
.State
[0]) {
133 /* Factor for converting rectangle coords to
134 * normalized coords. Should only show up on non-r500. */
135 case RC_STATE_R300_TEXRECT_FACTOR
:
136 tex
= r300_resource(texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
);
137 vec
[0] = 1.0 / tex
->tex
.width0
;
138 vec
[1] = 1.0 / tex
->tex
.height0
;
143 case RC_STATE_R300_TEXSCALE_FACTOR
:
144 tex
= r300_resource(texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
);
145 /* Add a small number to the texture size to work around rounding errors in hw. */
146 vec
[0] = tex
->b
.b
.width0
/ (tex
->tex
.width0
+ 0.001f
);
147 vec
[1] = tex
->b
.b
.height0
/ (tex
->tex
.height0
+ 0.001f
);
148 vec
[2] = tex
->b
.b
.depth0
/ (tex
->tex
.depth0
+ 0.001f
);
152 case RC_STATE_R300_VIEWPORT_SCALE
:
153 vec
[0] = r300
->viewport
.scale
[0];
154 vec
[1] = r300
->viewport
.scale
[1];
155 vec
[2] = r300
->viewport
.scale
[2];
159 case RC_STATE_R300_VIEWPORT_OFFSET
:
160 vec
[0] = r300
->viewport
.translate
[0];
161 vec
[1] = r300
->viewport
.translate
[1];
162 vec
[2] = r300
->viewport
.translate
[2];
167 fprintf(stderr
, "r300: Implementation error: "
168 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
176 /* Convert a normal single-precision float into the 7.16 format
177 * used by the R300 fragment shader.
179 uint32_t pack_float24(float f
)
187 uint32_t float24
= 0;
194 mantissa
= frexpf(f
, &exponent
);
198 float24
|= (1 << 23);
199 mantissa
= mantissa
* -1.0;
201 /* Handle exponent, bias of 63 */
203 float24
|= (exponent
<< 16);
204 /* Kill 7 LSB of mantissa */
205 float24
|= (u
.u
& 0x7FFFFF) >> 7;
210 void r300_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
212 struct r300_fragment_shader
*fs
= r300_fs(r300
);
215 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
218 void r300_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
220 struct r300_fragment_shader
*fs
= r300_fs(r300
);
221 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
222 unsigned count
= fs
->shader
->externals_count
;
230 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, count
* 4);
231 if (buf
->remap_table
){
232 for (i
= 0; i
< count
; i
++) {
233 float *data
= (float*)&buf
->ptr
[buf
->remap_table
[i
]*4];
234 for (j
= 0; j
< 4; j
++)
235 OUT_CS(pack_float24(data
[j
]));
238 for (i
= 0; i
< count
; i
++)
239 for (j
= 0; j
< 4; j
++)
240 OUT_CS(pack_float24(*(float*)&buf
->ptr
[i
*4+j
]));
246 void r300_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
248 struct r300_fragment_shader
*fs
= r300_fs(r300
);
249 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
251 unsigned count
= fs
->shader
->rc_state_count
;
252 unsigned first
= fs
->shader
->externals_count
;
253 unsigned end
= constants
->Count
;
261 for(i
= first
; i
< end
; ++i
) {
262 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
265 get_rc_constant_state(data
, r300
, &constants
->Constants
[i
]);
267 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
268 for (j
= 0; j
< 4; j
++)
269 OUT_CS(pack_float24(data
[j
]));
275 void r500_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
277 struct r300_fragment_shader
*fs
= r300_fs(r300
);
280 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
283 void r500_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
285 struct r300_fragment_shader
*fs
= r300_fs(r300
);
286 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
287 unsigned count
= fs
->shader
->externals_count
;
294 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
295 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, count
* 4);
296 if (buf
->remap_table
){
297 for (unsigned i
= 0; i
< count
; i
++) {
298 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
299 OUT_CS_TABLE(data
, 4);
302 OUT_CS_TABLE(buf
->ptr
, count
* 4);
307 void r500_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
309 struct r300_fragment_shader
*fs
= r300_fs(r300
);
310 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
312 unsigned count
= fs
->shader
->rc_state_count
;
313 unsigned first
= fs
->shader
->externals_count
;
314 unsigned end
= constants
->Count
;
321 for(i
= first
; i
< end
; ++i
) {
322 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
325 get_rc_constant_state(data
, r300
, &constants
->Constants
[i
]);
327 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
328 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
329 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
330 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
331 OUT_CS_TABLE(data
, 4);
337 void r300_emit_gpu_flush(struct r300_context
*r300
, unsigned size
, void *state
)
339 struct r300_gpu_flush
*gpuflush
= (struct r300_gpu_flush
*)state
;
340 struct pipe_framebuffer_state
* fb
=
341 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
342 uint32_t height
= fb
->height
;
343 uint32_t width
= fb
->width
;
346 if (r300
->cbzb_clear
) {
347 struct r300_surface
*surf
= r300_surface(fb
->cbufs
[0]);
349 height
= surf
->cbzb_height
;
350 width
= surf
->cbzb_width
;
353 DBG(r300
, DBG_SCISSOR
,
354 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
355 width
, height
, r300
->cbzb_clear
? "YES" : "NO");
360 * By writing to the SC registers, SC & US assert idle. */
361 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
362 if (r300
->screen
->caps
.is_r500
) {
364 OUT_CS(((width
- 1) << R300_SCISSORS_X_SHIFT
) |
365 ((height
- 1) << R300_SCISSORS_Y_SHIFT
));
367 OUT_CS((1440 << R300_SCISSORS_X_SHIFT
) |
368 (1440 << R300_SCISSORS_Y_SHIFT
));
369 OUT_CS(((width
+ 1440-1) << R300_SCISSORS_X_SHIFT
) |
370 ((height
+ 1440-1) << R300_SCISSORS_Y_SHIFT
));
373 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
374 OUT_CS_TABLE(gpuflush
->cb_flush_clean
, 6);
378 void r300_emit_aa_state(struct r300_context
*r300
, unsigned size
, void *state
)
380 struct r300_aa_state
*aa
= (struct r300_aa_state
*)state
;
384 OUT_CS_REG(R300_GB_AA_CONFIG
, aa
->aa_config
);
387 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET
, 3);
388 OUT_CS(aa
->dest
->offset
);
389 OUT_CS(aa
->dest
->pitch
& R300_RB3D_AARESOLVE_PITCH_MASK
);
390 OUT_CS(R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE
|
391 R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE
);
392 OUT_CS_RELOC(aa
->dest
);
394 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL
, 0);
400 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
402 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
403 struct r300_surface
* surf
;
405 uint32_t rb3d_cctl
= 0;
411 if (r300
->screen
->caps
.is_r500
) {
412 rb3d_cctl
= R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
;
414 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers. */
415 if (fb
->nr_cbufs
&& r300
->fb_multiwrite
) {
416 rb3d_cctl
|= R300_RB3D_CCTL_NUM_MULTIWRITES(fb
->nr_cbufs
);
418 if (r300
->cmask_in_use
) {
419 rb3d_cctl
|= R300_RB3D_CCTL_AA_COMPRESSION_ENABLE
|
420 R300_RB3D_CCTL_CMASK_ENABLE
;
423 OUT_CS_REG(R300_RB3D_CCTL
, rb3d_cctl
);
425 /* Set up colorbuffers. */
426 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
427 surf
= r300_surface(r300_get_nonnull_cb(fb
, i
));
429 OUT_CS_REG(R300_RB3D_COLOROFFSET0
+ (4 * i
), surf
->offset
);
432 OUT_CS_REG(R300_RB3D_COLORPITCH0
+ (4 * i
), surf
->pitch
);
435 if (r300
->cmask_in_use
&& i
== 0) {
436 OUT_CS_REG(R300_RB3D_CMASK_OFFSET0
, 0);
437 OUT_CS_REG(R300_RB3D_CMASK_PITCH0
, surf
->pitch_cmask
);
438 OUT_CS_REG(R300_RB3D_COLOR_CLEAR_VALUE
, r300
->color_clear_value
);
439 if (r300
->screen
->caps
.is_r500
&& r300
->screen
->info
.drm_minor
>= 29) {
440 OUT_CS_REG_SEQ(R500_RB3D_COLOR_CLEAR_VALUE_AR
, 2);
441 OUT_CS(r300
->color_clear_value_ar
);
442 OUT_CS(r300
->color_clear_value_gb
);
447 /* Set up the ZB part of the CBZB clear. */
448 if (r300
->cbzb_clear
) {
449 surf
= r300_surface(fb
->cbufs
[0]);
451 OUT_CS_REG(R300_ZB_FORMAT
, surf
->cbzb_format
);
453 OUT_CS_REG(R300_ZB_DEPTHOFFSET
, surf
->cbzb_midpoint_offset
);
456 OUT_CS_REG(R300_ZB_DEPTHPITCH
, surf
->cbzb_pitch
);
460 "CBZB clearing cbuf %08x %08x\n", surf
->cbzb_format
,
463 /* Set up a zbuffer. */
464 else if (fb
->zsbuf
) {
465 surf
= r300_surface(fb
->zsbuf
);
467 OUT_CS_REG(R300_ZB_FORMAT
, surf
->format
);
469 OUT_CS_REG(R300_ZB_DEPTHOFFSET
, surf
->offset
);
472 OUT_CS_REG(R300_ZB_DEPTHPITCH
, surf
->pitch
);
475 if (r300
->hyperz_enabled
) {
477 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, 0);
478 OUT_CS_REG(R300_ZB_HIZ_PITCH
, surf
->pitch_hiz
);
479 /* Z Mask RAM. (compressed zbuffer) */
480 OUT_CS_REG(R300_ZB_ZMASK_OFFSET
, 0);
481 OUT_CS_REG(R300_ZB_ZMASK_PITCH
, surf
->pitch_zmask
);
488 void r300_emit_hyperz_state(struct r300_context
*r300
,
489 unsigned size
, void *state
)
491 struct r300_hyperz_state
*z
= state
;
495 WRITE_CS_TABLE(&z
->cb_flush_begin
, size
);
497 WRITE_CS_TABLE(&z
->cb_begin
, size
- 2);
500 void r300_emit_hyperz_end(struct r300_context
*r300
)
502 struct r300_hyperz_state z
=
503 *(struct r300_hyperz_state
*)r300
->hyperz_state
.state
;
507 z
.zb_depthclearvalue
= 0;
508 z
.sc_hyperz
= R300_SC_HYPERZ_ADJ_2
;
509 z
.gb_z_peq_config
= 0;
511 r300_emit_hyperz_state(r300
, r300
->hyperz_state
.size
, &z
);
514 #define R300_NIBBLES(x0, y0, x1, y1, x2, y2, d0y, d0x) \
515 (((x0) & 0xf) | (((y0) & 0xf) << 4) | \
516 (((x1) & 0xf) << 8) | (((y1) & 0xf) << 12) | \
517 (((x2) & 0xf) << 16) | (((y2) & 0xf) << 20) | \
518 (((d0y) & 0xf) << 24) | (((d0x) & 0xf) << 28))
520 static unsigned r300_get_mspos(int index
, unsigned *p
)
522 unsigned reg
, i
, distx
, disty
, dist
;
525 /* MSPOS0 contains positions for samples 0,1,2 as (X,Y) pairs of nibbles,
526 * followed by a (Y,X) pair containing the minimum distance from the pixel
528 * X0, Y0, X1, Y1, X2, Y2, D0_Y, D0_X
530 * There is a quirk when setting D0_X. The value represents the distance
531 * from the left edge of the pixel quad to the first sample in subpixels.
532 * All values less than eight should use the actual value, but „7‟ should
533 * be used for the distance „8‟. The hardware will convert 7 into 8 internally.
536 for (i
= 0; i
< 12; i
+= 2) {
542 for (i
= 1; i
< 12; i
+= 2) {
550 reg
= R300_NIBBLES(p
[0], p
[1], p
[2], p
[3], p
[4], p
[5], disty
, distx
);
552 /* MSPOS1 contains positions for samples 3,4,5 as (X,Y) pairs of nibbles,
553 * followed by the minimum distance from the pixel edge (not sure if X or Y):
554 * X3, Y3, X4, Y4, X5, Y5, D1
557 for (i
= 0; i
< 12; i
++) {
562 reg
= R300_NIBBLES(p
[6], p
[7], p
[8], p
[9], p
[10], p
[11], dist
, 0);
567 void r300_emit_fb_state_pipelined(struct r300_context
*r300
,
568 unsigned size
, void *state
)
570 /* The sample coordinates are in the range [0,11], because
571 * GB_TILE_CONFIG.SUBPIXEL is set to the 1/12 subpixel precision.
573 * Some sample coordinates reach to neighboring pixels and should not be used.
576 * The unused samples must be set to the positions of other valid samples. */
577 static unsigned sample_locs_1x
[12] = {
578 6,6, 6,6, 6,6, 6,6, 6,6, 6,6
580 static unsigned sample_locs_2x
[12] = {
581 3,9, 9,3, 9,3, 9,3, 9,3, 9,3
583 static unsigned sample_locs_4x
[12] = {
584 4,4, 8,8, 2,10, 10,2, 10,2, 10,2
586 static unsigned sample_locs_6x
[12] = {
587 3,1, 7,3, 11,5, 1,7, 5,9, 9,10
590 struct pipe_framebuffer_state
* fb
=
591 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
592 unsigned i
, num_cbufs
= fb
->nr_cbufs
;
593 unsigned mspos0
, mspos1
;
596 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be
597 * marked as UNUSED in the US block. */
598 if (r300
->fb_multiwrite
) {
599 num_cbufs
= MIN2(num_cbufs
, 1);
604 /* Colorbuffer format in the US block.
605 * (must be written after unpipelined regs) */
606 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0
, 4);
607 for (i
= 0; i
< num_cbufs
; i
++) {
608 OUT_CS(r300_surface(r300_get_nonnull_cb(fb
, i
))->format
);
611 OUT_CS(R300_US_OUT_FMT_C4_8
|
612 R300_C0_SEL_B
| R300_C1_SEL_G
|
613 R300_C2_SEL_R
| R300_C3_SEL_A
);
616 OUT_CS(R300_US_OUT_FMT_UNUSED
);
619 /* Set sample positions. It depends on the framebuffer sample count.
620 * These are pipelined regs and as such cannot be moved to the AA state.
622 switch (r300
->num_samples
) {
624 mspos0
= r300_get_mspos(0, sample_locs_1x
);
625 mspos1
= r300_get_mspos(1, sample_locs_1x
);
628 mspos0
= r300_get_mspos(0, sample_locs_2x
);
629 mspos1
= r300_get_mspos(1, sample_locs_2x
);
632 mspos0
= r300_get_mspos(0, sample_locs_4x
);
633 mspos1
= r300_get_mspos(1, sample_locs_4x
);
636 mspos0
= r300_get_mspos(0, sample_locs_6x
);
637 mspos1
= r300_get_mspos(1, sample_locs_6x
);
641 OUT_CS_REG_SEQ(R300_GB_MSPOS0
, 2);
647 void r300_emit_query_start(struct r300_context
*r300
, unsigned size
, void*state
)
649 struct r300_query
*query
= r300
->query_current
;
656 if (r300
->screen
->caps
.family
== CHIP_RV530
) {
657 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
659 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
661 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
663 query
->begin_emitted
= TRUE
;
666 static void r300_emit_query_end_frag_pipes(struct r300_context
*r300
,
667 struct r300_query
*query
)
669 struct r300_capabilities
* caps
= &r300
->screen
->caps
;
670 uint32_t gb_pipes
= r300
->screen
->info
.r300_num_gb_pipes
;
675 BEGIN_CS(6 * gb_pipes
+ 2);
676 /* I'm not so sure I like this switch, but it's hard to be elegant
677 * when there's so many special cases...
679 * So here's the basic idea. For each pipe, enable writes to it only,
680 * then put out the relocation for ZPASS_ADDR, taking into account a
681 * 4-byte offset for each pipe. RV380 and older are special; they have
682 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
683 * so there's a chipset cap for that. */
687 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
688 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 3) * 4);
689 OUT_CS_RELOC(r300
->query_current
);
692 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
693 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 2) * 4);
694 OUT_CS_RELOC(r300
->query_current
);
697 /* As mentioned above, accommodate RV380 and older. */
698 OUT_CS_REG(R300_SU_REG_DEST
,
699 1 << (caps
->high_second_pipe
? 3 : 1));
700 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 1) * 4);
701 OUT_CS_RELOC(r300
->query_current
);
704 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
705 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 0) * 4);
706 OUT_CS_RELOC(r300
->query_current
);
709 fprintf(stderr
, "r300: Implementation error: Chipset reports %d"
710 " pixel pipes!\n", gb_pipes
);
714 /* And, finally, reset it to normal... */
715 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
719 static void rv530_emit_query_end_single_z(struct r300_context
*r300
,
720 struct r300_query
*query
)
725 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
726 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, query
->num_results
* 4);
727 OUT_CS_RELOC(r300
->query_current
);
728 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
732 static void rv530_emit_query_end_double_z(struct r300_context
*r300
,
733 struct r300_query
*query
)
738 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
739 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 0) * 4);
740 OUT_CS_RELOC(r300
->query_current
);
741 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
742 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 1) * 4);
743 OUT_CS_RELOC(r300
->query_current
);
744 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
748 void r300_emit_query_end(struct r300_context
* r300
)
750 struct r300_capabilities
*caps
= &r300
->screen
->caps
;
751 struct r300_query
*query
= r300
->query_current
;
756 if (query
->begin_emitted
== FALSE
)
759 if (caps
->family
== CHIP_RV530
) {
760 if (r300
->screen
->info
.r300_num_z_pipes
== 2)
761 rv530_emit_query_end_double_z(r300
, query
);
763 rv530_emit_query_end_single_z(r300
, query
);
765 r300_emit_query_end_frag_pipes(r300
, query
);
767 query
->begin_emitted
= FALSE
;
768 query
->num_results
+= query
->num_pipes
;
770 /* XXX grab all the results and reset the counter. */
771 if (query
->num_results
>= query
->buf
->size
/ 4 - 4) {
772 query
->num_results
= (query
->buf
->size
/ 4) / 2;
773 fprintf(stderr
, "r300: Rewinding OQBO...\n");
777 void r300_emit_invariant_state(struct r300_context
*r300
,
778 unsigned size
, void *state
)
781 WRITE_CS_TABLE(state
, size
);
784 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
786 struct r300_rs_state
* rs
= state
;
790 OUT_CS_TABLE(rs
->cb_main
, RS_STATE_MAIN_SIZE
);
791 if (rs
->polygon_offset_enable
) {
792 if (r300
->zbuffer_bpp
== 16) {
793 OUT_CS_TABLE(rs
->cb_poly_offset_zb16
, 5);
795 OUT_CS_TABLE(rs
->cb_poly_offset_zb24
, 5);
801 void r300_emit_rs_block_state(struct r300_context
* r300
,
802 unsigned size
, void* state
)
804 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
806 /* It's the same for both INST and IP tables */
807 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
810 if (DBG_ON(r300
, DBG_RS_BLOCK
)) {
811 r500_dump_rs_block(rs
);
813 fprintf(stderr
, "r300: RS emit:\n");
815 for (i
= 0; i
< count
; i
++)
816 fprintf(stderr
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
818 for (i
= 0; i
< count
; i
++)
819 fprintf(stderr
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
821 fprintf(stderr
, " : count: 0x%08x inst_count: 0x%08x\n",
822 rs
->count
, rs
->inst_count
);
826 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
827 OUT_CS(rs
->vap_vtx_state_cntl
);
828 OUT_CS(rs
->vap_vsm_vtx_assm
);
829 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
830 OUT_CS(rs
->vap_out_vtx_fmt
[0]);
831 OUT_CS(rs
->vap_out_vtx_fmt
[1]);
832 OUT_CS_REG_SEQ(R300_GB_ENABLE
, 1);
833 OUT_CS(rs
->gb_enable
);
835 if (r300
->screen
->caps
.is_r500
) {
836 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
838 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
840 OUT_CS_TABLE(rs
->ip
, count
);
842 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
844 OUT_CS(rs
->inst_count
);
846 if (r300
->screen
->caps
.is_r500
) {
847 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
849 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
851 OUT_CS_TABLE(rs
->inst
, count
);
855 void r300_emit_sample_mask(struct r300_context
*r300
,
856 unsigned size
, void *state
)
858 unsigned mask
= (*(unsigned*)state
) & ((1 << 6)-1);
862 OUT_CS_REG(R300_SC_SCREENDOOR
,
863 mask
| (mask
<< 6) | (mask
<< 12) | (mask
<< 18));
867 void r300_emit_scissor_state(struct r300_context
* r300
,
868 unsigned size
, void* state
)
870 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
874 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0
, 2);
875 if (r300
->screen
->caps
.is_r500
) {
876 OUT_CS((scissor
->minx
<< R300_CLIPRECT_X_SHIFT
) |
877 (scissor
->miny
<< R300_CLIPRECT_Y_SHIFT
));
878 OUT_CS(((scissor
->maxx
- 1) << R300_CLIPRECT_X_SHIFT
) |
879 ((scissor
->maxy
- 1) << R300_CLIPRECT_Y_SHIFT
));
881 OUT_CS(((scissor
->minx
+ 1440) << R300_CLIPRECT_X_SHIFT
) |
882 ((scissor
->miny
+ 1440) << R300_CLIPRECT_Y_SHIFT
));
883 OUT_CS(((scissor
->maxx
+ 1440-1) << R300_CLIPRECT_X_SHIFT
) |
884 ((scissor
->maxy
+ 1440-1) << R300_CLIPRECT_Y_SHIFT
));
889 void r300_emit_textures_state(struct r300_context
*r300
,
890 unsigned size
, void *state
)
892 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
893 struct r300_texture_sampler_state
*texstate
;
894 struct r300_resource
*tex
;
896 boolean has_us_format
= r300
->screen
->caps
.has_us_format
;
900 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
902 for (i
= 0; i
< allstate
->count
; i
++) {
903 if ((1 << i
) & allstate
->tx_enable
) {
904 texstate
= &allstate
->regs
[i
];
905 tex
= r300_resource(allstate
->sampler_views
[i
]->base
.texture
);
907 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter0
);
908 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter1
);
909 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
910 texstate
->border_color
);
912 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
.format0
);
913 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
.format1
);
914 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
.format2
);
916 OUT_CS_REG(R300_TX_OFFSET_0
+ (i
* 4), texstate
->format
.tile_config
);
920 OUT_CS_REG(R500_US_FORMAT0_0
+ (i
* 4),
921 texstate
->format
.us_format0
);
928 void r300_emit_vertex_arrays(struct r300_context
* r300
, int offset
,
929 boolean indexed
, int instance_id
)
931 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
932 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
933 struct r300_resource
*buf
;
935 unsigned vertex_array_count
= r300
->velems
->count
;
936 unsigned packet_size
= (vertex_array_count
* 3 + 1) / 2;
937 struct pipe_vertex_buffer
*vb1
, *vb2
;
938 unsigned *hw_format_size
= r300
->velems
->format_size
;
939 unsigned size1
, size2
, offset1
, offset2
, stride1
, stride2
;
942 BEGIN_CS(2 + packet_size
+ vertex_array_count
* 2);
943 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
944 OUT_CS(vertex_array_count
| (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
946 if (instance_id
== -1) {
947 /* Non-instanced arrays. This ignores instance_divisor and instance_id. */
948 for (i
= 0; i
< vertex_array_count
- 1; i
+= 2) {
949 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
950 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
951 size1
= hw_format_size
[i
];
952 size2
= hw_format_size
[i
+1];
954 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
955 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
956 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
957 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
960 if (vertex_array_count
& 1) {
961 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
962 size1
= hw_format_size
[i
];
964 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
965 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
968 for (i
= 0; i
< vertex_array_count
; i
++) {
969 buf
= r300_resource(vbuf
[velem
[i
].vertex_buffer_index
].buffer
);
973 /* Instanced arrays. */
974 for (i
= 0; i
< vertex_array_count
- 1; i
+= 2) {
975 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
976 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
977 size1
= hw_format_size
[i
];
978 size2
= hw_format_size
[i
+1];
980 if (velem
[i
].instance_divisor
) {
982 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+
983 (instance_id
/ velem
[i
].instance_divisor
) * vb1
->stride
;
985 stride1
= vb1
->stride
;
986 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
;
988 if (velem
[i
+1].instance_divisor
) {
990 offset2
= vb2
->buffer_offset
+ velem
[i
+1].src_offset
+
991 (instance_id
/ velem
[i
+1].instance_divisor
) * vb2
->stride
;
993 stride2
= vb2
->stride
;
994 offset2
= vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
;
997 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(stride1
) |
998 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(stride2
));
1003 if (vertex_array_count
& 1) {
1004 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
1005 size1
= hw_format_size
[i
];
1007 if (velem
[i
].instance_divisor
) {
1009 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+
1010 (instance_id
/ velem
[i
].instance_divisor
) * vb1
->stride
;
1012 stride1
= vb1
->stride
;
1013 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
;
1016 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(stride1
));
1020 for (i
= 0; i
< vertex_array_count
; i
++) {
1021 buf
= r300_resource(vbuf
[velem
[i
].vertex_buffer_index
].buffer
);
1028 void r300_emit_vertex_arrays_swtcl(struct r300_context
*r300
, boolean indexed
)
1032 DBG(r300
, DBG_SWTCL
, "r300: Preparing vertex buffer %p for render, "
1033 "vertex size %d\n", r300
->vbo
,
1034 r300
->vertex_info
.size
);
1035 /* Set the pointer to our vertex buffer. The emitted values are this:
1036 * PACKET3 [3D_LOAD_VBPNTR]
1038 * FORMAT [size | stride << 8]
1039 * OFFSET [offset into BO]
1040 * VBPNTR [relocated BO]
1043 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
1044 OUT_CS(1 | (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
1045 OUT_CS(r300
->vertex_info
.size
|
1046 (r300
->vertex_info
.size
<< 8));
1047 OUT_CS(r300
->draw_vbo_offset
);
1051 OUT_CS(0xc0001000); /* PKT3_NOP */
1052 OUT_CS(r300
->rws
->cs_lookup_buffer(r300
->cs
, r300
->vbo
) * 4);
1056 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
1057 unsigned size
, void* state
)
1059 struct r300_vertex_stream_state
*streams
=
1060 (struct r300_vertex_stream_state
*)state
;
1064 if (DBG_ON(r300
, DBG_PSC
)) {
1065 fprintf(stderr
, "r300: PSC emit:\n");
1067 for (i
= 0; i
< streams
->count
; i
++) {
1068 fprintf(stderr
, " : prog_stream_cntl%d: 0x%08x\n", i
,
1069 streams
->vap_prog_stream_cntl
[i
]);
1072 for (i
= 0; i
< streams
->count
; i
++) {
1073 fprintf(stderr
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
1074 streams
->vap_prog_stream_cntl_ext
[i
]);
1079 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
1080 OUT_CS_TABLE(streams
->vap_prog_stream_cntl
, streams
->count
);
1081 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
1082 OUT_CS_TABLE(streams
->vap_prog_stream_cntl_ext
, streams
->count
);
1086 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
1091 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
1095 void r300_emit_vap_invariant_state(struct r300_context
*r300
,
1096 unsigned size
, void *state
)
1099 WRITE_CS_TABLE(state
, size
);
1102 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
1104 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
1105 struct r300_vertex_program_code
* code
= &vs
->code
;
1106 struct r300_screen
* r300screen
= r300
->screen
;
1107 unsigned instruction_count
= code
->length
/ 4;
1109 unsigned vtx_mem_size
= r300screen
->caps
.is_r500
? 128 : 72;
1110 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
1111 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
1112 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
1114 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
1115 vtx_mem_size
/ output_count
, 10);
1116 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 5);
1122 /* R300_VAP_PVS_CODE_CNTL_0
1123 * R300_VAP_PVS_CONST_CNTL
1124 * R300_VAP_PVS_CODE_CNTL_1
1125 * See the r5xx docs for instructions on how to use these. */
1126 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0
, R300_PVS_FIRST_INST(0) |
1127 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
1128 R300_PVS_LAST_INST(instruction_count
- 1));
1129 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1
, instruction_count
- 1);
1131 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
1132 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
1133 OUT_CS_TABLE(code
->body
.d
, code
->length
);
1135 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
1136 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
1137 R300_PVS_NUM_FPUS(r300screen
->caps
.num_vert_fpus
) |
1138 R300_PVS_VF_MAX_VTX_NUM(12) |
1139 (r300
->clip_halfz
? R300_DX_CLIP_SPACE_DEF
: 0) |
1140 (r300screen
->caps
.is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
1142 /* Emit flow control instructions. Even if there are no fc instructions,
1143 * we still need to write the registers to make sure they are cleared. */
1144 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC
, code
->fc_ops
);
1145 if (r300screen
->caps
.is_r500
) {
1146 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0
, R300_VS_MAX_FC_OPS
* 2);
1147 OUT_CS_TABLE(code
->fc_op_addrs
.r500
, R300_VS_MAX_FC_OPS
* 2);
1149 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0
, R300_VS_MAX_FC_OPS
);
1150 OUT_CS_TABLE(code
->fc_op_addrs
.r300
, R300_VS_MAX_FC_OPS
);
1152 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
, R300_VS_MAX_FC_OPS
);
1153 OUT_CS_TABLE(code
->fc_loop_index
, R300_VS_MAX_FC_OPS
);
1158 void r300_emit_vs_constants(struct r300_context
* r300
,
1159 unsigned size
, void *state
)
1162 ((struct r300_vertex_shader
*)r300
->vs_state
.state
)->externals_count
;
1163 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
1164 struct r300_vertex_shader
*vs
= (struct r300_vertex_shader
*)r300
->vs_state
.state
;
1166 int imm_first
= vs
->externals_count
;
1167 int imm_end
= vs
->code
.constants
.Count
;
1168 int imm_count
= vs
->immediates_count
;
1172 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL
,
1173 R300_PVS_CONST_BASE_OFFSET(buf
->buffer_base
) |
1174 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end
- 1, 0)));
1175 if (vs
->externals_count
) {
1176 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1177 (r300
->screen
->caps
.is_r500
?
1178 R500_PVS_CONST_START
: R300_PVS_CONST_START
) + buf
->buffer_base
);
1179 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, count
* 4);
1180 if (buf
->remap_table
){
1181 for (i
= 0; i
< count
; i
++) {
1182 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
1183 OUT_CS_TABLE(data
, 4);
1186 OUT_CS_TABLE(buf
->ptr
, count
* 4);
1190 /* Emit immediates. */
1192 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1193 (r300
->screen
->caps
.is_r500
?
1194 R500_PVS_CONST_START
: R300_PVS_CONST_START
) +
1195 buf
->buffer_base
+ imm_first
);
1196 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, imm_count
* 4);
1197 for (i
= imm_first
; i
< imm_end
; i
++) {
1198 const float *data
= vs
->code
.constants
.Constants
[i
].u
.Immediate
;
1199 OUT_CS_TABLE(data
, 4);
1205 void r300_emit_viewport_state(struct r300_context
* r300
,
1206 unsigned size
, void* state
)
1208 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
1212 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
1213 OUT_CS_TABLE(&viewport
->xscale
, 6);
1214 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
1218 void r300_emit_hiz_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1220 struct pipe_framebuffer_state
*fb
=
1221 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1222 struct r300_resource
* tex
;
1225 tex
= r300_resource(fb
->zsbuf
->texture
);
1228 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ
, 2);
1230 OUT_CS(tex
->tex
.hiz_dwords
[fb
->zsbuf
->u
.tex
.level
]);
1231 OUT_CS(r300
->hiz_clear_value
);
1234 /* Mark the current zbuffer's hiz ram as in use. */
1235 r300
->hiz_in_use
= TRUE
;
1236 r300
->hiz_func
= HIZ_FUNC_NONE
;
1237 r300_mark_atom_dirty(r300
, &r300
->hyperz_state
);
1240 void r300_emit_zmask_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1242 struct pipe_framebuffer_state
*fb
=
1243 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1244 struct r300_resource
*tex
;
1247 tex
= r300_resource(fb
->zsbuf
->texture
);
1250 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK
, 2);
1252 OUT_CS(tex
->tex
.zmask_dwords
[fb
->zsbuf
->u
.tex
.level
]);
1256 /* Mark the current zbuffer's zmask as in use. */
1257 r300
->zmask_in_use
= TRUE
;
1258 r300_mark_atom_dirty(r300
, &r300
->hyperz_state
);
1261 void r300_emit_cmask_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1263 struct pipe_framebuffer_state
*fb
=
1264 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1265 struct r300_resource
*tex
;
1268 tex
= r300_resource(fb
->cbufs
[0]->texture
);
1271 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_CMASK
, 2);
1273 OUT_CS(tex
->tex
.cmask_dwords
);
1277 /* Mark the current zbuffer's zmask as in use. */
1278 r300
->cmask_in_use
= TRUE
;
1279 r300_mark_fb_state_dirty(r300
, R300_CHANGED_CMASK_ENABLE
);
1282 void r300_emit_ztop_state(struct r300_context
* r300
,
1283 unsigned size
, void* state
)
1285 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
1289 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
1293 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
1298 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
1302 boolean
r300_emit_buffer_validate(struct r300_context
*r300
,
1303 boolean do_validate_vertex_buffers
,
1304 struct pipe_resource
*index_buffer
)
1306 struct pipe_framebuffer_state
*fb
=
1307 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1308 struct r300_aa_state
*aa
= (struct r300_aa_state
*)r300
->aa_state
.state
;
1309 struct r300_textures_state
*texstate
=
1310 (struct r300_textures_state
*)r300
->textures_state
.state
;
1311 struct r300_resource
*tex
;
1313 boolean flushed
= FALSE
;
1316 if (r300
->fb_state
.dirty
) {
1317 /* Color buffers... */
1318 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1321 tex
= r300_resource(fb
->cbufs
[i
]->texture
);
1322 assert(tex
&& tex
->buf
&& "cbuf is marked, but NULL!");
1323 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->buf
,
1324 RADEON_USAGE_READWRITE
,
1325 r300_surface(fb
->cbufs
[i
])->domain
,
1326 tex
->b
.b
.nr_samples
> 1 ?
1327 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1328 RADEON_PRIO_COLOR_BUFFER
);
1330 /* ...depth buffer... */
1332 tex
= r300_resource(fb
->zsbuf
->texture
);
1333 assert(tex
&& tex
->buf
&& "zsbuf is marked, but NULL!");
1334 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->buf
,
1335 RADEON_USAGE_READWRITE
,
1336 r300_surface(fb
->zsbuf
)->domain
,
1337 tex
->b
.b
.nr_samples
> 1 ?
1338 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
1339 RADEON_PRIO_DEPTH_BUFFER
);
1342 /* The AA resolve buffer. */
1343 if (r300
->aa_state
.dirty
) {
1345 r300
->rws
->cs_add_buffer(r300
->cs
, aa
->dest
->buf
,
1348 RADEON_PRIO_COLOR_BUFFER
);
1351 if (r300
->textures_state
.dirty
) {
1352 /* ...textures... */
1353 for (i
= 0; i
< texstate
->count
; i
++) {
1354 if (!(texstate
->tx_enable
& (1 << i
))) {
1358 tex
= r300_resource(texstate
->sampler_views
[i
]->base
.texture
);
1359 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->buf
, RADEON_USAGE_READ
,
1360 tex
->domain
, RADEON_PRIO_SAMPLER_TEXTURE
);
1363 /* ...occlusion query buffer... */
1364 if (r300
->query_current
)
1365 r300
->rws
->cs_add_buffer(r300
->cs
, r300
->query_current
->buf
,
1366 RADEON_USAGE_WRITE
, RADEON_DOMAIN_GTT
,
1368 /* ...vertex buffer for SWTCL path... */
1370 r300
->rws
->cs_add_buffer(r300
->cs
, r300
->vbo
,
1371 RADEON_USAGE_READ
, RADEON_DOMAIN_GTT
,
1372 RADEON_PRIO_VERTEX_BUFFER
);
1373 /* ...vertex buffers for HWTCL path... */
1374 if (do_validate_vertex_buffers
&& r300
->vertex_arrays_dirty
) {
1375 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
1376 struct pipe_vertex_buffer
*last
= r300
->vertex_buffer
+
1377 r300
->nr_vertex_buffers
;
1378 struct pipe_resource
*buf
;
1380 for (; vbuf
!= last
; vbuf
++) {
1385 r300
->rws
->cs_add_buffer(r300
->cs
, r300_resource(buf
)->buf
,
1387 r300_resource(buf
)->domain
,
1388 RADEON_PRIO_SAMPLER_BUFFER
);
1391 /* ...and index buffer for HWTCL path. */
1393 r300
->rws
->cs_add_buffer(r300
->cs
, r300_resource(index_buffer
)->buf
,
1395 r300_resource(index_buffer
)->domain
,
1396 RADEON_PRIO_INDEX_BUFFER
);
1398 /* Now do the validation (flush is called inside cs_validate on failure). */
1399 if (!r300
->rws
->cs_validate(r300
->cs
)) {
1400 /* Ooops, an infinite loop, give up. */
1411 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
1413 struct r300_atom
* atom
;
1414 unsigned dwords
= 0;
1416 foreach_dirty_atom(r300
, atom
) {
1418 dwords
+= atom
->size
;
1422 /* let's reserve some more, just in case */
1428 unsigned r300_get_num_cs_end_dwords(struct r300_context
*r300
)
1430 unsigned dwords
= 0;
1432 /* Emitted in flush. */
1433 dwords
+= 26; /* emit_query_end */
1434 dwords
+= r300
->hyperz_state
.size
+ 2; /* emit_hyperz_end + zcache flush */
1435 if (r300
->screen
->caps
.is_r500
)
1436 dwords
+= 2; /* emit_index_bias */
1437 if (r300
->screen
->info
.drm_minor
>= 6)
1438 dwords
+= 3; /* MSPOS */
1443 /* Emit all dirty state. */
1444 void r300_emit_dirty_state(struct r300_context
* r300
)
1446 struct r300_atom
*atom
;
1448 foreach_dirty_atom(r300
, atom
) {
1450 atom
->emit(r300
, atom
->size
, atom
->state
);
1451 atom
->dirty
= FALSE
;
1455 r300
->first_dirty
= NULL
;
1456 r300
->last_dirty
= NULL
;