2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
30 #include "r300_context.h"
32 #include "r300_emit.h"
34 #include "r300_screen.h"
37 void r300_emit_blend_state(struct r300_context
* r300
,
38 unsigned size
, void* state
)
40 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
41 struct pipe_framebuffer_state
* fb
=
42 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
46 OUT_CS_REG(R300_RB3D_ROPCNTL
, blend
->rop
);
47 OUT_CS_REG_SEQ(R300_RB3D_CBLEND
, 3);
49 OUT_CS(blend
->blend_control
);
50 OUT_CS(blend
->alpha_blend_control
);
51 OUT_CS(blend
->color_channel_mask
);
56 /* XXX also disable fastfill here once it's supported */
58 OUT_CS_REG(R300_RB3D_DITHER_CTL
, blend
->dither
);
62 void r300_emit_blend_color_state(struct r300_context
* r300
,
63 unsigned size
, void* state
)
65 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
66 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
69 if (r300screen
->caps
->is_r500
) {
71 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR
, 2);
72 OUT_CS(bc
->blend_color_red_alpha
);
73 OUT_CS(bc
->blend_color_green_blue
);
77 OUT_CS_REG(R300_RB3D_BLEND_COLOR
, bc
->blend_color
);
82 void r300_emit_clip_state(struct r300_context
* r300
,
83 unsigned size
, void* state
)
85 struct pipe_clip_state
* clip
= (struct pipe_clip_state
*)state
;
87 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
90 if (r300screen
->caps
->has_tcl
) {
92 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
93 (r300screen
->caps
->is_r500
?
94 R500_PVS_UCP_START
: R300_PVS_UCP_START
));
95 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, 6 * 4);
96 for (i
= 0; i
< 6; i
++) {
97 OUT_CS_32F(clip
->ucp
[i
][0]);
98 OUT_CS_32F(clip
->ucp
[i
][1]);
99 OUT_CS_32F(clip
->ucp
[i
][2]);
100 OUT_CS_32F(clip
->ucp
[i
][3]);
102 OUT_CS_REG(R300_VAP_CLIP_CNTL
, ((1 << clip
->nr
) - 1) |
103 R300_PS_UCP_MODE_CLIP_AS_TRIFAN
);
107 OUT_CS_REG(R300_VAP_CLIP_CNTL
, R300_CLIP_DISABLE
);
113 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
115 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
116 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
117 struct pipe_framebuffer_state
* fb
=
118 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
119 struct pipe_stencil_ref stencil_ref
= r300
->stencil_ref
;
123 OUT_CS_REG(R300_FG_ALPHA_FUNC
, dsa
->alpha_function
);
124 OUT_CS_REG_SEQ(R300_ZB_CNTL
, 3);
127 OUT_CS(dsa
->z_buffer_control
);
128 OUT_CS(dsa
->z_stencil_control
);
134 OUT_CS(dsa
->stencil_ref_mask
| stencil_ref
.ref_value
[0]);
136 if (r300screen
->caps
->is_r500
) {
137 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF
, dsa
->stencil_ref_bf
| stencil_ref
.ref_value
[1]);
142 static const float * get_shader_constant(
143 struct r300_context
* r300
,
144 struct rc_constant
* constant
,
145 struct r300_constant_buffer
* externals
)
147 struct r300_viewport_state
* viewport
=
148 (struct r300_viewport_state
*)r300
->viewport_state
.state
;
149 struct r300_textures_state
* texstate
=
150 (struct r300_textures_state
*)r300
->textures_state
.state
;
151 static float vec
[4] = { 0.0, 0.0, 0.0, 1.0 };
152 struct pipe_texture
*tex
;
154 switch(constant
->Type
) {
155 case RC_CONSTANT_EXTERNAL
:
156 return externals
->constants
[constant
->u
.External
];
158 case RC_CONSTANT_IMMEDIATE
:
159 return constant
->u
.Immediate
;
161 case RC_CONSTANT_STATE
:
162 switch (constant
->u
.State
[0]) {
163 /* Factor for converting rectangle coords to
164 * normalized coords. Should only show up on non-r500. */
165 case RC_STATE_R300_TEXRECT_FACTOR
:
166 tex
= &texstate
->textures
[constant
->u
.State
[1]]->tex
;
167 vec
[0] = 1.0 / tex
->width0
;
168 vec
[1] = 1.0 / tex
->height0
;
171 /* Texture compare-fail value. Shouldn't ever show up, but if
172 * it does, we'll be ready. */
173 case RC_STATE_SHADOW_AMBIENT
:
177 case RC_STATE_R300_VIEWPORT_SCALE
:
178 vec
[0] = viewport
->xscale
;
179 vec
[1] = viewport
->yscale
;
180 vec
[2] = viewport
->zscale
;
183 case RC_STATE_R300_VIEWPORT_OFFSET
:
184 vec
[0] = viewport
->xoffset
;
185 vec
[1] = viewport
->yoffset
;
186 vec
[2] = viewport
->zoffset
;
190 debug_printf("r300: Implementation error: "
191 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
196 debug_printf("r300: Implementation error: "
197 "Unhandled constant type %d\n", constant
->Type
);
200 /* This should either be (0, 0, 0, 1), which should be a relatively safe
201 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
206 /* Convert a normal single-precision float into the 7.16 format
207 * used by the R300 fragment shader.
209 static uint32_t pack_float24(float f
)
217 uint32_t float24
= 0;
224 mantissa
= frexpf(f
, &exponent
);
228 float24
|= (1 << 23);
229 mantissa
= mantissa
* -1.0;
231 /* Handle exponent, bias of 63 */
233 float24
|= (exponent
<< 16);
234 /* Kill 7 LSB of mantissa */
235 float24
|= (u
.u
& 0x7FFFFF) >> 7;
240 void r300_emit_fragment_program_code(struct r300_context
* r300
,
241 struct rX00_fragment_program_code
* generic_code
)
243 struct r300_fragment_program_code
* code
= &generic_code
->code
.r300
;
248 code
->alu
.length
* 4 +
249 (code
->tex
.length
? (1 + code
->tex
.length
) : 0));
251 OUT_CS_REG(R300_US_CONFIG
, code
->config
);
252 OUT_CS_REG(R300_US_PIXSIZE
, code
->pixsize
);
253 OUT_CS_REG(R300_US_CODE_OFFSET
, code
->code_offset
);
255 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0
, 4);
256 for(i
= 0; i
< 4; ++i
)
257 OUT_CS(code
->code_addr
[i
]);
259 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0
, code
->alu
.length
);
260 for (i
= 0; i
< code
->alu
.length
; i
++)
261 OUT_CS(code
->alu
.inst
[i
].rgb_inst
);
263 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0
, code
->alu
.length
);
264 for (i
= 0; i
< code
->alu
.length
; i
++)
265 OUT_CS(code
->alu
.inst
[i
].rgb_addr
);
267 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0
, code
->alu
.length
);
268 for (i
= 0; i
< code
->alu
.length
; i
++)
269 OUT_CS(code
->alu
.inst
[i
].alpha_inst
);
271 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0
, code
->alu
.length
);
272 for (i
= 0; i
< code
->alu
.length
; i
++)
273 OUT_CS(code
->alu
.inst
[i
].alpha_addr
);
275 if (code
->tex
.length
) {
276 OUT_CS_REG_SEQ(R300_US_TEX_INST_0
, code
->tex
.length
);
277 for(i
= 0; i
< code
->tex
.length
; ++i
)
278 OUT_CS(code
->tex
.inst
[i
]);
284 void r300_emit_fs_constant_buffer(struct r300_context
* r300
,
285 struct rc_constant_list
* constants
)
290 if (constants
->Count
== 0)
293 BEGIN_CS(constants
->Count
* 4 + 1);
294 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, constants
->Count
* 4);
295 for(i
= 0; i
< constants
->Count
; ++i
) {
296 const float * data
= get_shader_constant(r300
,
297 &constants
->Constants
[i
],
298 &r300
->shader_constants
[PIPE_SHADER_FRAGMENT
]);
299 OUT_CS(pack_float24(data
[0]));
300 OUT_CS(pack_float24(data
[1]));
301 OUT_CS(pack_float24(data
[2]));
302 OUT_CS(pack_float24(data
[3]));
307 static void r300_emit_fragment_depth_config(struct r300_context
* r300
,
308 struct r300_fragment_shader
* fs
)
313 if (r300_fragment_shader_writes_depth(fs
)) {
314 OUT_CS_REG(R300_FG_DEPTH_SRC
, R300_FG_DEPTH_SRC_SHADER
);
315 OUT_CS_REG(R300_US_W_FMT
, R300_W_FMT_W24
| R300_W_SRC_US
);
317 OUT_CS_REG(R300_FG_DEPTH_SRC
, R300_FG_DEPTH_SRC_SCAN
);
318 OUT_CS_REG(R300_US_W_FMT
, R300_W_FMT_W0
| R300_W_SRC_US
);
323 void r500_emit_fragment_program_code(struct r300_context
* r300
,
324 struct rX00_fragment_program_code
* generic_code
)
326 struct r500_fragment_program_code
* code
= &generic_code
->code
.r500
;
331 ((code
->inst_end
+ 1) * 6));
332 OUT_CS_REG(R500_US_CONFIG
, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO
);
333 OUT_CS_REG(R500_US_PIXSIZE
, code
->max_temp_idx
);
334 OUT_CS_REG(R500_US_CODE_RANGE
,
335 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code
->inst_end
));
336 OUT_CS_REG(R500_US_CODE_OFFSET
, 0);
337 OUT_CS_REG(R500_US_CODE_ADDR
,
338 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code
->inst_end
));
340 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_INSTR
);
341 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, (code
->inst_end
+ 1) * 6);
342 for (i
= 0; i
<= code
->inst_end
; i
++) {
343 OUT_CS(code
->inst
[i
].inst0
);
344 OUT_CS(code
->inst
[i
].inst1
);
345 OUT_CS(code
->inst
[i
].inst2
);
346 OUT_CS(code
->inst
[i
].inst3
);
347 OUT_CS(code
->inst
[i
].inst4
);
348 OUT_CS(code
->inst
[i
].inst5
);
354 void r500_emit_fs_constant_buffer(struct r300_context
* r300
,
355 struct rc_constant_list
* constants
)
360 if (constants
->Count
== 0)
363 BEGIN_CS(constants
->Count
* 4 + 3);
364 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
365 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, constants
->Count
* 4);
366 for (i
= 0; i
< constants
->Count
; i
++) {
367 const float * data
= get_shader_constant(r300
,
368 &constants
->Constants
[i
],
369 &r300
->shader_constants
[PIPE_SHADER_FRAGMENT
]);
378 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
380 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
381 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
382 struct r300_texture
* tex
;
383 struct pipe_surface
* surf
;
389 /* Flush and free renderbuffer caches. */
390 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT
,
391 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS
|
392 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
393 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
,
394 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
395 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);
397 /* Set the number of colorbuffers. */
398 if (fb
->nr_cbufs
> 1) {
399 if (r300screen
->caps
->is_r500
) {
400 OUT_CS_REG(R300_RB3D_CCTL
,
401 R300_RB3D_CCTL_NUM_MULTIWRITES(fb
->nr_cbufs
) |
402 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
);
404 OUT_CS_REG(R300_RB3D_CCTL
,
405 R300_RB3D_CCTL_NUM_MULTIWRITES(fb
->nr_cbufs
));
408 OUT_CS_REG(R300_RB3D_CCTL
, 0x0);
411 /* Set up colorbuffers. */
412 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
414 tex
= (struct r300_texture
*)surf
->texture
;
415 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
417 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
+ (4 * i
), 1);
418 OUT_CS_RELOC(tex
->buffer
, surf
->offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
420 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0
+ (4 * i
), 1);
421 OUT_CS_RELOC(tex
->buffer
, tex
->fb_state
.colorpitch
[surf
->level
],
422 0, RADEON_GEM_DOMAIN_VRAM
, 0);
424 OUT_CS_REG(R300_US_OUT_FMT_0
+ (4 * i
), tex
->fb_state
.us_out_fmt
);
427 OUT_CS_REG(R300_US_OUT_FMT_0
+ (4 * i
), R300_US_OUT_FMT_UNUSED
);
430 /* Set up a zbuffer. */
433 tex
= (struct r300_texture
*)surf
->texture
;
434 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
436 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
437 OUT_CS_RELOC(tex
->buffer
, surf
->offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
439 OUT_CS_REG(R300_ZB_FORMAT
, tex
->fb_state
.zb_format
);
441 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
442 OUT_CS_RELOC(tex
->buffer
, tex
->fb_state
.depthpitch
[surf
->level
],
443 0, RADEON_GEM_DOMAIN_VRAM
, 0);
446 OUT_CS_REG(R300_GA_POINT_MINMAX
,
447 (MAX2(fb
->width
, fb
->height
) * 6) << R300_GA_POINT_MINMAX_MAX_SHIFT
);
451 static void r300_emit_query_start(struct r300_context
*r300
)
453 struct r300_capabilities
*caps
= r300_screen(r300
->context
.screen
)->caps
;
454 struct r300_query
*query
= r300
->query_current
;
461 if (caps
->family
== CHIP_FAMILY_RV530
) {
462 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
464 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
466 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
468 query
->begin_emitted
= TRUE
;
472 static void r300_emit_query_finish(struct r300_context
*r300
,
473 struct r300_query
*query
)
475 struct r300_capabilities
* caps
= r300_screen(r300
->context
.screen
)->caps
;
478 assert(caps
->num_frag_pipes
);
480 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
481 /* I'm not so sure I like this switch, but it's hard to be elegant
482 * when there's so many special cases...
484 * So here's the basic idea. For each pipe, enable writes to it only,
485 * then put out the relocation for ZPASS_ADDR, taking into account a
486 * 4-byte offset for each pipe. RV380 and older are special; they have
487 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
488 * so there's a chipset cap for that. */
489 switch (caps
->num_frag_pipes
) {
492 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
493 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
494 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 3),
495 0, RADEON_GEM_DOMAIN_GTT
, 0);
498 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
499 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
500 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 2),
501 0, RADEON_GEM_DOMAIN_GTT
, 0);
504 /* As mentioned above, accomodate RV380 and older. */
505 OUT_CS_REG(R300_SU_REG_DEST
,
506 1 << (caps
->high_second_pipe
? 3 : 1));
507 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
508 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 1),
509 0, RADEON_GEM_DOMAIN_GTT
, 0);
512 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
513 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
514 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 0),
515 0, RADEON_GEM_DOMAIN_GTT
, 0);
518 debug_printf("r300: Implementation error: Chipset reports %d"
519 " pixel pipes!\n", caps
->num_frag_pipes
);
523 /* And, finally, reset it to normal... */
524 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
528 static void rv530_emit_query_single(struct r300_context
*r300
,
529 struct r300_query
*query
)
534 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
535 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
536 OUT_CS_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
537 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
541 static void rv530_emit_query_double(struct r300_context
*r300
,
542 struct r300_query
*query
)
547 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
548 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
549 OUT_CS_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
550 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
551 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
552 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
553 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
557 void r300_emit_query_end(struct r300_context
* r300
)
559 struct r300_capabilities
*caps
= r300_screen(r300
->context
.screen
)->caps
;
560 struct r300_query
*query
= r300
->query_current
;
565 if (query
->begin_emitted
== FALSE
)
568 if (caps
->family
== CHIP_FAMILY_RV530
) {
569 if (caps
->num_z_pipes
== 2)
570 rv530_emit_query_double(r300
, query
);
572 rv530_emit_query_single(r300
, query
);
574 r300_emit_query_finish(r300
, query
);
577 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
579 struct r300_rs_state
* rs
= (struct r300_rs_state
*)state
;
584 OUT_CS_REG(R300_VAP_CNTL_STATUS
, rs
->vap_control_status
);
586 OUT_CS_REG(R300_GB_AA_CONFIG
, rs
->antialiasing_config
);
588 OUT_CS_REG(R300_GA_POINT_SIZE
, rs
->point_size
);
589 OUT_CS_REG(R300_GA_LINE_CNTL
, rs
->line_control
);
591 if (rs
->polygon_offset_enable
) {
592 scale
= rs
->depth_scale
* 12;
593 offset
= rs
->depth_offset
;
595 switch (r300
->zbuffer_bpp
) {
604 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
611 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE
, 2);
612 OUT_CS(rs
->polygon_offset_enable
);
613 OUT_CS(rs
->cull_mode
);
614 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG
, rs
->line_stipple_config
);
615 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE
, rs
->line_stipple_value
);
616 OUT_CS_REG(R300_GA_POLY_MODE
, rs
->polygon_mode
);
620 void r300_emit_rs_block_state(struct r300_context
* r300
,
621 unsigned size
, void* state
)
623 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
625 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
626 /* It's the same for both INST and IP tables */
627 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
630 DBG(r300
, DBG_DRAW
, "r300: RS emit:\n");
633 if (r300screen
->caps
->is_r500
) {
634 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
636 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
638 for (i
= 0; i
< count
; i
++) {
640 DBG(r300
, DBG_DRAW
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
643 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
645 OUT_CS(rs
->inst_count
);
647 if (r300screen
->caps
->is_r500
) {
648 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
650 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
652 for (i
= 0; i
< count
; i
++) {
654 DBG(r300
, DBG_DRAW
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
657 DBG(r300
, DBG_DRAW
, " : count: 0x%08x inst_count: 0x%08x\n",
658 rs
->count
, rs
->inst_count
);
663 void r300_emit_scissor_state(struct r300_context
* r300
,
664 unsigned size
, void* state
)
666 unsigned minx
, miny
, maxx
, maxy
;
667 uint32_t top_left
, bottom_right
;
668 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
669 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
670 struct pipe_framebuffer_state
* fb
=
671 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
678 if (((struct r300_rs_state
*)r300
->rs_state
.state
)->rs
.scissor
) {
679 minx
= MAX2(minx
, scissor
->minx
);
680 miny
= MAX2(miny
, scissor
->miny
);
681 maxx
= MIN2(maxx
, scissor
->maxx
);
682 maxy
= MIN2(maxy
, scissor
->maxy
);
685 /* Special case for zero-area scissor.
687 * We can't allow the variables maxx and maxy to be zero because they are
688 * subtracted from later in the code, which would cause emitting ~0 and
689 * making the kernel checker angry.
691 * Let's consider we change maxx and maxy to 1, which is effectively
692 * a one-pixel area. We must then change minx and miny to a number which is
693 * greater than 1 to get the zero area back. */
694 if (!maxx
|| !maxy
) {
701 if (r300screen
->caps
->is_r500
) {
703 (minx
<< R300_SCISSORS_X_SHIFT
) |
704 (miny
<< R300_SCISSORS_Y_SHIFT
);
706 ((maxx
- 1) << R300_SCISSORS_X_SHIFT
) |
707 ((maxy
- 1) << R300_SCISSORS_Y_SHIFT
);
709 /* Offset of 1440 in non-R500 chipsets. */
711 ((minx
+ 1440) << R300_SCISSORS_X_SHIFT
) |
712 ((miny
+ 1440) << R300_SCISSORS_Y_SHIFT
);
714 (((maxx
- 1) + 1440) << R300_SCISSORS_X_SHIFT
) |
715 (((maxy
- 1) + 1440) << R300_SCISSORS_Y_SHIFT
);
719 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
721 OUT_CS(bottom_right
);
725 void r300_emit_textures_state(struct r300_context
*r300
,
726 unsigned size
, void *state
)
728 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
729 struct r300_texture_sampler_state
*texstate
;
734 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
736 for (i
= 0; i
< allstate
->count
; i
++) {
737 if ((1 << i
) & allstate
->tx_enable
) {
738 texstate
= &allstate
->regs
[i
];
740 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter
[0]);
741 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter
[1]);
742 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
743 texstate
->border_color
);
745 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
[0]);
746 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
[1]);
747 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
[2]);
749 OUT_CS_REG_SEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
750 OUT_CS_RELOC(allstate
->textures
[i
]->buffer
, texstate
->tile_config
,
751 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0, 0);
757 void r300_emit_aos(struct r300_context
* r300
, unsigned offset
)
759 struct pipe_vertex_buffer
*vb1
, *vb2
, *vbuf
= r300
->vertex_buffer
;
760 struct pipe_vertex_element
*velem
= r300
->vertex_element
;
762 unsigned size1
, size2
, aos_count
= r300
->vertex_element_count
;
763 unsigned packet_size
= (aos_count
* 3 + 1) / 2;
766 BEGIN_CS(2 + packet_size
+ aos_count
* 2);
767 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
770 for (i
= 0; i
< aos_count
- 1; i
+= 2) {
771 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
772 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
773 size1
= util_format_get_blocksize(velem
[i
].src_format
);
774 size2
= util_format_get_blocksize(velem
[i
+1].src_format
);
776 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
777 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
778 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
779 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
783 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
784 size1
= util_format_get_blocksize(velem
[i
].src_format
);
786 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
787 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
790 for (i
= 0; i
< aos_count
; i
++) {
791 OUT_CS_RELOC_NO_OFFSET(vbuf
[velem
[i
].vertex_buffer_index
].buffer
,
792 RADEON_GEM_DOMAIN_GTT
, 0, 0);
797 void r300_emit_vertex_buffer(struct r300_context
* r300
)
801 DBG(r300
, DBG_DRAW
, "r300: Preparing vertex buffer %p for render, "
802 "vertex size %d\n", r300
->vbo
,
803 r300
->vertex_info
.size
);
804 /* Set the pointer to our vertex buffer. The emitted values are this:
805 * PACKET3 [3D_LOAD_VBPNTR]
807 * FORMAT [size | stride << 8]
808 * OFFSET [offset into BO]
809 * VBPNTR [relocated BO]
812 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
814 OUT_CS(r300
->vertex_info
.size
|
815 (r300
->vertex_info
.size
<< 8));
816 OUT_CS(r300
->vbo_offset
);
817 OUT_CS_RELOC(r300
->vbo
, 0, RADEON_GEM_DOMAIN_GTT
, 0, 0);
821 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
822 unsigned size
, void* state
)
824 struct r300_vertex_stream_state
*streams
=
825 (struct r300_vertex_stream_state
*)state
;
829 DBG(r300
, DBG_DRAW
, "r300: PSC emit:\n");
832 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
833 for (i
= 0; i
< streams
->count
; i
++) {
834 OUT_CS(streams
->vap_prog_stream_cntl
[i
]);
835 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl%d: 0x%08x\n", i
,
836 streams
->vap_prog_stream_cntl
[i
]);
838 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
839 for (i
= 0; i
< streams
->count
; i
++) {
840 OUT_CS(streams
->vap_prog_stream_cntl_ext
[i
]);
841 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
842 streams
->vap_prog_stream_cntl_ext
[i
]);
847 void r300_emit_vap_output_state(struct r300_context
* r300
,
848 unsigned size
, void* state
)
850 struct r300_vap_output_state
*vap_out_state
=
851 (struct r300_vap_output_state
*)state
;
854 DBG(r300
, DBG_DRAW
, "r300: VAP emit:\n");
857 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
858 OUT_CS(vap_out_state
->vap_vtx_state_cntl
);
859 OUT_CS(vap_out_state
->vap_vsm_vtx_assm
);
860 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
861 OUT_CS(vap_out_state
->vap_out_vtx_fmt
[0]);
862 OUT_CS(vap_out_state
->vap_out_vtx_fmt
[1]);
866 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
871 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
875 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
877 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
878 struct r300_vertex_program_code
* code
= &vs
->code
;
879 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
880 unsigned instruction_count
= code
->length
/ 4;
883 unsigned vtx_mem_size
= r300screen
->caps
->is_r500
? 128 : 72;
884 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
885 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
886 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
888 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
889 vtx_mem_size
/ output_count
, 10);
890 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 6);
894 if (!r300screen
->caps
->has_tcl
) {
895 debug_printf("r300: Implementation error: emit_vs_state called,"
896 " but has_tcl is FALSE!\n");
901 /* R300_VAP_PVS_CODE_CNTL_0
902 * R300_VAP_PVS_CONST_CNTL
903 * R300_VAP_PVS_CODE_CNTL_1
904 * See the r5xx docs for instructions on how to use these. */
905 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0
, 3);
906 OUT_CS(R300_PVS_FIRST_INST(0) |
907 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
908 R300_PVS_LAST_INST(instruction_count
- 1));
909 OUT_CS(R300_PVS_MAX_CONST_ADDR(code
->constants
.Count
- 1));
910 OUT_CS(instruction_count
- 1);
912 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
913 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
914 for (i
= 0; i
< code
->length
; i
++) {
915 OUT_CS(code
->body
.d
[i
]);
918 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
919 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
920 R300_PVS_NUM_FPUS(r300screen
->caps
->num_vert_fpus
) |
921 R300_PVS_VF_MAX_VTX_NUM(12) |
922 (r300screen
->caps
->is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
926 void r300_emit_vs_constant_buffer(struct r300_context
* r300
,
927 struct rc_constant_list
* constants
)
930 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
933 if (!r300screen
->caps
->has_tcl
) {
934 debug_printf("r300: Implementation error: emit_vs_constant_buffer called,"
935 " but has_tcl is FALSE!\n");
939 if (constants
->Count
== 0)
942 BEGIN_CS(constants
->Count
* 4 + 3);
943 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
944 (r300screen
->caps
->is_r500
?
945 R500_PVS_CONST_START
: R300_PVS_CONST_START
));
946 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, constants
->Count
* 4);
947 for (i
= 0; i
< constants
->Count
; i
++) {
948 const float * data
= get_shader_constant(r300
,
949 &constants
->Constants
[i
],
950 &r300
->shader_constants
[PIPE_SHADER_VERTEX
]);
959 void r300_emit_viewport_state(struct r300_context
* r300
,
960 unsigned size
, void* state
)
962 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
966 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
967 OUT_CS_32F(viewport
->xscale
);
968 OUT_CS_32F(viewport
->xoffset
);
969 OUT_CS_32F(viewport
->yscale
);
970 OUT_CS_32F(viewport
->yoffset
);
971 OUT_CS_32F(viewport
->zscale
);
972 OUT_CS_32F(viewport
->zoffset
);
973 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
977 void r300_emit_ztop_state(struct r300_context
* r300
,
978 unsigned size
, void* state
)
980 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
984 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
988 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
993 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
997 void r300_emit_buffer_validate(struct r300_context
*r300
,
998 boolean do_validate_vertex_buffers
,
999 struct pipe_buffer
*index_buffer
)
1001 struct pipe_framebuffer_state
* fb
=
1002 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1003 struct r300_textures_state
*texstate
=
1004 (struct r300_textures_state
*)r300
->textures_state
.state
;
1005 struct r300_texture
* tex
;
1006 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
1007 struct pipe_vertex_element
*velem
= r300
->vertex_element
;
1008 struct pipe_buffer
*pbuf
;
1010 boolean invalid
= FALSE
;
1012 /* Clean out BOs. */
1013 r300
->winsys
->reset_bos(r300
->winsys
);
1016 /* Color buffers... */
1017 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1018 tex
= (struct r300_texture
*)fb
->cbufs
[i
]->texture
;
1019 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
1020 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
1021 0, RADEON_GEM_DOMAIN_VRAM
)) {
1022 r300
->context
.flush(&r300
->context
, 0, NULL
);
1026 /* ...depth buffer... */
1028 tex
= (struct r300_texture
*)fb
->zsbuf
->texture
;
1029 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
1030 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
1031 0, RADEON_GEM_DOMAIN_VRAM
)) {
1032 r300
->context
.flush(&r300
->context
, 0, NULL
);
1036 /* ...textures... */
1037 for (i
= 0; i
< texstate
->count
; i
++) {
1038 tex
= texstate
->textures
[i
];
1039 if (!tex
|| !texstate
->sampler_states
[i
])
1041 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
1042 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0)) {
1043 r300
->context
.flush(&r300
->context
, 0, NULL
);
1047 /* ...occlusion query buffer... */
1048 if (r300
->dirty_state
& R300_NEW_QUERY
) {
1049 if (!r300
->winsys
->add_buffer(r300
->winsys
, r300
->oqbo
,
1050 0, RADEON_GEM_DOMAIN_GTT
)) {
1051 r300
->context
.flush(&r300
->context
, 0, NULL
);
1055 /* ...vertex buffer for SWTCL path... */
1057 if (!r300
->winsys
->add_buffer(r300
->winsys
, r300
->vbo
,
1058 RADEON_GEM_DOMAIN_GTT
, 0)) {
1059 r300
->context
.flush(&r300
->context
, 0, NULL
);
1063 /* ...vertex buffers for HWTCL path... */
1064 if (do_validate_vertex_buffers
) {
1065 for (i
= 0; i
< r300
->vertex_element_count
; i
++) {
1066 pbuf
= vbuf
[velem
[i
].vertex_buffer_index
].buffer
;
1068 if (!r300
->winsys
->add_buffer(r300
->winsys
, pbuf
,
1069 RADEON_GEM_DOMAIN_GTT
, 0)) {
1070 r300
->context
.flush(&r300
->context
, 0, NULL
);
1075 /* ...and index buffer for HWTCL path. */
1077 if (!r300
->winsys
->add_buffer(r300
->winsys
, index_buffer
,
1078 RADEON_GEM_DOMAIN_GTT
, 0)) {
1079 r300
->context
.flush(&r300
->context
, 0, NULL
);
1084 if (!r300
->winsys
->validate(r300
->winsys
)) {
1085 r300
->context
.flush(&r300
->context
, 0, NULL
);
1088 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1096 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
1098 struct r300_atom
* atom
;
1099 unsigned dwords
= 0;
1101 foreach(atom
, &r300
->atom_list
) {
1102 if (atom
->dirty
|| atom
->always_dirty
) {
1103 dwords
+= atom
->size
;
1107 /* XXX This is the compensation for the non-atomized states. */
1113 /* Emit all dirty state. */
1114 void r300_emit_dirty_state(struct r300_context
* r300
)
1116 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
1117 struct r300_atom
* atom
;
1119 if (r300
->dirty_state
& R300_NEW_QUERY
) {
1120 r300_emit_query_start(r300
);
1121 r300
->dirty_state
&= ~R300_NEW_QUERY
;
1124 foreach(atom
, &r300
->atom_list
) {
1125 if (atom
->dirty
|| atom
->always_dirty
) {
1126 atom
->emit(r300
, atom
->size
, atom
->state
);
1127 atom
->dirty
= FALSE
;
1131 if (r300
->dirty_state
& R300_NEW_FRAGMENT_SHADER
) {
1132 r300_emit_fragment_depth_config(r300
, r300
->fs
);
1133 if (r300screen
->caps
->is_r500
) {
1134 r500_emit_fragment_program_code(r300
, &r300
->fs
->shader
->code
);
1136 r300_emit_fragment_program_code(r300
, &r300
->fs
->shader
->code
);
1138 r300
->dirty_state
&= ~R300_NEW_FRAGMENT_SHADER
;
1141 if (r300
->dirty_state
& R300_NEW_FRAGMENT_SHADER_CONSTANTS
) {
1142 if (r300screen
->caps
->is_r500
) {
1143 r500_emit_fs_constant_buffer(r300
,
1144 &r300
->fs
->shader
->code
.constants
);
1146 r300_emit_fs_constant_buffer(r300
,
1147 &r300
->fs
->shader
->code
.constants
);
1149 r300
->dirty_state
&= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS
;
1152 if (r300
->dirty_state
& R300_NEW_VERTEX_SHADER_CONSTANTS
) {
1153 struct r300_vertex_shader
* vs
= r300
->vs_state
.state
;
1154 r300_emit_vs_constant_buffer(r300
, &vs
->code
.constants
);
1155 r300
->dirty_state
&= ~R300_NEW_VERTEX_SHADER_CONSTANTS
;
1159 assert(r300->dirty_state == 0);
1162 /* Emit the VBO for SWTCL. */
1163 if (!r300screen
->caps
->has_tcl
) {
1164 r300_emit_vertex_buffer(r300
);