2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
30 #include "r300_context.h"
33 #include "r300_emit.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
39 void r300_emit_blend_state(struct r300_context
* r300
,
40 unsigned size
, void* state
)
42 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
43 struct pipe_framebuffer_state
* fb
=
44 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
48 if (fb
->cbufs
[0]->format
== PIPE_FORMAT_R16G16B16A16_FLOAT
)
49 WRITE_CS_TABLE(blend
->cb_noclamp
, size
);
51 WRITE_CS_TABLE(blend
->cb_clamp
, size
);
53 WRITE_CS_TABLE(blend
->cb_no_readwrite
, size
);
57 void r300_emit_blend_color_state(struct r300_context
* r300
,
58 unsigned size
, void* state
)
60 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
63 WRITE_CS_TABLE(bc
->cb
, size
);
66 void r300_emit_clip_state(struct r300_context
* r300
,
67 unsigned size
, void* state
)
69 struct r300_clip_state
* clip
= (struct r300_clip_state
*)state
;
72 WRITE_CS_TABLE(clip
->cb
, size
);
75 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
77 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
78 struct pipe_framebuffer_state
* fb
=
79 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
83 if (fb
->nr_cbufs
&& fb
->cbufs
[0]->format
== PIPE_FORMAT_R16G16B16A16_FLOAT
)
84 WRITE_CS_TABLE(&dsa
->cb_begin_fp16
, size
);
86 WRITE_CS_TABLE(&dsa
->cb_begin
, size
);
88 if (fb
->nr_cbufs
&& fb
->cbufs
[0]->format
== PIPE_FORMAT_R16G16B16A16_FLOAT
)
89 WRITE_CS_TABLE(dsa
->cb_fp16_zb_no_readwrite
, size
);
91 WRITE_CS_TABLE(dsa
->cb_zb_no_readwrite
, size
);
95 static void get_rc_constant_state(
97 struct r300_context
* r300
,
98 struct rc_constant
* constant
)
100 struct r300_textures_state
* texstate
= r300
->textures_state
.state
;
101 struct r300_resource
*tex
;
103 assert(constant
->Type
== RC_CONSTANT_STATE
);
105 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
106 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
109 switch (constant
->u
.State
[0]) {
110 /* Factor for converting rectangle coords to
111 * normalized coords. Should only show up on non-r500. */
112 case RC_STATE_R300_TEXRECT_FACTOR
:
113 tex
= r300_resource(texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
);
114 vec
[0] = 1.0 / tex
->tex
.width0
;
115 vec
[1] = 1.0 / tex
->tex
.height0
;
120 case RC_STATE_R300_TEXSCALE_FACTOR
:
121 tex
= r300_resource(texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
);
122 /* Add a small number to the texture size to work around rounding errors in hw. */
123 vec
[0] = tex
->b
.b
.b
.width0
/ (tex
->tex
.width0
+ 0.001f
);
124 vec
[1] = tex
->b
.b
.b
.height0
/ (tex
->tex
.height0
+ 0.001f
);
125 vec
[2] = tex
->b
.b
.b
.depth0
/ (tex
->tex
.depth0
+ 0.001f
);
129 case RC_STATE_R300_VIEWPORT_SCALE
:
130 vec
[0] = r300
->viewport
.scale
[0];
131 vec
[1] = r300
->viewport
.scale
[1];
132 vec
[2] = r300
->viewport
.scale
[2];
136 case RC_STATE_R300_VIEWPORT_OFFSET
:
137 vec
[0] = r300
->viewport
.translate
[0];
138 vec
[1] = r300
->viewport
.translate
[1];
139 vec
[2] = r300
->viewport
.translate
[2];
144 fprintf(stderr
, "r300: Implementation error: "
145 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
153 /* Convert a normal single-precision float into the 7.16 format
154 * used by the R300 fragment shader.
156 uint32_t pack_float24(float f
)
164 uint32_t float24
= 0;
171 mantissa
= frexpf(f
, &exponent
);
175 float24
|= (1 << 23);
176 mantissa
= mantissa
* -1.0;
178 /* Handle exponent, bias of 63 */
180 float24
|= (exponent
<< 16);
181 /* Kill 7 LSB of mantissa */
182 float24
|= (u
.u
& 0x7FFFFF) >> 7;
187 void r300_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
189 struct r300_fragment_shader
*fs
= r300_fs(r300
);
192 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
195 void r300_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
197 struct r300_fragment_shader
*fs
= r300_fs(r300
);
198 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
199 unsigned count
= fs
->shader
->externals_count
;
207 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, count
* 4);
208 if (buf
->remap_table
){
209 for (i
= 0; i
< count
; i
++) {
210 float *data
= (float*)&buf
->ptr
[buf
->remap_table
[i
]*4];
211 for (j
= 0; j
< 4; j
++)
212 OUT_CS(pack_float24(data
[j
]));
215 for (i
= 0; i
< count
; i
++)
216 for (j
= 0; j
< 4; j
++)
217 OUT_CS(pack_float24(*(float*)&buf
->ptr
[i
*4+j
]));
223 void r300_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
225 struct r300_fragment_shader
*fs
= r300_fs(r300
);
226 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
228 unsigned count
= fs
->shader
->rc_state_count
;
229 unsigned first
= fs
->shader
->externals_count
;
230 unsigned end
= constants
->Count
;
238 for(i
= first
; i
< end
; ++i
) {
239 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
242 get_rc_constant_state(data
, r300
, &constants
->Constants
[i
]);
244 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
245 for (j
= 0; j
< 4; j
++)
246 OUT_CS(pack_float24(data
[j
]));
252 void r500_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
254 struct r300_fragment_shader
*fs
= r300_fs(r300
);
257 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
260 void r500_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
262 struct r300_fragment_shader
*fs
= r300_fs(r300
);
263 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
264 unsigned count
= fs
->shader
->externals_count
;
271 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
272 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, count
* 4);
273 if (buf
->remap_table
){
274 for (unsigned i
= 0; i
< count
; i
++) {
275 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
276 OUT_CS_TABLE(data
, 4);
279 OUT_CS_TABLE(buf
->ptr
, count
* 4);
284 void r500_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
286 struct r300_fragment_shader
*fs
= r300_fs(r300
);
287 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
289 unsigned count
= fs
->shader
->rc_state_count
;
290 unsigned first
= fs
->shader
->externals_count
;
291 unsigned end
= constants
->Count
;
298 for(i
= first
; i
< end
; ++i
) {
299 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
302 get_rc_constant_state(data
, r300
, &constants
->Constants
[i
]);
304 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
305 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
306 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
307 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
308 OUT_CS_TABLE(data
, 4);
314 void r300_emit_gpu_flush(struct r300_context
*r300
, unsigned size
, void *state
)
316 struct r300_gpu_flush
*gpuflush
= (struct r300_gpu_flush
*)state
;
317 struct pipe_framebuffer_state
* fb
=
318 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
319 uint32_t height
= fb
->height
;
320 uint32_t width
= fb
->width
;
323 if (r300
->cbzb_clear
) {
324 struct r300_surface
*surf
= r300_surface(fb
->cbufs
[0]);
326 height
= surf
->cbzb_height
;
327 width
= surf
->cbzb_width
;
330 DBG(r300
, DBG_SCISSOR
,
331 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
332 width
, height
, r300
->cbzb_clear
? "YES" : "NO");
337 * By writing to the SC registers, SC & US assert idle. */
338 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
339 if (r300
->screen
->caps
.is_r500
) {
341 OUT_CS(((width
- 1) << R300_SCISSORS_X_SHIFT
) |
342 ((height
- 1) << R300_SCISSORS_Y_SHIFT
));
344 OUT_CS((1440 << R300_SCISSORS_X_SHIFT
) |
345 (1440 << R300_SCISSORS_Y_SHIFT
));
346 OUT_CS(((width
+ 1440-1) << R300_SCISSORS_X_SHIFT
) |
347 ((height
+ 1440-1) << R300_SCISSORS_Y_SHIFT
));
350 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
351 OUT_CS_TABLE(gpuflush
->cb_flush_clean
, 6);
355 void r300_emit_aa_state(struct r300_context
*r300
, unsigned size
, void *state
)
357 struct r300_aa_state
*aa
= (struct r300_aa_state
*)state
;
361 OUT_CS_REG(R300_GB_AA_CONFIG
, aa
->aa_config
);
364 OUT_CS_REG(R300_RB3D_AARESOLVE_OFFSET
, aa
->dest
->offset
);
365 OUT_CS_RELOC(aa
->dest
);
366 OUT_CS_REG(R300_RB3D_AARESOLVE_PITCH
, aa
->dest
->pitch
);
369 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL
, aa
->aaresolve_ctl
);
373 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
375 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
376 struct r300_surface
* surf
;
378 boolean can_hyperz
= r300
->rws
->get_value(r300
->rws
, R300_CAN_HYPERZ
);
379 uint32_t rb3d_cctl
= 0;
385 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
386 * what we usually want. */
387 if (r300
->screen
->caps
.is_r500
) {
388 rb3d_cctl
= R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
;
390 if (fb
->nr_cbufs
&& r300
->fb_multiwrite
) {
391 rb3d_cctl
|= R300_RB3D_CCTL_NUM_MULTIWRITES(fb
->nr_cbufs
);
394 OUT_CS_REG(R300_RB3D_CCTL
, rb3d_cctl
);
396 /* Set up colorbuffers. */
397 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
398 surf
= r300_surface(fb
->cbufs
[i
]);
400 OUT_CS_REG(R300_RB3D_COLOROFFSET0
+ (4 * i
), surf
->offset
);
403 OUT_CS_REG(R300_RB3D_COLORPITCH0
+ (4 * i
), surf
->pitch
);
407 /* Set up the ZB part of the CBZB clear. */
408 if (r300
->cbzb_clear
) {
409 surf
= r300_surface(fb
->cbufs
[0]);
411 OUT_CS_REG(R300_ZB_FORMAT
, surf
->cbzb_format
);
413 OUT_CS_REG(R300_ZB_DEPTHOFFSET
, surf
->cbzb_midpoint_offset
);
416 OUT_CS_REG(R300_ZB_DEPTHPITCH
, surf
->cbzb_pitch
);
420 "CBZB clearing cbuf %08x %08x\n", surf
->cbzb_format
,
423 /* Set up a zbuffer. */
424 else if (fb
->zsbuf
) {
425 surf
= r300_surface(fb
->zsbuf
);
427 OUT_CS_REG(R300_ZB_FORMAT
, surf
->format
);
429 OUT_CS_REG(R300_ZB_DEPTHOFFSET
, surf
->offset
);
432 OUT_CS_REG(R300_ZB_DEPTHPITCH
, surf
->pitch
);
437 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, 0);
438 OUT_CS_REG(R300_ZB_HIZ_PITCH
, surf
->pitch_hiz
);
439 /* Z Mask RAM. (compressed zbuffer) */
440 OUT_CS_REG(R300_ZB_ZMASK_OFFSET
, 0);
441 OUT_CS_REG(R300_ZB_ZMASK_PITCH
, surf
->pitch_zmask
);
448 void r300_emit_hyperz_state(struct r300_context
*r300
,
449 unsigned size
, void *state
)
451 struct r300_hyperz_state
*z
= state
;
455 WRITE_CS_TABLE(&z
->cb_flush_begin
, size
);
457 WRITE_CS_TABLE(&z
->cb_begin
, size
- 2);
460 void r300_emit_hyperz_end(struct r300_context
*r300
)
462 struct r300_hyperz_state z
=
463 *(struct r300_hyperz_state
*)r300
->hyperz_state
.state
;
467 z
.zb_depthclearvalue
= 0;
468 z
.sc_hyperz
= R300_SC_HYPERZ_ADJ_2
;
469 z
.gb_z_peq_config
= 0;
471 r300_emit_hyperz_state(r300
, r300
->hyperz_state
.size
, &z
);
474 void r300_emit_fb_state_pipelined(struct r300_context
*r300
,
475 unsigned size
, void *state
)
477 struct pipe_framebuffer_state
* fb
=
478 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
479 unsigned i
, num_cbufs
= fb
->nr_cbufs
;
480 unsigned mspos0
, mspos1
;
483 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be
484 * marked as UNUSED in the US block. */
485 if (r300
->fb_multiwrite
) {
486 num_cbufs
= MIN2(num_cbufs
, 1);
491 /* Colorbuffer format in the US block.
492 * (must be written after unpipelined regs) */
493 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0
, 4);
494 for (i
= 0; i
< num_cbufs
; i
++) {
495 OUT_CS(r300_surface(fb
->cbufs
[i
])->format
);
498 OUT_CS(R300_US_OUT_FMT_C4_8
|
499 R300_C0_SEL_B
| R300_C1_SEL_G
|
500 R300_C2_SEL_R
| R300_C3_SEL_A
);
503 OUT_CS(R300_US_OUT_FMT_UNUSED
);
506 /* Multisampling. Depends on framebuffer sample count.
507 * These are pipelined regs and as such cannot be moved
508 * to the AA state. */
512 if (fb
->nr_cbufs
&& fb
->cbufs
[0]->texture
->nr_samples
> 1) {
513 /* Subsample placement. These may not be optimal. */
514 switch (fb
->cbufs
[0]->texture
->nr_samples
) {
532 debug_printf("r300: Bad number of multisamples!\n");
536 OUT_CS_REG_SEQ(R300_GB_MSPOS0
, 2);
542 void r300_emit_query_start(struct r300_context
*r300
, unsigned size
, void*state
)
544 struct r300_query
*query
= r300
->query_current
;
551 if (r300
->screen
->caps
.family
== CHIP_FAMILY_RV530
) {
552 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
554 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
556 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
558 query
->begin_emitted
= TRUE
;
561 static void r300_emit_query_end_frag_pipes(struct r300_context
*r300
,
562 struct r300_query
*query
)
564 struct r300_capabilities
* caps
= &r300
->screen
->caps
;
567 assert(caps
->num_frag_pipes
);
569 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
570 /* I'm not so sure I like this switch, but it's hard to be elegant
571 * when there's so many special cases...
573 * So here's the basic idea. For each pipe, enable writes to it only,
574 * then put out the relocation for ZPASS_ADDR, taking into account a
575 * 4-byte offset for each pipe. RV380 and older are special; they have
576 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
577 * so there's a chipset cap for that. */
578 switch (caps
->num_frag_pipes
) {
581 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
582 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 3) * 4);
583 OUT_CS_RELOC(r300
->query_current
);
586 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
587 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 2) * 4);
588 OUT_CS_RELOC(r300
->query_current
);
591 /* As mentioned above, accomodate RV380 and older. */
592 OUT_CS_REG(R300_SU_REG_DEST
,
593 1 << (caps
->high_second_pipe
? 3 : 1));
594 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 1) * 4);
595 OUT_CS_RELOC(r300
->query_current
);
598 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
599 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 0) * 4);
600 OUT_CS_RELOC(r300
->query_current
);
603 fprintf(stderr
, "r300: Implementation error: Chipset reports %d"
604 " pixel pipes!\n", caps
->num_frag_pipes
);
608 /* And, finally, reset it to normal... */
609 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
613 static void rv530_emit_query_end_single_z(struct r300_context
*r300
,
614 struct r300_query
*query
)
619 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
620 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, query
->num_results
* 4);
621 OUT_CS_RELOC(r300
->query_current
);
622 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
626 static void rv530_emit_query_end_double_z(struct r300_context
*r300
,
627 struct r300_query
*query
)
632 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
633 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 0) * 4);
634 OUT_CS_RELOC(r300
->query_current
);
635 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
636 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 1) * 4);
637 OUT_CS_RELOC(r300
->query_current
);
638 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
642 void r300_emit_query_end(struct r300_context
* r300
)
644 struct r300_capabilities
*caps
= &r300
->screen
->caps
;
645 struct r300_query
*query
= r300
->query_current
;
650 if (query
->begin_emitted
== FALSE
)
653 if (caps
->family
== CHIP_FAMILY_RV530
) {
654 if (caps
->num_z_pipes
== 2)
655 rv530_emit_query_end_double_z(r300
, query
);
657 rv530_emit_query_end_single_z(r300
, query
);
659 r300_emit_query_end_frag_pipes(r300
, query
);
661 query
->begin_emitted
= FALSE
;
662 query
->num_results
+= query
->num_pipes
;
664 /* XXX grab all the results and reset the counter. */
665 if (query
->num_results
>= query
->buffer_size
/ 4 - 4) {
666 query
->num_results
= (query
->buffer_size
/ 4) / 2;
667 fprintf(stderr
, "r300: Rewinding OQBO...\n");
671 void r300_emit_invariant_state(struct r300_context
*r300
,
672 unsigned size
, void *state
)
675 WRITE_CS_TABLE(state
, size
);
678 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
680 struct r300_rs_state
* rs
= state
;
684 OUT_CS_TABLE(rs
->cb_main
, RS_STATE_MAIN_SIZE
);
685 if (rs
->polygon_offset_enable
) {
686 if (r300
->zbuffer_bpp
== 16) {
687 OUT_CS_TABLE(rs
->cb_poly_offset_zb16
, 5);
689 OUT_CS_TABLE(rs
->cb_poly_offset_zb24
, 5);
695 void r300_emit_rs_block_state(struct r300_context
* r300
,
696 unsigned size
, void* state
)
698 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
700 /* It's the same for both INST and IP tables */
701 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
704 if (DBG_ON(r300
, DBG_RS_BLOCK
)) {
705 r500_dump_rs_block(rs
);
707 fprintf(stderr
, "r300: RS emit:\n");
709 for (i
= 0; i
< count
; i
++)
710 fprintf(stderr
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
712 for (i
= 0; i
< count
; i
++)
713 fprintf(stderr
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
715 fprintf(stderr
, " : count: 0x%08x inst_count: 0x%08x\n",
716 rs
->count
, rs
->inst_count
);
720 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
721 OUT_CS(rs
->vap_vtx_state_cntl
);
722 OUT_CS(rs
->vap_vsm_vtx_assm
);
723 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
724 OUT_CS(rs
->vap_out_vtx_fmt
[0]);
725 OUT_CS(rs
->vap_out_vtx_fmt
[1]);
726 OUT_CS_REG_SEQ(R300_GB_ENABLE
, 1);
727 OUT_CS(rs
->gb_enable
);
729 if (r300
->screen
->caps
.is_r500
) {
730 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
732 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
734 OUT_CS_TABLE(rs
->ip
, count
);
736 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
738 OUT_CS(rs
->inst_count
);
740 if (r300
->screen
->caps
.is_r500
) {
741 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
743 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
745 OUT_CS_TABLE(rs
->inst
, count
);
749 void r300_emit_scissor_state(struct r300_context
* r300
,
750 unsigned size
, void* state
)
752 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
756 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0
, 2);
757 if (r300
->screen
->caps
.is_r500
) {
758 OUT_CS((scissor
->minx
<< R300_CLIPRECT_X_SHIFT
) |
759 (scissor
->miny
<< R300_CLIPRECT_Y_SHIFT
));
760 OUT_CS(((scissor
->maxx
- 1) << R300_CLIPRECT_X_SHIFT
) |
761 ((scissor
->maxy
- 1) << R300_CLIPRECT_Y_SHIFT
));
763 OUT_CS(((scissor
->minx
+ 1440) << R300_CLIPRECT_X_SHIFT
) |
764 ((scissor
->miny
+ 1440) << R300_CLIPRECT_Y_SHIFT
));
765 OUT_CS(((scissor
->maxx
+ 1440-1) << R300_CLIPRECT_X_SHIFT
) |
766 ((scissor
->maxy
+ 1440-1) << R300_CLIPRECT_Y_SHIFT
));
771 void r300_emit_textures_state(struct r300_context
*r300
,
772 unsigned size
, void *state
)
774 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
775 struct r300_texture_sampler_state
*texstate
;
776 struct r300_resource
*tex
;
778 boolean has_us_format
= r300
->screen
->caps
.has_us_format
;
782 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
784 for (i
= 0; i
< allstate
->count
; i
++) {
785 if ((1 << i
) & allstate
->tx_enable
) {
786 texstate
= &allstate
->regs
[i
];
787 tex
= r300_resource(allstate
->sampler_views
[i
]->base
.texture
);
789 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter0
);
790 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter1
);
791 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
792 texstate
->border_color
);
794 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
.format0
);
795 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
.format1
);
796 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
.format2
);
798 OUT_CS_REG(R300_TX_OFFSET_0
+ (i
* 4), texstate
->format
.tile_config
);
802 OUT_CS_REG(R500_US_FORMAT0_0
+ (i
* 4),
803 texstate
->format
.us_format0
);
810 void r300_emit_vertex_arrays(struct r300_context
* r300
, int offset
,
811 boolean indexed
, int instance_id
)
813 struct pipe_vertex_buffer
*vbuf
= r300
->vbuf_mgr
->vertex_buffer
;
814 struct pipe_resource
**valid_vbuf
= r300
->vbuf_mgr
->real_vertex_buffer
;
815 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
816 struct r300_resource
*buf
;
818 unsigned vertex_array_count
= r300
->velems
->count
;
819 unsigned packet_size
= (vertex_array_count
* 3 + 1) / 2;
820 struct pipe_vertex_buffer
*vb1
, *vb2
;
821 unsigned *hw_format_size
= r300
->velems
->format_size
;
822 unsigned size1
, size2
, offset1
, offset2
, stride1
, stride2
;
825 BEGIN_CS(2 + packet_size
+ vertex_array_count
* 2);
826 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
827 OUT_CS(vertex_array_count
| (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
829 if (instance_id
== -1) {
830 /* Non-instanced arrays. This ignores instance_divisor and instance_id. */
831 for (i
= 0; i
< vertex_array_count
- 1; i
+= 2) {
832 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
833 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
834 size1
= hw_format_size
[i
];
835 size2
= hw_format_size
[i
+1];
837 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
838 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
839 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
840 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
843 if (vertex_array_count
& 1) {
844 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
845 size1
= hw_format_size
[i
];
847 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
848 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
851 for (i
= 0; i
< vertex_array_count
; i
++) {
852 buf
= r300_resource(valid_vbuf
[velem
[i
].vertex_buffer_index
]);
856 /* Instanced arrays. */
857 for (i
= 0; i
< vertex_array_count
- 1; i
+= 2) {
858 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
859 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
860 size1
= hw_format_size
[i
];
861 size2
= hw_format_size
[i
+1];
863 if (velem
[i
].instance_divisor
) {
865 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+
866 (instance_id
/ velem
[i
].instance_divisor
) * vb1
->stride
;
868 stride1
= vb1
->stride
;
869 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
;
871 if (velem
[i
+1].instance_divisor
) {
873 offset2
= vb2
->buffer_offset
+ velem
[i
+1].src_offset
+
874 (instance_id
/ velem
[i
+1].instance_divisor
) * vb2
->stride
;
876 stride2
= vb2
->stride
;
877 offset2
= vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
;
880 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(stride1
) |
881 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(stride2
));
886 if (vertex_array_count
& 1) {
887 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
888 size1
= hw_format_size
[i
];
890 if (velem
[i
].instance_divisor
) {
892 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+
893 (instance_id
/ velem
[i
].instance_divisor
) * vb1
->stride
;
895 stride1
= vb1
->stride
;
896 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
;
899 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(stride1
));
903 for (i
= 0; i
< vertex_array_count
; i
++) {
904 buf
= r300_resource(valid_vbuf
[velem
[i
].vertex_buffer_index
]);
911 void r300_emit_vertex_arrays_swtcl(struct r300_context
*r300
, boolean indexed
)
915 DBG(r300
, DBG_SWTCL
, "r300: Preparing vertex buffer %p for render, "
916 "vertex size %d\n", r300
->vbo
,
917 r300
->vertex_info
.size
);
918 /* Set the pointer to our vertex buffer. The emitted values are this:
919 * PACKET3 [3D_LOAD_VBPNTR]
921 * FORMAT [size | stride << 8]
922 * OFFSET [offset into BO]
923 * VBPNTR [relocated BO]
926 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
927 OUT_CS(1 | (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
928 OUT_CS(r300
->vertex_info
.size
|
929 (r300
->vertex_info
.size
<< 8));
930 OUT_CS(r300
->draw_vbo_offset
);
932 OUT_CS_RELOC(r300_resource(r300
->vbo
));
936 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
937 unsigned size
, void* state
)
939 struct r300_vertex_stream_state
*streams
=
940 (struct r300_vertex_stream_state
*)state
;
944 if (DBG_ON(r300
, DBG_PSC
)) {
945 fprintf(stderr
, "r300: PSC emit:\n");
947 for (i
= 0; i
< streams
->count
; i
++) {
948 fprintf(stderr
, " : prog_stream_cntl%d: 0x%08x\n", i
,
949 streams
->vap_prog_stream_cntl
[i
]);
952 for (i
= 0; i
< streams
->count
; i
++) {
953 fprintf(stderr
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
954 streams
->vap_prog_stream_cntl_ext
[i
]);
959 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
960 OUT_CS_TABLE(streams
->vap_prog_stream_cntl
, streams
->count
);
961 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
962 OUT_CS_TABLE(streams
->vap_prog_stream_cntl_ext
, streams
->count
);
966 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
971 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
975 void r300_emit_vap_invariant_state(struct r300_context
*r300
,
976 unsigned size
, void *state
)
979 WRITE_CS_TABLE(state
, size
);
982 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
984 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
985 struct r300_vertex_program_code
* code
= &vs
->code
;
986 struct r300_screen
* r300screen
= r300
->screen
;
987 unsigned instruction_count
= code
->length
/ 4;
989 unsigned vtx_mem_size
= r300screen
->caps
.is_r500
? 128 : 72;
990 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
991 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
992 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
994 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
995 vtx_mem_size
/ output_count
, 10);
996 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 5);
1002 /* R300_VAP_PVS_CODE_CNTL_0
1003 * R300_VAP_PVS_CONST_CNTL
1004 * R300_VAP_PVS_CODE_CNTL_1
1005 * See the r5xx docs for instructions on how to use these. */
1006 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0
, R300_PVS_FIRST_INST(0) |
1007 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
1008 R300_PVS_LAST_INST(instruction_count
- 1));
1009 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1
, instruction_count
- 1);
1011 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
1012 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
1013 OUT_CS_TABLE(code
->body
.d
, code
->length
);
1015 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
1016 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
1017 R300_PVS_NUM_FPUS(r300screen
->caps
.num_vert_fpus
) |
1018 R300_PVS_VF_MAX_VTX_NUM(12) |
1019 (r300screen
->caps
.is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
1021 /* Emit flow control instructions. */
1022 if (code
->num_fc_ops
) {
1024 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC
, code
->fc_ops
);
1025 if (r300screen
->caps
.is_r500
) {
1026 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0
, code
->num_fc_ops
* 2);
1027 OUT_CS_TABLE(code
->fc_op_addrs
.r500
, code
->num_fc_ops
* 2);
1029 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0
, code
->num_fc_ops
);
1030 OUT_CS_TABLE(code
->fc_op_addrs
.r300
, code
->num_fc_ops
);
1032 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
, code
->num_fc_ops
);
1033 OUT_CS_TABLE(code
->fc_loop_index
, code
->num_fc_ops
);
1039 void r300_emit_vs_constants(struct r300_context
* r300
,
1040 unsigned size
, void *state
)
1043 ((struct r300_vertex_shader
*)r300
->vs_state
.state
)->externals_count
;
1044 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
1045 struct r300_vertex_shader
*vs
= (struct r300_vertex_shader
*)r300
->vs_state
.state
;
1047 int imm_first
= vs
->externals_count
;
1048 int imm_end
= vs
->code
.constants
.Count
;
1049 int imm_count
= vs
->immediates_count
;
1053 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL
,
1054 R300_PVS_CONST_BASE_OFFSET(buf
->buffer_base
) |
1055 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end
- 1, 0)));
1056 if (vs
->externals_count
) {
1057 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1058 (r300
->screen
->caps
.is_r500
?
1059 R500_PVS_CONST_START
: R300_PVS_CONST_START
) + buf
->buffer_base
);
1060 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, count
* 4);
1061 if (buf
->remap_table
){
1062 for (i
= 0; i
< count
; i
++) {
1063 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
1064 OUT_CS_TABLE(data
, 4);
1067 OUT_CS_TABLE(buf
->ptr
, count
* 4);
1071 /* Emit immediates. */
1073 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1074 (r300
->screen
->caps
.is_r500
?
1075 R500_PVS_CONST_START
: R300_PVS_CONST_START
) +
1076 buf
->buffer_base
+ imm_first
);
1077 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, imm_count
* 4);
1078 for (i
= imm_first
; i
< imm_end
; i
++) {
1079 const float *data
= vs
->code
.constants
.Constants
[i
].u
.Immediate
;
1080 OUT_CS_TABLE(data
, 4);
1086 void r300_emit_viewport_state(struct r300_context
* r300
,
1087 unsigned size
, void* state
)
1089 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
1093 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
1094 OUT_CS_TABLE(&viewport
->xscale
, 6);
1095 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
1099 void r300_emit_hiz_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1101 struct pipe_framebuffer_state
*fb
=
1102 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1103 struct r300_resource
* tex
;
1106 tex
= r300_resource(fb
->zsbuf
->texture
);
1109 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ
, 2);
1111 OUT_CS(tex
->tex
.hiz_dwords
[fb
->zsbuf
->u
.tex
.level
]);
1112 OUT_CS(r300
->hiz_clear_value
);
1115 /* Mark the current zbuffer's hiz ram as in use. */
1116 r300
->hiz_in_use
= TRUE
;
1117 r300
->hiz_func
= HIZ_FUNC_NONE
;
1118 r300_mark_atom_dirty(r300
, &r300
->hyperz_state
);
1121 void r300_emit_zmask_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1123 struct pipe_framebuffer_state
*fb
=
1124 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1125 struct r300_resource
*tex
;
1128 tex
= r300_resource(fb
->zsbuf
->texture
);
1131 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK
, 2);
1133 OUT_CS(tex
->tex
.zmask_dwords
[fb
->zsbuf
->u
.tex
.level
]);
1137 /* Mark the current zbuffer's zmask as in use. */
1138 r300
->zmask_in_use
= TRUE
;
1139 r300_mark_atom_dirty(r300
, &r300
->hyperz_state
);
1142 void r300_emit_ztop_state(struct r300_context
* r300
,
1143 unsigned size
, void* state
)
1145 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
1149 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
1153 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
1158 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
1162 boolean
r300_emit_buffer_validate(struct r300_context
*r300
,
1163 boolean do_validate_vertex_buffers
,
1164 struct pipe_resource
*index_buffer
)
1166 struct pipe_framebuffer_state
*fb
=
1167 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1168 struct r300_textures_state
*texstate
=
1169 (struct r300_textures_state
*)r300
->textures_state
.state
;
1170 struct r300_resource
*tex
;
1172 boolean flushed
= FALSE
;
1175 if (r300
->fb_state
.dirty
) {
1176 /* Color buffers... */
1177 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1178 tex
= r300_resource(fb
->cbufs
[i
]->texture
);
1179 assert(tex
&& tex
->buf
&& "cbuf is marked, but NULL!");
1180 r300
->rws
->cs_add_reloc(r300
->cs
, tex
->cs_buf
, 0,
1181 r300_surface(fb
->cbufs
[i
])->domain
);
1183 /* ...depth buffer... */
1185 tex
= r300_resource(fb
->zsbuf
->texture
);
1186 assert(tex
&& tex
->buf
&& "zsbuf is marked, but NULL!");
1187 r300
->rws
->cs_add_reloc(r300
->cs
, tex
->cs_buf
, 0,
1188 r300_surface(fb
->zsbuf
)->domain
);
1191 if (r300
->textures_state
.dirty
) {
1192 /* ...textures... */
1193 for (i
= 0; i
< texstate
->count
; i
++) {
1194 if (!(texstate
->tx_enable
& (1 << i
))) {
1198 tex
= r300_resource(texstate
->sampler_views
[i
]->base
.texture
);
1199 r300
->rws
->cs_add_reloc(r300
->cs
, tex
->cs_buf
, tex
->domain
, 0);
1202 /* ...occlusion query buffer... */
1203 if (r300
->query_current
)
1204 r300
->rws
->cs_add_reloc(r300
->cs
, r300
->query_current
->cs_buf
,
1205 0, r300
->query_current
->domain
);
1206 /* ...vertex buffer for SWTCL path... */
1208 r300
->rws
->cs_add_reloc(r300
->cs
, r300_resource(r300
->vbo
)->cs_buf
,
1209 r300_resource(r300
->vbo
)->domain
, 0);
1210 /* ...vertex buffers for HWTCL path... */
1211 if (do_validate_vertex_buffers
&& r300
->vertex_arrays_dirty
) {
1212 struct pipe_resource
**buf
= r300
->vbuf_mgr
->real_vertex_buffer
;
1213 struct pipe_resource
**last
= r300
->vbuf_mgr
->real_vertex_buffer
+
1214 r300
->vbuf_mgr
->nr_real_vertex_buffers
;
1215 for (; buf
!= last
; buf
++) {
1219 r300
->rws
->cs_add_reloc(r300
->cs
, r300_resource(*buf
)->cs_buf
,
1220 r300_resource(*buf
)->domain
, 0);
1223 /* ...and index buffer for HWTCL path. */
1225 r300
->rws
->cs_add_reloc(r300
->cs
, r300_resource(index_buffer
)->cs_buf
,
1226 r300_resource(index_buffer
)->domain
, 0);
1228 /* Now do the validation. */
1229 if (!r300
->rws
->cs_validate(r300
->cs
)) {
1230 /* Ooops, an infinite loop, give up. */
1234 r300_flush(&r300
->context
, R300_FLUSH_ASYNC
, NULL
);
1242 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
1244 struct r300_atom
* atom
;
1245 unsigned dwords
= 0;
1247 foreach_dirty_atom(r300
, atom
) {
1249 dwords
+= atom
->size
;
1253 /* let's reserve some more, just in case */
1259 unsigned r300_get_num_cs_end_dwords(struct r300_context
*r300
)
1261 unsigned dwords
= 0;
1263 /* Emitted in flush. */
1264 dwords
+= 26; /* emit_query_end */
1265 dwords
+= r300
->hyperz_state
.size
+ 2; /* emit_hyperz_end + zcache flush */
1266 if (r300
->screen
->caps
.is_r500
)
1272 /* Emit all dirty state. */
1273 void r300_emit_dirty_state(struct r300_context
* r300
)
1275 struct r300_atom
*atom
;
1277 foreach_dirty_atom(r300
, atom
) {
1279 atom
->emit(r300
, atom
->size
, atom
->state
);
1280 atom
->dirty
= FALSE
;
1284 r300
->first_dirty
= NULL
;
1285 r300
->last_dirty
= NULL
;