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r300g: Use table CS writing when applicable.
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300,
39 unsigned size, void* state)
40 {
41 struct r300_blend_state* blend = (struct r300_blend_state*)state;
42 struct pipe_framebuffer_state* fb =
43 (struct pipe_framebuffer_state*)r300->fb_state.state;
44 CS_LOCALS(r300);
45
46 BEGIN_CS(size);
47 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
48 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
49 if (fb->nr_cbufs) {
50 OUT_CS(blend->blend_control);
51 OUT_CS(blend->alpha_blend_control);
52 OUT_CS(blend->color_channel_mask);
53 } else {
54 OUT_CS(0);
55 OUT_CS(0);
56 OUT_CS(0);
57 /* XXX also disable fastfill here once it's supported */
58 }
59 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
60 END_CS;
61 }
62
63 void r300_emit_blend_color_state(struct r300_context* r300,
64 unsigned size, void* state)
65 {
66 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
67 CS_LOCALS(r300);
68
69 if (r300->screen->caps.is_r500) {
70 BEGIN_CS(size);
71 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
72 OUT_CS(bc->blend_color_red_alpha);
73 OUT_CS(bc->blend_color_green_blue);
74 END_CS;
75 } else {
76 BEGIN_CS(size);
77 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
78 END_CS;
79 }
80 }
81
82 void r300_emit_clip_state(struct r300_context* r300,
83 unsigned size, void* state)
84 {
85 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
86 int i;
87 CS_LOCALS(r300);
88
89 if (r300->screen->caps.has_tcl) {
90 BEGIN_CS(size);
91 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
92 (r300->screen->caps.is_r500 ?
93 R500_PVS_UCP_START : R300_PVS_UCP_START));
94 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
95 for (i = 0; i < 6; i++) {
96 OUT_CS_TABLE(clip->ucp[i], 4);
97 }
98 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
99 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
100 END_CS;
101 } else {
102 BEGIN_CS(size);
103 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
104 END_CS;
105 }
106
107 }
108
109 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
110 {
111 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
112 struct pipe_framebuffer_state* fb =
113 (struct pipe_framebuffer_state*)r300->fb_state.state;
114 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
115 CS_LOCALS(r300);
116
117 BEGIN_CS(size);
118 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
119 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
120
121 if (fb->zsbuf) {
122 OUT_CS(dsa->z_buffer_control);
123 OUT_CS(dsa->z_stencil_control);
124 } else {
125 OUT_CS(0);
126 OUT_CS(0);
127 }
128
129 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
130
131 if (r300->screen->caps.is_r500) {
132 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
133 }
134 END_CS;
135 }
136
137 static const float * get_rc_constant_state(
138 struct r300_context * r300,
139 struct rc_constant * constant)
140 {
141 struct r300_viewport_state* viewport = r300->viewport_state.state;
142 struct r300_textures_state* texstate = r300->textures_state.state;
143 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
144 struct pipe_resource *tex;
145
146 assert(constant->Type == RC_CONSTANT_STATE);
147
148 switch (constant->u.State[0]) {
149 /* Factor for converting rectangle coords to
150 * normalized coords. Should only show up on non-r500. */
151 case RC_STATE_R300_TEXRECT_FACTOR:
152 tex = texstate->sampler_views[constant->u.State[1]]->base.texture;
153 vec[0] = 1.0 / tex->width0;
154 vec[1] = 1.0 / tex->height0;
155 break;
156
157 case RC_STATE_R300_VIEWPORT_SCALE:
158 vec[0] = viewport->xscale;
159 vec[1] = viewport->yscale;
160 vec[2] = viewport->zscale;
161 break;
162
163 case RC_STATE_R300_VIEWPORT_OFFSET:
164 vec[0] = viewport->xoffset;
165 vec[1] = viewport->yoffset;
166 vec[2] = viewport->zoffset;
167 break;
168
169 default:
170 fprintf(stderr, "r300: Implementation error: "
171 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
172 }
173
174 /* This should either be (0, 0, 0, 1), which should be a relatively safe
175 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
176 * state factors. */
177 return vec;
178 }
179
180 /* Convert a normal single-precision float into the 7.16 format
181 * used by the R300 fragment shader.
182 */
183 static uint32_t pack_float24(float f)
184 {
185 union {
186 float fl;
187 uint32_t u;
188 } u;
189 float mantissa;
190 int exponent;
191 uint32_t float24 = 0;
192
193 if (f == 0.0)
194 return 0;
195
196 u.fl = f;
197
198 mantissa = frexpf(f, &exponent);
199
200 /* Handle -ve */
201 if (mantissa < 0) {
202 float24 |= (1 << 23);
203 mantissa = mantissa * -1.0;
204 }
205 /* Handle exponent, bias of 63 */
206 exponent += 62;
207 float24 |= (exponent << 16);
208 /* Kill 7 LSB of mantissa */
209 float24 |= (u.u & 0x7FFFFF) >> 7;
210
211 return float24;
212 }
213
214 unsigned r300_get_fs_atom_size(struct r300_context *r300)
215 {
216 struct r300_fragment_shader *fs = r300_fs(r300);
217 unsigned imm_count = fs->shader->immediates_count;
218 struct r300_fragment_program_code *code = &fs->shader->code.code.r300;
219
220 return 19 +
221 code->alu.length * 4 +
222 (code->tex.length ? (1 + code->tex.length) : 0) +
223 (imm_count ? imm_count * 5 : 0);
224 }
225
226 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
227 {
228 struct r300_fragment_shader *fs = r300_fs(r300);
229 struct rX00_fragment_program_code* generic_code = &fs->shader->code;
230 struct r300_fragment_program_code * code = &generic_code->code.r300;
231 unsigned i;
232 unsigned imm_count = fs->shader->immediates_count;
233 unsigned imm_first = fs->shader->externals_count;
234 unsigned imm_end = generic_code->constants.Count;
235 struct rc_constant *constants = generic_code->constants.Constants;
236 CS_LOCALS(r300);
237
238 BEGIN_CS(size);
239 OUT_CS_REG(R300_US_CONFIG, code->config);
240 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
241 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
242
243 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
244 OUT_CS_TABLE(code->code_addr, 4);
245
246 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
247 for (i = 0; i < code->alu.length; i++)
248 OUT_CS(code->alu.inst[i].rgb_inst);
249
250 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
251 for (i = 0; i < code->alu.length; i++)
252 OUT_CS(code->alu.inst[i].rgb_addr);
253
254 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
255 for (i = 0; i < code->alu.length; i++)
256 OUT_CS(code->alu.inst[i].alpha_inst);
257
258 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
259 for (i = 0; i < code->alu.length; i++)
260 OUT_CS(code->alu.inst[i].alpha_addr);
261
262 if (code->tex.length) {
263 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
264 OUT_CS_TABLE(code->tex.inst, code->tex.length);
265 }
266
267 /* Emit immediates. */
268 if (imm_count) {
269 for(i = imm_first; i < imm_end; ++i) {
270 if (constants[i].Type == RC_CONSTANT_IMMEDIATE) {
271 const float *data = constants[i].u.Immediate;
272
273 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
274 OUT_CS(pack_float24(data[0]));
275 OUT_CS(pack_float24(data[1]));
276 OUT_CS(pack_float24(data[2]));
277 OUT_CS(pack_float24(data[3]));
278 }
279 }
280 }
281
282 OUT_CS_REG(R300_FG_DEPTH_SRC, fs->shader->fg_depth_src);
283 OUT_CS_REG(R300_US_W_FMT, fs->shader->us_out_w);
284 END_CS;
285 }
286
287 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
288 {
289 struct r300_fragment_shader *fs = r300_fs(r300);
290 struct rc_constant_list *constants = &fs->shader->code.constants;
291 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
292 unsigned i, count = fs->shader->externals_count;
293 CS_LOCALS(r300);
294
295 if (count == 0)
296 return;
297
298 BEGIN_CS(size);
299 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
300 for(i = 0; i < count; ++i) {
301 const float *data;
302 assert(constants->Constants[i].Type == RC_CONSTANT_EXTERNAL);
303 data = buf->constants[i];
304 OUT_CS(pack_float24(data[0]));
305 OUT_CS(pack_float24(data[1]));
306 OUT_CS(pack_float24(data[2]));
307 OUT_CS(pack_float24(data[3]));
308 }
309 END_CS;
310 }
311
312 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
313 {
314 struct r300_fragment_shader *fs = r300_fs(r300);
315 struct rc_constant_list *constants = &fs->shader->code.constants;
316 unsigned i;
317 unsigned count = fs->shader->rc_state_count;
318 unsigned first = fs->shader->externals_count;
319 unsigned end = constants->Count;
320 CS_LOCALS(r300);
321
322 if (count == 0)
323 return;
324
325 BEGIN_CS(size);
326 for(i = first; i < end; ++i) {
327 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
328 const float *data =
329 get_rc_constant_state(r300, &constants->Constants[i]);
330
331 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
332 OUT_CS(pack_float24(data[0]));
333 OUT_CS(pack_float24(data[1]));
334 OUT_CS(pack_float24(data[2]));
335 OUT_CS(pack_float24(data[3]));
336 }
337 }
338 END_CS;
339 }
340
341 unsigned r500_get_fs_atom_size(struct r300_context *r300)
342 {
343 struct r300_fragment_shader *fs = r300_fs(r300);
344 unsigned imm_count = fs->shader->immediates_count;
345 struct r500_fragment_program_code *code = &fs->shader->code.code.r500;
346
347 return 17 +
348 ((code->inst_end + 1) * 6) +
349 (imm_count ? imm_count * 7 : 0);
350 }
351
352 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
353 {
354 struct r300_fragment_shader *fs = r300_fs(r300);
355 struct rX00_fragment_program_code* generic_code = &fs->shader->code;
356 struct r500_fragment_program_code * code = &generic_code->code.r500;
357 unsigned i;
358 unsigned imm_count = fs->shader->immediates_count;
359 unsigned imm_first = fs->shader->externals_count;
360 unsigned imm_end = generic_code->constants.Count;
361 struct rc_constant *constants = generic_code->constants.Constants;
362 CS_LOCALS(r300);
363
364 BEGIN_CS(size);
365 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
366 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
367 OUT_CS_REG(R500_US_CODE_RANGE,
368 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
369 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
370 OUT_CS_REG(R500_US_CODE_ADDR,
371 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
372
373 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
374 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
375 for (i = 0; i <= code->inst_end; i++) {
376 OUT_CS(code->inst[i].inst0);
377 OUT_CS(code->inst[i].inst1);
378 OUT_CS(code->inst[i].inst2);
379 OUT_CS(code->inst[i].inst3);
380 OUT_CS(code->inst[i].inst4);
381 OUT_CS(code->inst[i].inst5);
382 }
383
384 /* Emit immediates. */
385 if (imm_count) {
386 for(i = imm_first; i < imm_end; ++i) {
387 if (constants[i].Type == RC_CONSTANT_IMMEDIATE) {
388 const float *data = constants[i].u.Immediate;
389
390 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
391 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
392 (i & R500_GA_US_VECTOR_INDEX_MASK));
393 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
394 OUT_CS_TABLE(data, 4);
395 }
396 }
397 }
398
399 OUT_CS_REG(R300_FG_DEPTH_SRC, fs->shader->fg_depth_src);
400 OUT_CS_REG(R300_US_W_FMT, fs->shader->us_out_w);
401 END_CS;
402 }
403
404 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
405 {
406 struct r300_fragment_shader *fs = r300_fs(r300);
407 struct rc_constant_list *constants = &fs->shader->code.constants;
408 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
409 unsigned i, count = fs->shader->externals_count;
410 CS_LOCALS(r300);
411
412 if (count == 0)
413 return;
414
415 BEGIN_CS(size);
416 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
417 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
418 for(i = 0; i < count; ++i) {
419 const float *data;
420 assert(constants->Constants[i].Type == RC_CONSTANT_EXTERNAL);
421 data = buf->constants[i];
422
423 OUT_CS_TABLE(data, 4);
424 }
425 END_CS;
426 }
427
428 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
429 {
430 struct r300_fragment_shader *fs = r300_fs(r300);
431 struct rc_constant_list *constants = &fs->shader->code.constants;
432 unsigned i;
433 unsigned count = fs->shader->rc_state_count;
434 unsigned first = fs->shader->externals_count;
435 unsigned end = constants->Count;
436 CS_LOCALS(r300);
437
438 if (count == 0)
439 return;
440
441 BEGIN_CS(size);
442 for(i = first; i < end; ++i) {
443 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
444 const float *data =
445 get_rc_constant_state(r300, &constants->Constants[i]);
446
447 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
448 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
449 (i & R500_GA_US_VECTOR_INDEX_MASK));
450 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
451 OUT_CS_TABLE(data, 4);
452 }
453 }
454 END_CS;
455 }
456
457 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
458 {
459 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
460 struct r300_texture* tex;
461 struct pipe_surface* surf;
462 int i;
463 CS_LOCALS(r300);
464
465 BEGIN_CS(size);
466
467 /* Flush and free renderbuffer caches. */
468 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
469 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
470 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
471 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
472 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
473 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
474
475 /* Set the number of colorbuffers. */
476 if (fb->nr_cbufs > 1) {
477 if (r300->screen->caps.is_r500) {
478 OUT_CS_REG(R300_RB3D_CCTL,
479 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
480 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
481 } else {
482 OUT_CS_REG(R300_RB3D_CCTL,
483 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
484 }
485 } else {
486 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
487 }
488
489 /* Set up colorbuffers. */
490 for (i = 0; i < fb->nr_cbufs; i++) {
491 surf = fb->cbufs[i];
492 tex = r300_texture(surf->texture);
493 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
494
495 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
496 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
497
498 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
499 OUT_CS_TEX_RELOC(tex, tex->fb_state.colorpitch[surf->level],
500 0, RADEON_GEM_DOMAIN_VRAM, 0);
501
502 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
503 }
504 for (; i < 4; i++) {
505 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
506 }
507
508 /* Set up a zbuffer. */
509 if (fb->zsbuf) {
510 surf = fb->zsbuf;
511 tex = r300_texture(surf->texture);
512 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
513
514 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
515 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
516
517 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
518
519 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
520 OUT_CS_TEX_RELOC(tex, tex->fb_state.depthpitch[surf->level],
521 0, RADEON_GEM_DOMAIN_VRAM, 0);
522 }
523
524 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
525 if (r300->screen->caps.is_r500) {
526 OUT_CS(0);
527 OUT_CS(((fb->width - 1) << R300_SCISSORS_X_SHIFT) |
528 ((fb->height - 1) << R300_SCISSORS_Y_SHIFT));
529 } else {
530 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
531 (1440 << R300_SCISSORS_Y_SHIFT));
532 OUT_CS(((fb->width + 1440-1) << R300_SCISSORS_X_SHIFT) |
533 ((fb->height + 1440-1) << R300_SCISSORS_Y_SHIFT));
534 }
535 OUT_CS_REG(R300_GA_POINT_MINMAX,
536 (MAX2(fb->width, fb->height) * 6) << R300_GA_POINT_MINMAX_MAX_SHIFT);
537 END_CS;
538 }
539
540 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
541 {
542 struct r300_query *query = r300->query_current;
543 CS_LOCALS(r300);
544
545 if (!query)
546 return;
547
548 BEGIN_CS(size);
549 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
550 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
551 } else {
552 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
553 }
554 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
555 END_CS;
556 query->begin_emitted = TRUE;
557 }
558
559
560 static void r300_emit_query_finish(struct r300_context *r300,
561 struct r300_query *query)
562 {
563 struct r300_capabilities* caps = &r300->screen->caps;
564 CS_LOCALS(r300);
565
566 assert(caps->num_frag_pipes);
567
568 BEGIN_CS(6 * caps->num_frag_pipes + 2);
569 /* I'm not so sure I like this switch, but it's hard to be elegant
570 * when there's so many special cases...
571 *
572 * So here's the basic idea. For each pipe, enable writes to it only,
573 * then put out the relocation for ZPASS_ADDR, taking into account a
574 * 4-byte offset for each pipe. RV380 and older are special; they have
575 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
576 * so there's a chipset cap for that. */
577 switch (caps->num_frag_pipes) {
578 case 4:
579 /* pipe 3 only */
580 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
581 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
582 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
583 0, RADEON_GEM_DOMAIN_GTT, 0);
584 case 3:
585 /* pipe 2 only */
586 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
587 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
588 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
589 0, RADEON_GEM_DOMAIN_GTT, 0);
590 case 2:
591 /* pipe 1 only */
592 /* As mentioned above, accomodate RV380 and older. */
593 OUT_CS_REG(R300_SU_REG_DEST,
594 1 << (caps->high_second_pipe ? 3 : 1));
595 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
596 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
597 0, RADEON_GEM_DOMAIN_GTT, 0);
598 case 1:
599 /* pipe 0 only */
600 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
601 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
602 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
603 0, RADEON_GEM_DOMAIN_GTT, 0);
604 break;
605 default:
606 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
607 " pixel pipes!\n", caps->num_frag_pipes);
608 abort();
609 }
610
611 /* And, finally, reset it to normal... */
612 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
613 END_CS;
614 }
615
616 static void rv530_emit_query_single(struct r300_context *r300,
617 struct r300_query *query)
618 {
619 CS_LOCALS(r300);
620
621 BEGIN_CS(8);
622 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
623 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
624 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
625 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
626 END_CS;
627 }
628
629 static void rv530_emit_query_double(struct r300_context *r300,
630 struct r300_query *query)
631 {
632 CS_LOCALS(r300);
633
634 BEGIN_CS(14);
635 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
636 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
637 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
638 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
639 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
640 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
641 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
642 END_CS;
643 }
644
645 void r300_emit_query_end(struct r300_context* r300)
646 {
647 struct r300_capabilities *caps = &r300->screen->caps;
648 struct r300_query *query = r300->query_current;
649
650 if (!query)
651 return;
652
653 if (query->begin_emitted == FALSE)
654 return;
655
656 if (caps->family == CHIP_FAMILY_RV530) {
657 if (caps->num_z_pipes == 2)
658 rv530_emit_query_double(r300, query);
659 else
660 rv530_emit_query_single(r300, query);
661 } else
662 r300_emit_query_finish(r300, query);
663 }
664
665 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
666 {
667 struct r300_rs_state* rs = (struct r300_rs_state*)state;
668 float scale, offset;
669 CS_LOCALS(r300);
670
671 BEGIN_CS(size);
672 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
673
674 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
675
676 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
677 OUT_CS_REG(R300_GA_LINE_CNTL, rs->line_control);
678
679 if (rs->polygon_offset_enable) {
680 scale = rs->depth_scale * 12;
681 offset = rs->depth_offset;
682
683 switch (r300->zbuffer_bpp) {
684 case 16:
685 offset *= 4;
686 break;
687 case 24:
688 offset *= 2;
689 break;
690 }
691
692 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
693 OUT_CS_32F(scale);
694 OUT_CS_32F(offset);
695 OUT_CS_32F(scale);
696 OUT_CS_32F(offset);
697 }
698
699 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
700 OUT_CS(rs->polygon_offset_enable);
701 OUT_CS(rs->cull_mode);
702 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
703 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
704 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
705 OUT_CS_REG(R300_SC_CLIP_RULE, rs->clip_rule);
706 OUT_CS_REG(R300_GB_ENABLE, rs->stuffing_enable);
707 OUT_CS_REG_SEQ(R300_GA_POINT_S0, 4);
708 OUT_CS_32F(rs->point_texcoord_left);
709 OUT_CS_32F(rs->point_texcoord_bottom);
710 OUT_CS_32F(rs->point_texcoord_right);
711 OUT_CS_32F(rs->point_texcoord_top);
712 END_CS;
713 }
714
715 void r300_emit_rs_block_state(struct r300_context* r300,
716 unsigned size, void* state)
717 {
718 struct r300_rs_block* rs = (struct r300_rs_block*)state;
719 unsigned i;
720 /* It's the same for both INST and IP tables */
721 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
722 CS_LOCALS(r300);
723
724 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
725
726 BEGIN_CS(size);
727 if (r300->screen->caps.is_r500) {
728 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
729 } else {
730 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
731 }
732 OUT_CS_TABLE(rs->ip, count);
733 for (i = 0; i < count; i++) {
734 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
735 }
736
737 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
738 OUT_CS(rs->count);
739 OUT_CS(rs->inst_count);
740
741 if (r300->screen->caps.is_r500) {
742 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
743 } else {
744 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
745 }
746 OUT_CS_TABLE(rs->inst, count);
747 for (i = 0; i < count; i++) {
748 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
749 }
750
751 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
752 rs->count, rs->inst_count);
753
754 END_CS;
755 }
756
757 void r300_emit_scissor_state(struct r300_context* r300,
758 unsigned size, void* state)
759 {
760 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
761 CS_LOCALS(r300);
762
763 BEGIN_CS(size);
764 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
765 if (r300->screen->caps.is_r500) {
766 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
767 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
768 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
769 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
770 } else {
771 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
772 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
773 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
774 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
775 }
776 END_CS;
777 }
778
779 void r300_emit_textures_state(struct r300_context *r300,
780 unsigned size, void *state)
781 {
782 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
783 struct r300_texture_sampler_state *texstate;
784 unsigned i;
785 CS_LOCALS(r300);
786
787 BEGIN_CS(size);
788 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
789
790 for (i = 0; i < allstate->count; i++) {
791 if ((1 << i) & allstate->tx_enable) {
792 texstate = &allstate->regs[i];
793
794 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
795 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
796 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
797 texstate->border_color);
798
799 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
800 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
801 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
802
803 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
804 OUT_CS_TEX_RELOC(r300_texture(allstate->sampler_views[i]->base.texture),
805 texstate->format.tile_config,
806 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
807 }
808 }
809 END_CS;
810 }
811
812 void r300_emit_aos(struct r300_context* r300, unsigned offset, boolean indexed)
813 {
814 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
815 struct pipe_vertex_element *velem = r300->velems->velem;
816 int i;
817 unsigned size1, size2, aos_count = r300->velems->count;
818 unsigned packet_size = (aos_count * 3 + 1) / 2;
819 CS_LOCALS(r300);
820
821 for (i = 0; i < aos_count; i++) {
822 if ((vbuf[velem[i].vertex_buffer_index].buffer_offset + velem[i].src_offset) % 4 != 0) {
823 /* XXX We must align the buffer. */
824 assert(0);
825 fprintf(stderr, "r300: Unaligned vertex buffer offsets aren't supported, aborting..\n");
826 abort();
827 }
828 }
829
830 BEGIN_CS(2 + packet_size + aos_count * 2);
831 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
832 OUT_CS(aos_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
833
834 for (i = 0; i < aos_count - 1; i += 2) {
835 vb1 = &vbuf[velem[i].vertex_buffer_index];
836 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
837 size1 = util_format_get_blocksize(velem[i].src_format);
838 size2 = util_format_get_blocksize(velem[i+1].src_format);
839
840 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
841 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
842 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
843 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
844 }
845
846 if (aos_count & 1) {
847 vb1 = &vbuf[velem[i].vertex_buffer_index];
848 size1 = util_format_get_blocksize(velem[i].src_format);
849
850 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
851 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
852 }
853
854 for (i = 0; i < aos_count; i++) {
855 OUT_CS_BUF_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
856 RADEON_GEM_DOMAIN_GTT, 0, 0);
857 }
858 END_CS;
859 }
860
861 void r300_emit_vertex_buffer(struct r300_context* r300)
862 {
863 CS_LOCALS(r300);
864
865 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
866 "vertex size %d\n", r300->vbo,
867 r300->vertex_info.size);
868 /* Set the pointer to our vertex buffer. The emitted values are this:
869 * PACKET3 [3D_LOAD_VBPNTR]
870 * COUNT [1]
871 * FORMAT [size | stride << 8]
872 * OFFSET [offset into BO]
873 * VBPNTR [relocated BO]
874 */
875 BEGIN_CS(7);
876 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
877 OUT_CS(1);
878 OUT_CS(r300->vertex_info.size |
879 (r300->vertex_info.size << 8));
880 OUT_CS(r300->vbo_offset);
881 OUT_CS_BUF_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
882 END_CS;
883 }
884
885 void r300_emit_vertex_stream_state(struct r300_context* r300,
886 unsigned size, void* state)
887 {
888 struct r300_vertex_stream_state *streams =
889 (struct r300_vertex_stream_state*)state;
890 unsigned i;
891 CS_LOCALS(r300);
892
893 DBG(r300, DBG_DRAW, "r300: PSC emit:\n");
894
895 BEGIN_CS(size);
896 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
897 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
898 for (i = 0; i < streams->count; i++) {
899 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
900 streams->vap_prog_stream_cntl[i]);
901 }
902 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
903 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
904 for (i = 0; i < streams->count; i++) {
905 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
906 streams->vap_prog_stream_cntl_ext[i]);
907 }
908 END_CS;
909 }
910
911 void r300_emit_vap_output_state(struct r300_context* r300,
912 unsigned size, void* state)
913 {
914 struct r300_vap_output_state *vap_out_state =
915 (struct r300_vap_output_state*)state;
916 CS_LOCALS(r300);
917
918 DBG(r300, DBG_DRAW, "r300: VAP emit:\n");
919
920 BEGIN_CS(size);
921 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
922 OUT_CS(vap_out_state->vap_vtx_state_cntl);
923 OUT_CS(vap_out_state->vap_vsm_vtx_assm);
924 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
925 OUT_CS(vap_out_state->vap_out_vtx_fmt[0]);
926 OUT_CS(vap_out_state->vap_out_vtx_fmt[1]);
927 END_CS;
928 }
929
930 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
931 {
932 CS_LOCALS(r300);
933
934 BEGIN_CS(size);
935 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
936 END_CS;
937 }
938
939 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
940 {
941 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
942 struct r300_vertex_program_code* code = &vs->code;
943 struct r300_screen* r300screen = r300->screen;
944 unsigned instruction_count = code->length / 4;
945 unsigned i;
946
947 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
948 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
949 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
950 unsigned temp_count = MAX2(code->num_temporaries, 1);
951
952 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
953 vtx_mem_size / output_count, 10);
954 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
955
956 unsigned imm_first = vs->externals_count;
957 unsigned imm_end = vs->code.constants.Count;
958 unsigned imm_count = vs->immediates_count;
959
960 CS_LOCALS(r300);
961
962 BEGIN_CS(size);
963 /* R300_VAP_PVS_CODE_CNTL_0
964 * R300_VAP_PVS_CONST_CNTL
965 * R300_VAP_PVS_CODE_CNTL_1
966 * See the r5xx docs for instructions on how to use these. */
967 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
968 OUT_CS(R300_PVS_FIRST_INST(0) |
969 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
970 R300_PVS_LAST_INST(instruction_count - 1));
971 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
972 OUT_CS(instruction_count - 1);
973
974 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
975 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
976 OUT_CS_TABLE(code->body.d, code->length);
977
978 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
979 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
980 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
981 R300_PVS_VF_MAX_VTX_NUM(12) |
982 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
983
984 /* Emit immediates. */
985 if (imm_count) {
986 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
987 (r300->screen->caps.is_r500 ?
988 R500_PVS_CONST_START : R300_PVS_CONST_START) +
989 imm_first);
990 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
991 for (i = imm_first; i < imm_end; i++) {
992 const float *data = vs->code.constants.Constants[i].u.Immediate;
993 OUT_CS_TABLE(data, 4);
994 }
995 }
996 END_CS;
997 }
998
999 void r300_emit_vs_constants(struct r300_context* r300,
1000 unsigned size, void *state)
1001 {
1002 unsigned i;
1003 unsigned count =
1004 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
1005 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
1006 CS_LOCALS(r300);
1007
1008 if (!count)
1009 return;
1010
1011 BEGIN_CS(size);
1012 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1013 (r300->screen->caps.is_r500 ?
1014 R500_PVS_CONST_START : R300_PVS_CONST_START));
1015 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1016 for (i = 0; i < count; i++) {
1017 const float *data = buf->constants[i];
1018 OUT_CS_TABLE(data, 4);
1019 }
1020 END_CS;
1021 }
1022
1023 void r300_emit_viewport_state(struct r300_context* r300,
1024 unsigned size, void* state)
1025 {
1026 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1027 CS_LOCALS(r300);
1028
1029 BEGIN_CS(size);
1030 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1031 OUT_CS_32F(viewport->xscale);
1032 OUT_CS_32F(viewport->xoffset);
1033 OUT_CS_32F(viewport->yscale);
1034 OUT_CS_32F(viewport->yoffset);
1035 OUT_CS_32F(viewport->zscale);
1036 OUT_CS_32F(viewport->zoffset);
1037 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1038 END_CS;
1039 }
1040
1041 void r300_emit_ztop_state(struct r300_context* r300,
1042 unsigned size, void* state)
1043 {
1044 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1045 CS_LOCALS(r300);
1046
1047 BEGIN_CS(size);
1048 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1049 END_CS;
1050 }
1051
1052 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1053 {
1054 CS_LOCALS(r300);
1055
1056 BEGIN_CS(size);
1057 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1058 END_CS;
1059 }
1060
1061 void r300_emit_buffer_validate(struct r300_context *r300,
1062 boolean do_validate_vertex_buffers,
1063 struct pipe_resource *index_buffer)
1064 {
1065 struct pipe_framebuffer_state* fb =
1066 (struct pipe_framebuffer_state*)r300->fb_state.state;
1067 struct r300_textures_state *texstate =
1068 (struct r300_textures_state*)r300->textures_state.state;
1069 struct r300_texture* tex;
1070 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1071 struct pipe_vertex_element *velem = r300->velems->velem;
1072 struct pipe_resource *pbuf;
1073 unsigned i;
1074 boolean invalid = FALSE;
1075
1076 /* upload buffers first */
1077 if (r300->any_user_vbs) {
1078 r300_upload_user_buffers(r300);
1079 r300->any_user_vbs = false;
1080 }
1081
1082 /* Clean out BOs. */
1083 r300->rws->reset_bos(r300->rws);
1084
1085 validate:
1086 /* Color buffers... */
1087 for (i = 0; i < fb->nr_cbufs; i++) {
1088 tex = r300_texture(fb->cbufs[i]->texture);
1089 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1090 if (!r300_add_texture(r300->rws, tex,
1091 0, RADEON_GEM_DOMAIN_VRAM)) {
1092 r300->context.flush(&r300->context, 0, NULL);
1093 goto validate;
1094 }
1095 }
1096 /* ...depth buffer... */
1097 if (fb->zsbuf) {
1098 tex = r300_texture(fb->zsbuf->texture);
1099 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1100 if (!r300_add_texture(r300->rws, tex,
1101 0, RADEON_GEM_DOMAIN_VRAM)) {
1102 r300->context.flush(&r300->context, 0, NULL);
1103 goto validate;
1104 }
1105 }
1106 /* ...textures... */
1107 for (i = 0; i < texstate->count; i++) {
1108 if (!(texstate->tx_enable & (1 << i))) {
1109 continue;
1110 }
1111
1112 tex = r300_texture(texstate->sampler_views[i]->base.texture);
1113 if (!r300_add_texture(r300->rws, tex,
1114 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1115 r300->context.flush(&r300->context, 0, NULL);
1116 goto validate;
1117 }
1118 }
1119 /* ...occlusion query buffer... */
1120 if (r300->query_start.dirty) {
1121 if (!r300_add_buffer(r300->rws, r300->oqbo,
1122 0, RADEON_GEM_DOMAIN_GTT)) {
1123 r300->context.flush(&r300->context, 0, NULL);
1124 goto validate;
1125 }
1126 }
1127 /* ...vertex buffer for SWTCL path... */
1128 if (r300->vbo) {
1129 if (!r300_add_buffer(r300->rws, r300->vbo,
1130 RADEON_GEM_DOMAIN_GTT, 0)) {
1131 r300->context.flush(&r300->context, 0, NULL);
1132 goto validate;
1133 }
1134 }
1135 /* ...vertex buffers for HWTCL path... */
1136 if (do_validate_vertex_buffers) {
1137 for (i = 0; i < r300->velems->count; i++) {
1138 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1139
1140 if (!r300_add_buffer(r300->rws, pbuf,
1141 RADEON_GEM_DOMAIN_GTT, 0)) {
1142 r300->context.flush(&r300->context, 0, NULL);
1143 goto validate;
1144 }
1145 }
1146 }
1147 /* ...and index buffer for HWTCL path. */
1148 if (index_buffer) {
1149 if (!r300_add_buffer(r300->rws, index_buffer,
1150 RADEON_GEM_DOMAIN_GTT, 0)) {
1151 r300->context.flush(&r300->context, 0, NULL);
1152 goto validate;
1153 }
1154 }
1155 if (!r300->rws->validate(r300->rws)) {
1156 r300->context.flush(&r300->context, 0, NULL);
1157 if (invalid) {
1158 /* Well, hell. */
1159 fprintf(stderr, "r300: Stuck in validation loop, gonna quit now.\n");
1160 abort();
1161 }
1162 invalid = TRUE;
1163 goto validate;
1164 }
1165 }
1166
1167 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1168 {
1169 struct r300_atom* atom;
1170 unsigned dwords = 0;
1171
1172 foreach(atom, &r300->atom_list) {
1173 if (atom->dirty) {
1174 dwords += atom->size;
1175 }
1176 }
1177
1178 return dwords;
1179 }
1180
1181 /* Emit all dirty state. */
1182 void r300_emit_dirty_state(struct r300_context* r300)
1183 {
1184 struct r300_screen* r300screen = r300->screen;
1185 struct r300_atom* atom;
1186
1187 foreach(atom, &r300->atom_list) {
1188 if (atom->dirty) {
1189 atom->emit(r300, atom->size, atom->state);
1190 atom->dirty = FALSE;
1191 }
1192 }
1193
1194 /* Emit the VBO for SWTCL. */
1195 if (!r300screen->caps.has_tcl) {
1196 r300_emit_vertex_buffer(r300);
1197 }
1198
1199 r300->dirty_hw++;
1200 }