2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
30 #include "r300_context.h"
32 #include "r300_emit.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
38 void r300_emit_blend_state(struct r300_context
* r300
,
39 unsigned size
, void* state
)
41 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
42 struct pipe_framebuffer_state
* fb
=
43 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
47 OUT_CS_REG(R300_RB3D_ROPCNTL
, blend
->rop
);
48 OUT_CS_REG_SEQ(R300_RB3D_CBLEND
, 3);
50 OUT_CS(blend
->blend_control
);
51 OUT_CS(blend
->alpha_blend_control
);
52 OUT_CS(blend
->color_channel_mask
);
57 /* XXX also disable fastfill here once it's supported */
59 OUT_CS_REG(R300_RB3D_DITHER_CTL
, blend
->dither
);
63 void r300_emit_blend_color_state(struct r300_context
* r300
,
64 unsigned size
, void* state
)
66 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
69 if (r300
->screen
->caps
.is_r500
) {
71 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR
, 2);
72 OUT_CS(bc
->blend_color_red_alpha
);
73 OUT_CS(bc
->blend_color_green_blue
);
77 OUT_CS_REG(R300_RB3D_BLEND_COLOR
, bc
->blend_color
);
82 void r300_emit_clip_state(struct r300_context
* r300
,
83 unsigned size
, void* state
)
85 struct pipe_clip_state
* clip
= (struct pipe_clip_state
*)state
;
89 if (r300
->screen
->caps
.has_tcl
) {
91 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
92 (r300
->screen
->caps
.is_r500
?
93 R500_PVS_UCP_START
: R300_PVS_UCP_START
));
94 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, 6 * 4);
95 for (i
= 0; i
< 6; i
++) {
96 OUT_CS_32F(clip
->ucp
[i
][0]);
97 OUT_CS_32F(clip
->ucp
[i
][1]);
98 OUT_CS_32F(clip
->ucp
[i
][2]);
99 OUT_CS_32F(clip
->ucp
[i
][3]);
101 OUT_CS_REG(R300_VAP_CLIP_CNTL
, ((1 << clip
->nr
) - 1) |
102 R300_PS_UCP_MODE_CLIP_AS_TRIFAN
);
106 OUT_CS_REG(R300_VAP_CLIP_CNTL
, R300_CLIP_DISABLE
);
112 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
114 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
115 struct pipe_framebuffer_state
* fb
=
116 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
117 struct pipe_stencil_ref stencil_ref
= r300
->stencil_ref
;
121 OUT_CS_REG(R300_FG_ALPHA_FUNC
, dsa
->alpha_function
);
122 OUT_CS_REG_SEQ(R300_ZB_CNTL
, 3);
125 OUT_CS(dsa
->z_buffer_control
);
126 OUT_CS(dsa
->z_stencil_control
);
132 OUT_CS(dsa
->stencil_ref_mask
| stencil_ref
.ref_value
[0]);
134 if (r300
->screen
->caps
.is_r500
) {
135 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF
, dsa
->stencil_ref_bf
| stencil_ref
.ref_value
[1]);
140 static const float * get_rc_constant_state(
141 struct r300_context
* r300
,
142 struct rc_constant
* constant
)
144 struct r300_viewport_state
* viewport
= r300
->viewport_state
.state
;
145 struct r300_textures_state
* texstate
= r300
->textures_state
.state
;
146 static float vec
[4] = { 0.0, 0.0, 0.0, 1.0 };
147 struct pipe_resource
*tex
;
149 assert(constant
->Type
== RC_CONSTANT_STATE
);
151 switch (constant
->u
.State
[0]) {
152 /* Factor for converting rectangle coords to
153 * normalized coords. Should only show up on non-r500. */
154 case RC_STATE_R300_TEXRECT_FACTOR
:
155 tex
= texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
;
156 vec
[0] = 1.0 / tex
->width0
;
157 vec
[1] = 1.0 / tex
->height0
;
160 case RC_STATE_R300_VIEWPORT_SCALE
:
161 vec
[0] = viewport
->xscale
;
162 vec
[1] = viewport
->yscale
;
163 vec
[2] = viewport
->zscale
;
166 case RC_STATE_R300_VIEWPORT_OFFSET
:
167 vec
[0] = viewport
->xoffset
;
168 vec
[1] = viewport
->yoffset
;
169 vec
[2] = viewport
->zoffset
;
173 fprintf(stderr
, "r300: Implementation error: "
174 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
177 /* This should either be (0, 0, 0, 1), which should be a relatively safe
178 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
183 /* Convert a normal single-precision float into the 7.16 format
184 * used by the R300 fragment shader.
186 static uint32_t pack_float24(float f
)
194 uint32_t float24
= 0;
201 mantissa
= frexpf(f
, &exponent
);
205 float24
|= (1 << 23);
206 mantissa
= mantissa
* -1.0;
208 /* Handle exponent, bias of 63 */
210 float24
|= (exponent
<< 16);
211 /* Kill 7 LSB of mantissa */
212 float24
|= (u
.u
& 0x7FFFFF) >> 7;
217 unsigned r300_get_fs_atom_size(struct r300_context
*r300
)
219 struct r300_fragment_shader
*fs
= r300_fs(r300
);
220 unsigned imm_count
= fs
->shader
->immediates_count
;
221 struct r300_fragment_program_code
*code
= &fs
->shader
->code
.code
.r300
;
224 code
->alu
.length
* 4 +
225 (code
->tex
.length
? (1 + code
->tex
.length
) : 0) +
226 (imm_count
? imm_count
* 5 : 0);
229 void r300_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
231 struct r300_fragment_shader
*fs
= r300_fs(r300
);
232 struct rX00_fragment_program_code
* generic_code
= &fs
->shader
->code
;
233 struct r300_fragment_program_code
* code
= &generic_code
->code
.r300
;
235 unsigned imm_count
= fs
->shader
->immediates_count
;
236 unsigned imm_first
= fs
->shader
->externals_count
;
237 unsigned imm_end
= generic_code
->constants
.Count
;
238 struct rc_constant
*constants
= generic_code
->constants
.Constants
;
242 OUT_CS_REG(R300_US_CONFIG
, code
->config
);
243 OUT_CS_REG(R300_US_PIXSIZE
, code
->pixsize
);
244 OUT_CS_REG(R300_US_CODE_OFFSET
, code
->code_offset
);
246 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0
, 4);
247 for(i
= 0; i
< 4; ++i
)
248 OUT_CS(code
->code_addr
[i
]);
250 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0
, code
->alu
.length
);
251 for (i
= 0; i
< code
->alu
.length
; i
++)
252 OUT_CS(code
->alu
.inst
[i
].rgb_inst
);
254 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0
, code
->alu
.length
);
255 for (i
= 0; i
< code
->alu
.length
; i
++)
256 OUT_CS(code
->alu
.inst
[i
].rgb_addr
);
258 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0
, code
->alu
.length
);
259 for (i
= 0; i
< code
->alu
.length
; i
++)
260 OUT_CS(code
->alu
.inst
[i
].alpha_inst
);
262 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0
, code
->alu
.length
);
263 for (i
= 0; i
< code
->alu
.length
; i
++)
264 OUT_CS(code
->alu
.inst
[i
].alpha_addr
);
266 if (code
->tex
.length
) {
267 OUT_CS_REG_SEQ(R300_US_TEX_INST_0
, code
->tex
.length
);
268 for(i
= 0; i
< code
->tex
.length
; ++i
)
269 OUT_CS(code
->tex
.inst
[i
]);
272 /* Emit immediates. */
274 for(i
= imm_first
; i
< imm_end
; ++i
) {
275 if (constants
[i
].Type
== RC_CONSTANT_IMMEDIATE
) {
276 const float *data
= constants
[i
].u
.Immediate
;
278 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
279 OUT_CS(pack_float24(data
[0]));
280 OUT_CS(pack_float24(data
[1]));
281 OUT_CS(pack_float24(data
[2]));
282 OUT_CS(pack_float24(data
[3]));
287 OUT_CS_REG(R300_FG_DEPTH_SRC
, fs
->shader
->fg_depth_src
);
288 OUT_CS_REG(R300_US_W_FMT
, fs
->shader
->us_out_w
);
292 void r300_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
294 struct r300_fragment_shader
*fs
= r300_fs(r300
);
295 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
296 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
297 unsigned i
, count
= fs
->shader
->externals_count
;
304 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, count
* 4);
305 for(i
= 0; i
< count
; ++i
) {
307 assert(constants
->Constants
[i
].Type
== RC_CONSTANT_EXTERNAL
);
308 data
= buf
->constants
[i
];
309 OUT_CS(pack_float24(data
[0]));
310 OUT_CS(pack_float24(data
[1]));
311 OUT_CS(pack_float24(data
[2]));
312 OUT_CS(pack_float24(data
[3]));
317 void r300_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
319 struct r300_fragment_shader
*fs
= r300_fs(r300
);
320 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
322 unsigned count
= fs
->shader
->rc_state_count
;
323 unsigned first
= fs
->shader
->externals_count
;
324 unsigned end
= constants
->Count
;
331 for(i
= first
; i
< end
; ++i
) {
332 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
334 get_rc_constant_state(r300
, &constants
->Constants
[i
]);
336 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
337 OUT_CS(pack_float24(data
[0]));
338 OUT_CS(pack_float24(data
[1]));
339 OUT_CS(pack_float24(data
[2]));
340 OUT_CS(pack_float24(data
[3]));
346 unsigned r500_get_fs_atom_size(struct r300_context
*r300
)
348 struct r300_fragment_shader
*fs
= r300_fs(r300
);
349 unsigned imm_count
= fs
->shader
->immediates_count
;
350 struct r500_fragment_program_code
*code
= &fs
->shader
->code
.code
.r500
;
353 ((code
->inst_end
+ 1) * 6) +
354 (imm_count
? imm_count
* 7 : 0);
357 void r500_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
359 struct r300_fragment_shader
*fs
= r300_fs(r300
);
360 struct rX00_fragment_program_code
* generic_code
= &fs
->shader
->code
;
361 struct r500_fragment_program_code
* code
= &generic_code
->code
.r500
;
363 unsigned imm_count
= fs
->shader
->immediates_count
;
364 unsigned imm_first
= fs
->shader
->externals_count
;
365 unsigned imm_end
= generic_code
->constants
.Count
;
366 struct rc_constant
*constants
= generic_code
->constants
.Constants
;
370 OUT_CS_REG(R500_US_CONFIG
, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO
);
371 OUT_CS_REG(R500_US_PIXSIZE
, code
->max_temp_idx
);
372 OUT_CS_REG(R500_US_CODE_RANGE
,
373 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code
->inst_end
));
374 OUT_CS_REG(R500_US_CODE_OFFSET
, 0);
375 OUT_CS_REG(R500_US_CODE_ADDR
,
376 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code
->inst_end
));
378 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_INSTR
);
379 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, (code
->inst_end
+ 1) * 6);
380 for (i
= 0; i
<= code
->inst_end
; i
++) {
381 OUT_CS(code
->inst
[i
].inst0
);
382 OUT_CS(code
->inst
[i
].inst1
);
383 OUT_CS(code
->inst
[i
].inst2
);
384 OUT_CS(code
->inst
[i
].inst3
);
385 OUT_CS(code
->inst
[i
].inst4
);
386 OUT_CS(code
->inst
[i
].inst5
);
389 /* Emit immediates. */
391 for(i
= imm_first
; i
< imm_end
; ++i
) {
392 if (constants
[i
].Type
== RC_CONSTANT_IMMEDIATE
) {
393 const float *data
= constants
[i
].u
.Immediate
;
395 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
396 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
397 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
398 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
407 OUT_CS_REG(R300_FG_DEPTH_SRC
, fs
->shader
->fg_depth_src
);
408 OUT_CS_REG(R300_US_W_FMT
, fs
->shader
->us_out_w
);
412 void r500_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
414 struct r300_fragment_shader
*fs
= r300_fs(r300
);
415 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
416 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
417 unsigned i
, count
= fs
->shader
->externals_count
;
424 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
425 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, count
* 4);
426 for(i
= 0; i
< count
; ++i
) {
428 assert(constants
->Constants
[i
].Type
== RC_CONSTANT_EXTERNAL
);
429 data
= buf
->constants
[i
];
439 void r500_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
441 struct r300_fragment_shader
*fs
= r300_fs(r300
);
442 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
444 unsigned count
= fs
->shader
->rc_state_count
;
445 unsigned first
= fs
->shader
->externals_count
;
446 unsigned end
= constants
->Count
;
453 for(i
= first
; i
< end
; ++i
) {
454 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
456 get_rc_constant_state(r300
, &constants
->Constants
[i
]);
458 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
459 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
460 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
461 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
471 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
473 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
474 struct r300_texture
* tex
;
475 struct pipe_surface
* surf
;
481 /* Flush and free renderbuffer caches. */
482 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT
,
483 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS
|
484 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
485 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
,
486 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
487 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);
489 /* Set the number of colorbuffers. */
490 if (fb
->nr_cbufs
> 1) {
491 if (r300
->screen
->caps
.is_r500
) {
492 OUT_CS_REG(R300_RB3D_CCTL
,
493 R300_RB3D_CCTL_NUM_MULTIWRITES(fb
->nr_cbufs
) |
494 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
);
496 OUT_CS_REG(R300_RB3D_CCTL
,
497 R300_RB3D_CCTL_NUM_MULTIWRITES(fb
->nr_cbufs
));
500 OUT_CS_REG(R300_RB3D_CCTL
, 0x0);
503 /* Set up colorbuffers. */
504 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
506 tex
= r300_texture(surf
->texture
);
507 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
509 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
+ (4 * i
), 1);
510 OUT_CS_TEX_RELOC(tex
, surf
->offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
512 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0
+ (4 * i
), 1);
513 OUT_CS_TEX_RELOC(tex
, tex
->fb_state
.colorpitch
[surf
->level
],
514 0, RADEON_GEM_DOMAIN_VRAM
, 0);
516 OUT_CS_REG(R300_US_OUT_FMT_0
+ (4 * i
), tex
->fb_state
.us_out_fmt
);
519 OUT_CS_REG(R300_US_OUT_FMT_0
+ (4 * i
), R300_US_OUT_FMT_UNUSED
);
522 /* Set up a zbuffer. */
525 tex
= r300_texture(surf
->texture
);
526 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
528 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
529 OUT_CS_TEX_RELOC(tex
, surf
->offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
531 OUT_CS_REG(R300_ZB_FORMAT
, tex
->fb_state
.zb_format
);
533 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
534 OUT_CS_TEX_RELOC(tex
, tex
->fb_state
.depthpitch
[surf
->level
],
535 0, RADEON_GEM_DOMAIN_VRAM
, 0);
538 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
539 if (r300
->screen
->caps
.is_r500
) {
541 OUT_CS(((fb
->width
- 1) << R300_SCISSORS_X_SHIFT
) |
542 ((fb
->height
- 1) << R300_SCISSORS_Y_SHIFT
));
544 OUT_CS((1440 << R300_SCISSORS_X_SHIFT
) |
545 (1440 << R300_SCISSORS_Y_SHIFT
));
546 OUT_CS(((fb
->width
+ 1440-1) << R300_SCISSORS_X_SHIFT
) |
547 ((fb
->height
+ 1440-1) << R300_SCISSORS_Y_SHIFT
));
549 OUT_CS_REG(R300_GA_POINT_MINMAX
,
550 (MAX2(fb
->width
, fb
->height
) * 6) << R300_GA_POINT_MINMAX_MAX_SHIFT
);
554 void r300_emit_query_start(struct r300_context
*r300
, unsigned size
, void*state
)
556 struct r300_query
*query
= r300
->query_current
;
563 if (r300
->screen
->caps
.family
== CHIP_FAMILY_RV530
) {
564 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
566 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
568 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
570 query
->begin_emitted
= TRUE
;
574 static void r300_emit_query_finish(struct r300_context
*r300
,
575 struct r300_query
*query
)
577 struct r300_capabilities
* caps
= &r300
->screen
->caps
;
580 assert(caps
->num_frag_pipes
);
582 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
583 /* I'm not so sure I like this switch, but it's hard to be elegant
584 * when there's so many special cases...
586 * So here's the basic idea. For each pipe, enable writes to it only,
587 * then put out the relocation for ZPASS_ADDR, taking into account a
588 * 4-byte offset for each pipe. RV380 and older are special; they have
589 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
590 * so there's a chipset cap for that. */
591 switch (caps
->num_frag_pipes
) {
594 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
595 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
596 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 3),
597 0, RADEON_GEM_DOMAIN_GTT
, 0);
600 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
601 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
602 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 2),
603 0, RADEON_GEM_DOMAIN_GTT
, 0);
606 /* As mentioned above, accomodate RV380 and older. */
607 OUT_CS_REG(R300_SU_REG_DEST
,
608 1 << (caps
->high_second_pipe
? 3 : 1));
609 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
610 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 1),
611 0, RADEON_GEM_DOMAIN_GTT
, 0);
614 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
615 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
616 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 0),
617 0, RADEON_GEM_DOMAIN_GTT
, 0);
620 fprintf(stderr
, "r300: Implementation error: Chipset reports %d"
621 " pixel pipes!\n", caps
->num_frag_pipes
);
625 /* And, finally, reset it to normal... */
626 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
630 static void rv530_emit_query_single(struct r300_context
*r300
,
631 struct r300_query
*query
)
636 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
637 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
638 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
639 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
643 static void rv530_emit_query_double(struct r300_context
*r300
,
644 struct r300_query
*query
)
649 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
650 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
651 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
652 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
653 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
654 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
655 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
659 void r300_emit_query_end(struct r300_context
* r300
)
661 struct r300_capabilities
*caps
= &r300
->screen
->caps
;
662 struct r300_query
*query
= r300
->query_current
;
667 if (query
->begin_emitted
== FALSE
)
670 if (caps
->family
== CHIP_FAMILY_RV530
) {
671 if (caps
->num_z_pipes
== 2)
672 rv530_emit_query_double(r300
, query
);
674 rv530_emit_query_single(r300
, query
);
676 r300_emit_query_finish(r300
, query
);
679 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
681 struct r300_rs_state
* rs
= (struct r300_rs_state
*)state
;
686 OUT_CS_REG(R300_VAP_CNTL_STATUS
, rs
->vap_control_status
);
688 OUT_CS_REG(R300_GB_AA_CONFIG
, rs
->antialiasing_config
);
690 OUT_CS_REG(R300_GA_POINT_SIZE
, rs
->point_size
);
691 OUT_CS_REG(R300_GA_LINE_CNTL
, rs
->line_control
);
693 if (rs
->polygon_offset_enable
) {
694 scale
= rs
->depth_scale
* 12;
695 offset
= rs
->depth_offset
;
697 switch (r300
->zbuffer_bpp
) {
706 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
713 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE
, 2);
714 OUT_CS(rs
->polygon_offset_enable
);
715 OUT_CS(rs
->cull_mode
);
716 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG
, rs
->line_stipple_config
);
717 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE
, rs
->line_stipple_value
);
718 OUT_CS_REG(R300_GA_POLY_MODE
, rs
->polygon_mode
);
719 OUT_CS_REG(R300_SC_CLIP_RULE
, rs
->clip_rule
);
720 OUT_CS_REG(R300_GB_ENABLE
, rs
->stuffing_enable
);
721 OUT_CS_REG_SEQ(R300_GA_POINT_S0
, 4);
722 OUT_CS_32F(rs
->point_texcoord_left
);
723 OUT_CS_32F(rs
->point_texcoord_bottom
);
724 OUT_CS_32F(rs
->point_texcoord_right
);
725 OUT_CS_32F(rs
->point_texcoord_top
);
729 void r300_emit_rs_block_state(struct r300_context
* r300
,
730 unsigned size
, void* state
)
732 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
734 /* It's the same for both INST and IP tables */
735 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
738 DBG(r300
, DBG_DRAW
, "r300: RS emit:\n");
741 if (r300
->screen
->caps
.is_r500
) {
742 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
744 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
746 for (i
= 0; i
< count
; i
++) {
748 DBG(r300
, DBG_DRAW
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
751 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
753 OUT_CS(rs
->inst_count
);
755 if (r300
->screen
->caps
.is_r500
) {
756 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
758 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
760 for (i
= 0; i
< count
; i
++) {
762 DBG(r300
, DBG_DRAW
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
765 DBG(r300
, DBG_DRAW
, " : count: 0x%08x inst_count: 0x%08x\n",
766 rs
->count
, rs
->inst_count
);
771 void r300_emit_scissor_state(struct r300_context
* r300
,
772 unsigned size
, void* state
)
774 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
778 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0
, 2);
779 if (r300
->screen
->caps
.is_r500
) {
780 OUT_CS((scissor
->minx
<< R300_CLIPRECT_X_SHIFT
) |
781 (scissor
->miny
<< R300_CLIPRECT_Y_SHIFT
));
782 OUT_CS(((scissor
->maxx
- 1) << R300_CLIPRECT_X_SHIFT
) |
783 ((scissor
->maxy
- 1) << R300_CLIPRECT_Y_SHIFT
));
785 OUT_CS(((scissor
->minx
+ 1440) << R300_CLIPRECT_X_SHIFT
) |
786 ((scissor
->miny
+ 1440) << R300_CLIPRECT_Y_SHIFT
));
787 OUT_CS(((scissor
->maxx
+ 1440-1) << R300_CLIPRECT_X_SHIFT
) |
788 ((scissor
->maxy
+ 1440-1) << R300_CLIPRECT_Y_SHIFT
));
793 void r300_emit_textures_state(struct r300_context
*r300
,
794 unsigned size
, void *state
)
796 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
797 struct r300_texture_sampler_state
*texstate
;
802 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
804 for (i
= 0; i
< allstate
->count
; i
++) {
805 if ((1 << i
) & allstate
->tx_enable
) {
806 texstate
= &allstate
->regs
[i
];
808 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter0
);
809 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter1
);
810 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
811 texstate
->border_color
);
813 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
.format0
);
814 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
.format1
);
815 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
.format2
);
817 OUT_CS_REG_SEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
818 OUT_CS_TEX_RELOC(r300_texture(allstate
->sampler_views
[i
]->base
.texture
),
819 texstate
->format
.tile_config
,
820 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0, 0);
826 void r300_emit_aos(struct r300_context
* r300
, unsigned offset
, boolean indexed
)
828 struct pipe_vertex_buffer
*vb1
, *vb2
, *vbuf
= r300
->vertex_buffer
;
829 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
831 unsigned size1
, size2
, aos_count
= r300
->velems
->count
;
832 unsigned packet_size
= (aos_count
* 3 + 1) / 2;
835 for (i
= 0; i
< aos_count
; i
++) {
836 if ((vbuf
[velem
[i
].vertex_buffer_index
].buffer_offset
+ velem
[i
].src_offset
) % 4 != 0) {
837 /* XXX We must align the buffer. */
839 fprintf(stderr
, "r300: Unaligned vertex buffer offsets aren't supported, aborting..\n");
844 BEGIN_CS(2 + packet_size
+ aos_count
* 2);
845 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
846 OUT_CS(aos_count
| (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
848 for (i
= 0; i
< aos_count
- 1; i
+= 2) {
849 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
850 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
851 size1
= util_format_get_blocksize(velem
[i
].src_format
);
852 size2
= util_format_get_blocksize(velem
[i
+1].src_format
);
854 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
855 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
856 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
857 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
861 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
862 size1
= util_format_get_blocksize(velem
[i
].src_format
);
864 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
865 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
868 for (i
= 0; i
< aos_count
; i
++) {
869 OUT_CS_BUF_RELOC_NO_OFFSET(vbuf
[velem
[i
].vertex_buffer_index
].buffer
,
870 RADEON_GEM_DOMAIN_GTT
, 0, 0);
875 void r300_emit_vertex_buffer(struct r300_context
* r300
)
879 DBG(r300
, DBG_DRAW
, "r300: Preparing vertex buffer %p for render, "
880 "vertex size %d\n", r300
->vbo
,
881 r300
->vertex_info
.size
);
882 /* Set the pointer to our vertex buffer. The emitted values are this:
883 * PACKET3 [3D_LOAD_VBPNTR]
885 * FORMAT [size | stride << 8]
886 * OFFSET [offset into BO]
887 * VBPNTR [relocated BO]
890 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
892 OUT_CS(r300
->vertex_info
.size
|
893 (r300
->vertex_info
.size
<< 8));
894 OUT_CS(r300
->vbo_offset
);
895 OUT_CS_BUF_RELOC(r300
->vbo
, 0, RADEON_GEM_DOMAIN_GTT
, 0, 0);
899 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
900 unsigned size
, void* state
)
902 struct r300_vertex_stream_state
*streams
=
903 (struct r300_vertex_stream_state
*)state
;
907 DBG(r300
, DBG_DRAW
, "r300: PSC emit:\n");
910 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
911 for (i
= 0; i
< streams
->count
; i
++) {
912 OUT_CS(streams
->vap_prog_stream_cntl
[i
]);
913 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl%d: 0x%08x\n", i
,
914 streams
->vap_prog_stream_cntl
[i
]);
916 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
917 for (i
= 0; i
< streams
->count
; i
++) {
918 OUT_CS(streams
->vap_prog_stream_cntl_ext
[i
]);
919 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
920 streams
->vap_prog_stream_cntl_ext
[i
]);
925 void r300_emit_vap_output_state(struct r300_context
* r300
,
926 unsigned size
, void* state
)
928 struct r300_vap_output_state
*vap_out_state
=
929 (struct r300_vap_output_state
*)state
;
932 DBG(r300
, DBG_DRAW
, "r300: VAP emit:\n");
935 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
936 OUT_CS(vap_out_state
->vap_vtx_state_cntl
);
937 OUT_CS(vap_out_state
->vap_vsm_vtx_assm
);
938 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
939 OUT_CS(vap_out_state
->vap_out_vtx_fmt
[0]);
940 OUT_CS(vap_out_state
->vap_out_vtx_fmt
[1]);
944 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
949 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
953 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
955 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
956 struct r300_vertex_program_code
* code
= &vs
->code
;
957 struct r300_screen
* r300screen
= r300
->screen
;
958 unsigned instruction_count
= code
->length
/ 4;
961 unsigned vtx_mem_size
= r300screen
->caps
.is_r500
? 128 : 72;
962 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
963 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
964 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
966 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
967 vtx_mem_size
/ output_count
, 10);
968 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 6);
970 unsigned imm_first
= vs
->externals_count
;
971 unsigned imm_end
= vs
->code
.constants
.Count
;
972 unsigned imm_count
= vs
->immediates_count
;
977 /* R300_VAP_PVS_CODE_CNTL_0
978 * R300_VAP_PVS_CONST_CNTL
979 * R300_VAP_PVS_CODE_CNTL_1
980 * See the r5xx docs for instructions on how to use these. */
981 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0
, 3);
982 OUT_CS(R300_PVS_FIRST_INST(0) |
983 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
984 R300_PVS_LAST_INST(instruction_count
- 1));
985 OUT_CS(R300_PVS_MAX_CONST_ADDR(code
->constants
.Count
- 1));
986 OUT_CS(instruction_count
- 1);
988 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
989 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
990 for (i
= 0; i
< code
->length
; i
++) {
991 OUT_CS(code
->body
.d
[i
]);
994 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
995 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
996 R300_PVS_NUM_FPUS(r300screen
->caps
.num_vert_fpus
) |
997 R300_PVS_VF_MAX_VTX_NUM(12) |
998 (r300screen
->caps
.is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
1000 /* Emit immediates. */
1002 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1003 (r300
->screen
->caps
.is_r500
?
1004 R500_PVS_CONST_START
: R300_PVS_CONST_START
) +
1006 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, imm_count
* 4);
1007 for (i
= imm_first
; i
< imm_end
; i
++) {
1008 const float *data
= vs
->code
.constants
.Constants
[i
].u
.Immediate
;
1009 OUT_CS_32F(data
[0]);
1010 OUT_CS_32F(data
[1]);
1011 OUT_CS_32F(data
[2]);
1012 OUT_CS_32F(data
[3]);
1018 void r300_emit_vs_constants(struct r300_context
* r300
,
1019 unsigned size
, void *state
)
1023 ((struct r300_vertex_shader
*)r300
->vs_state
.state
)->externals_count
;
1024 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
1031 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1032 (r300
->screen
->caps
.is_r500
?
1033 R500_PVS_CONST_START
: R300_PVS_CONST_START
));
1034 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, count
* 4);
1035 for (i
= 0; i
< count
; i
++) {
1036 const float *data
= buf
->constants
[i
];
1037 OUT_CS_32F(data
[0]);
1038 OUT_CS_32F(data
[1]);
1039 OUT_CS_32F(data
[2]);
1040 OUT_CS_32F(data
[3]);
1045 void r300_emit_viewport_state(struct r300_context
* r300
,
1046 unsigned size
, void* state
)
1048 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
1052 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
1053 OUT_CS_32F(viewport
->xscale
);
1054 OUT_CS_32F(viewport
->xoffset
);
1055 OUT_CS_32F(viewport
->yscale
);
1056 OUT_CS_32F(viewport
->yoffset
);
1057 OUT_CS_32F(viewport
->zscale
);
1058 OUT_CS_32F(viewport
->zoffset
);
1059 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
1063 void r300_emit_ztop_state(struct r300_context
* r300
,
1064 unsigned size
, void* state
)
1066 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
1070 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
1074 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
1079 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
1083 void r300_emit_buffer_validate(struct r300_context
*r300
,
1084 boolean do_validate_vertex_buffers
,
1085 struct pipe_resource
*index_buffer
)
1087 struct pipe_framebuffer_state
* fb
=
1088 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1089 struct r300_textures_state
*texstate
=
1090 (struct r300_textures_state
*)r300
->textures_state
.state
;
1091 struct r300_texture
* tex
;
1092 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
1093 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
1094 struct pipe_resource
*pbuf
;
1096 boolean invalid
= FALSE
;
1098 /* upload buffers first */
1099 if (r300
->any_user_vbs
) {
1100 r300_upload_user_buffers(r300
);
1101 r300
->any_user_vbs
= false;
1104 /* Clean out BOs. */
1105 r300
->rws
->reset_bos(r300
->rws
);
1108 /* Color buffers... */
1109 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1110 tex
= r300_texture(fb
->cbufs
[i
]->texture
);
1111 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
1112 if (!r300_add_texture(r300
->rws
, tex
,
1113 0, RADEON_GEM_DOMAIN_VRAM
)) {
1114 r300
->context
.flush(&r300
->context
, 0, NULL
);
1118 /* ...depth buffer... */
1120 tex
= r300_texture(fb
->zsbuf
->texture
);
1121 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
1122 if (!r300_add_texture(r300
->rws
, tex
,
1123 0, RADEON_GEM_DOMAIN_VRAM
)) {
1124 r300
->context
.flush(&r300
->context
, 0, NULL
);
1128 /* ...textures... */
1129 for (i
= 0; i
< texstate
->count
; i
++) {
1130 if (!(texstate
->tx_enable
& (1 << i
))) {
1134 tex
= r300_texture(texstate
->sampler_views
[i
]->base
.texture
);
1135 if (!r300_add_texture(r300
->rws
, tex
,
1136 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0)) {
1137 r300
->context
.flush(&r300
->context
, 0, NULL
);
1141 /* ...occlusion query buffer... */
1142 if (r300
->query_start
.dirty
) {
1143 if (!r300_add_buffer(r300
->rws
, r300
->oqbo
,
1144 0, RADEON_GEM_DOMAIN_GTT
)) {
1145 r300
->context
.flush(&r300
->context
, 0, NULL
);
1149 /* ...vertex buffer for SWTCL path... */
1151 if (!r300_add_buffer(r300
->rws
, r300
->vbo
,
1152 RADEON_GEM_DOMAIN_GTT
, 0)) {
1153 r300
->context
.flush(&r300
->context
, 0, NULL
);
1157 /* ...vertex buffers for HWTCL path... */
1158 if (do_validate_vertex_buffers
) {
1159 for (i
= 0; i
< r300
->velems
->count
; i
++) {
1160 pbuf
= vbuf
[velem
[i
].vertex_buffer_index
].buffer
;
1162 if (!r300_add_buffer(r300
->rws
, pbuf
,
1163 RADEON_GEM_DOMAIN_GTT
, 0)) {
1164 r300
->context
.flush(&r300
->context
, 0, NULL
);
1169 /* ...and index buffer for HWTCL path. */
1171 if (!r300_add_buffer(r300
->rws
, index_buffer
,
1172 RADEON_GEM_DOMAIN_GTT
, 0)) {
1173 r300
->context
.flush(&r300
->context
, 0, NULL
);
1177 if (!r300
->rws
->validate(r300
->rws
)) {
1178 r300
->context
.flush(&r300
->context
, 0, NULL
);
1181 fprintf(stderr
, "r300: Stuck in validation loop, gonna quit now.\n");
1189 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
1191 struct r300_atom
* atom
;
1192 unsigned dwords
= 0;
1194 foreach(atom
, &r300
->atom_list
) {
1196 dwords
+= atom
->size
;
1203 /* Emit all dirty state. */
1204 void r300_emit_dirty_state(struct r300_context
* r300
)
1206 struct r300_screen
* r300screen
= r300
->screen
;
1207 struct r300_atom
* atom
;
1209 foreach(atom
, &r300
->atom_list
) {
1211 atom
->emit(r300
, atom
->size
, atom
->state
);
1212 atom
->dirty
= FALSE
;
1216 /* Emit the VBO for SWTCL. */
1217 if (!r300screen
->caps
.has_tcl
) {
1218 r300_emit_vertex_buffer(r300
);