2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23 /* r300_emit: Functions for emitting state. */
25 #include "util/u_math.h"
27 #include "r300_context.h"
29 #include "r300_emit.h"
31 #include "r300_screen.h"
32 #include "r300_state_derived.h"
33 #include "r300_state_inlines.h"
34 #include "r300_texture.h"
37 void r300_emit_blend_state(struct r300_context
* r300
,
38 struct r300_blend_state
* blend
)
42 OUT_CS_REG_SEQ(R300_RB3D_CBLEND
, 3);
43 OUT_CS(blend
->blend_control
);
44 OUT_CS(blend
->alpha_blend_control
);
45 OUT_CS(blend
->color_channel_mask
);
46 OUT_CS_REG(R300_RB3D_ROPCNTL
, blend
->rop
);
47 OUT_CS_REG(R300_RB3D_DITHER_CTL
, blend
->dither
);
51 void r300_emit_blend_color_state(struct r300_context
* r300
,
52 struct r300_blend_color_state
* bc
)
54 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
57 if (r300screen
->caps
->is_r500
) {
59 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR
, 2);
60 OUT_CS(bc
->blend_color_red_alpha
);
61 OUT_CS(bc
->blend_color_green_blue
);
65 OUT_CS_REG(R300_RB3D_BLEND_COLOR
, bc
->blend_color
);
70 void r300_emit_clip_state(struct r300_context
* r300
,
71 struct pipe_clip_state
* clip
)
74 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
77 if (r300screen
->caps
->has_tcl
) {
78 BEGIN_CS(5 + (6 * 4));
79 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
80 (r300screen
->caps
->is_r500
?
81 R500_PVS_UCP_START
: R300_PVS_UCP_START
));
82 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, 6 * 4);
83 for (i
= 0; i
< 6; i
++) {
84 OUT_CS_32F(clip
->ucp
[i
][0]);
85 OUT_CS_32F(clip
->ucp
[i
][1]);
86 OUT_CS_32F(clip
->ucp
[i
][2]);
87 OUT_CS_32F(clip
->ucp
[i
][3]);
89 OUT_CS_REG(R300_VAP_CLIP_CNTL
, ((1 << clip
->nr
) - 1) |
90 R300_PS_UCP_MODE_CLIP_AS_TRIFAN
);
94 OUT_CS_REG(R300_VAP_CLIP_CNTL
, R300_CLIP_DISABLE
);
100 void r300_emit_dsa_state(struct r300_context
* r300
,
101 struct r300_dsa_state
* dsa
)
103 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
106 BEGIN_CS(r300screen
->caps
->is_r500
? 10 : 8);
107 OUT_CS_REG(R300_FG_ALPHA_FUNC
, dsa
->alpha_function
);
109 /* not needed since we use the 8bit alpha ref */
110 /*if (r300screen->caps->is_r500) {
111 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
114 OUT_CS_REG_SEQ(R300_ZB_CNTL
, 3);
115 OUT_CS(dsa
->z_buffer_control
);
116 OUT_CS(dsa
->z_stencil_control
);
117 OUT_CS(dsa
->stencil_ref_mask
);
118 OUT_CS_REG(R300_ZB_ZTOP
, r300
->ztop_state
.z_buffer_top
);
120 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
121 if (r300screen
->caps
->is_r500
) {
122 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF
, dsa
->stencil_ref_bf
);
127 static const float * get_shader_constant(
128 struct r300_context
* r300
,
129 struct rc_constant
* constant
,
130 struct r300_constant_buffer
* externals
)
132 static float vec
[4] = { 0.0, 0.0, 0.0, 1.0 };
133 struct pipe_texture
*tex
;
135 switch(constant
->Type
) {
136 case RC_CONSTANT_EXTERNAL
:
137 return externals
->constants
[constant
->u
.External
];
139 case RC_CONSTANT_IMMEDIATE
:
140 return constant
->u
.Immediate
;
142 case RC_CONSTANT_STATE
:
143 switch (constant
->u
.State
[0]) {
144 /* Factor for converting rectangle coords to
145 * normalized coords. Should only show up on non-r500. */
146 case RC_STATE_R300_TEXRECT_FACTOR
:
147 tex
= &r300
->textures
[constant
->u
.State
[1]]->tex
;
148 vec
[0] = 1.0 / tex
->width
[0];
149 vec
[1] = 1.0 / tex
->height
[0];
153 debug_printf("r300: Implementation error: "
154 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
159 debug_printf("r300: Implementation error: "
160 "Unhandled constant type %d\n", constant
->Type
);
163 /* This should either be (0, 0, 0, 1), which should be a relatively safe
164 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
169 /* Convert a normal single-precision float into the 7.16 format
170 * used by the R300 fragment shader.
172 static uint32_t pack_float24(float f
)
180 uint32_t float24
= 0;
187 mantissa
= frexpf(f
, &exponent
);
191 float24
|= (1 << 23);
192 mantissa
= mantissa
* -1.0;
194 /* Handle exponent, bias of 63 */
196 float24
|= (exponent
<< 16);
197 /* Kill 7 LSB of mantissa */
198 float24
|= (u
.u
& 0x7FFFFF) >> 7;
203 void r300_emit_fragment_program_code(struct r300_context
* r300
,
204 struct rX00_fragment_program_code
* generic_code
)
206 struct r300_fragment_program_code
* code
= &generic_code
->code
.r300
;
211 code
->alu
.length
* 4 +
212 (code
->tex
.length
? (1 + code
->tex
.length
) : 0));
214 OUT_CS_REG(R300_US_CONFIG
, code
->config
);
215 OUT_CS_REG(R300_US_PIXSIZE
, code
->pixsize
);
216 OUT_CS_REG(R300_US_CODE_OFFSET
, code
->code_offset
);
218 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0
, 4);
219 for(i
= 0; i
< 4; ++i
)
220 OUT_CS(code
->code_addr
[i
]);
222 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0
, code
->alu
.length
);
223 for (i
= 0; i
< code
->alu
.length
; i
++)
224 OUT_CS(code
->alu
.inst
[i
].rgb_inst
);
226 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0
, code
->alu
.length
);
227 for (i
= 0; i
< code
->alu
.length
; i
++)
228 OUT_CS(code
->alu
.inst
[i
].rgb_addr
);
230 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0
, code
->alu
.length
);
231 for (i
= 0; i
< code
->alu
.length
; i
++)
232 OUT_CS(code
->alu
.inst
[i
].alpha_inst
);
234 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0
, code
->alu
.length
);
235 for (i
= 0; i
< code
->alu
.length
; i
++)
236 OUT_CS(code
->alu
.inst
[i
].alpha_addr
);
238 if (code
->tex
.length
) {
239 OUT_CS_REG_SEQ(R300_US_TEX_INST_0
, code
->tex
.length
);
240 for(i
= 0; i
< code
->tex
.length
; ++i
)
241 OUT_CS(code
->tex
.inst
[i
]);
247 void r300_emit_fs_constant_buffer(struct r300_context
* r300
,
248 struct rc_constant_list
* constants
)
253 if (constants
->Count
== 0)
256 BEGIN_CS(constants
->Count
* 4 + 1);
257 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, constants
->Count
* 4);
258 for(i
= 0; i
< constants
->Count
; ++i
) {
259 const float * data
= get_shader_constant(r300
,
260 &constants
->Constants
[i
],
261 &r300
->shader_constants
[PIPE_SHADER_FRAGMENT
]);
262 OUT_CS(pack_float24(data
[0]));
263 OUT_CS(pack_float24(data
[1]));
264 OUT_CS(pack_float24(data
[2]));
265 OUT_CS(pack_float24(data
[3]));
270 void r500_emit_fragment_program_code(struct r300_context
* r300
,
271 struct rX00_fragment_program_code
* generic_code
)
273 struct r500_fragment_program_code
* code
= &generic_code
->code
.r500
;
278 ((code
->inst_end
+ 1) * 6));
279 OUT_CS_REG(R500_US_CONFIG
, 0);
280 OUT_CS_REG(R500_US_PIXSIZE
, code
->max_temp_idx
);
281 OUT_CS_REG(R500_US_CODE_RANGE
,
282 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code
->inst_end
));
283 OUT_CS_REG(R500_US_CODE_OFFSET
, 0);
284 OUT_CS_REG(R500_US_CODE_ADDR
,
285 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code
->inst_end
));
287 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_INSTR
);
288 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, (code
->inst_end
+ 1) * 6);
289 for (i
= 0; i
<= code
->inst_end
; i
++) {
290 OUT_CS(code
->inst
[i
].inst0
);
291 OUT_CS(code
->inst
[i
].inst1
);
292 OUT_CS(code
->inst
[i
].inst2
);
293 OUT_CS(code
->inst
[i
].inst3
);
294 OUT_CS(code
->inst
[i
].inst4
);
295 OUT_CS(code
->inst
[i
].inst5
);
301 void r500_emit_fs_constant_buffer(struct r300_context
* r300
,
302 struct rc_constant_list
* constants
)
307 if (constants
->Count
== 0)
310 BEGIN_CS(constants
->Count
* 4 + 3);
311 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
312 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, constants
->Count
* 4);
313 for (i
= 0; i
< constants
->Count
; i
++) {
314 const float * data
= get_shader_constant(r300
,
315 &constants
->Constants
[i
],
316 &r300
->shader_constants
[PIPE_SHADER_FRAGMENT
]);
325 void r300_emit_fb_state(struct r300_context
* r300
,
326 struct pipe_framebuffer_state
* fb
)
328 struct r300_texture
* tex
;
329 struct pipe_surface
* surf
;
333 BEGIN_CS((10 * fb
->nr_cbufs
) + (fb
->zsbuf
? 10 : 0) + 4);
334 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT
,
335 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS
|
336 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
337 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
,
338 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
339 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);
341 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
343 tex
= (struct r300_texture
*)surf
->texture
;
344 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
346 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
+ (4 * i
), 1);
347 OUT_CS_RELOC(tex
->buffer
, surf
->offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
349 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0
+ (4 * i
), 1);
350 OUT_CS_RELOC(tex
->buffer
, tex
->pitch
[surf
->level
] |
351 r300_translate_colorformat(tex
->tex
.format
), 0,
352 RADEON_GEM_DOMAIN_VRAM
, 0);
354 OUT_CS_REG(R300_US_OUT_FMT_0
+ (4 * i
),
355 r300_translate_out_fmt(surf
->format
));
360 tex
= (struct r300_texture
*)surf
->texture
;
361 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
363 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
364 OUT_CS_RELOC(tex
->buffer
, surf
->offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
366 OUT_CS_REG(R300_ZB_FORMAT
, r300_translate_zsformat(tex
->tex
.format
));
368 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
369 OUT_CS_RELOC(tex
->buffer
, tex
->pitch
[surf
->level
], 0,
370 RADEON_GEM_DOMAIN_VRAM
, 0);
376 static void r300_emit_query_start(struct r300_context
*r300
)
378 struct r300_capabilities
*caps
= r300_screen(r300
->context
.screen
)->caps
;
379 struct r300_query
*query
= r300
->query_current
;
385 /* XXX This will almost certainly not return good results
386 * for overlapping queries. */
388 if (caps
->family
== CHIP_FAMILY_RV530
) {
389 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
391 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
393 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
395 query
->begin_emitted
= TRUE
;
399 static void r300_emit_query_finish(struct r300_context
*r300
,
400 struct r300_query
*query
)
402 struct r300_capabilities
* caps
= r300_screen(r300
->context
.screen
)->caps
;
405 assert(caps
->num_frag_pipes
);
407 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
408 /* I'm not so sure I like this switch, but it's hard to be elegant
409 * when there's so many special cases...
411 * So here's the basic idea. For each pipe, enable writes to it only,
412 * then put out the relocation for ZPASS_ADDR, taking into account a
413 * 4-byte offset for each pipe. RV380 and older are special; they have
414 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
415 * so there's a chipset cap for that. */
416 switch (caps
->num_frag_pipes
) {
419 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
420 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
421 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 3),
422 0, RADEON_GEM_DOMAIN_GTT
, 0);
425 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
426 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
427 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 2),
428 0, RADEON_GEM_DOMAIN_GTT
, 0);
431 /* As mentioned above, accomodate RV380 and older. */
432 OUT_CS_REG(R300_SU_REG_DEST
,
433 1 << (caps
->high_second_pipe
? 3 : 1));
434 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
435 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 1),
436 0, RADEON_GEM_DOMAIN_GTT
, 0);
439 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
440 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
441 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 0),
442 0, RADEON_GEM_DOMAIN_GTT
, 0);
445 debug_printf("r300: Implementation error: Chipset reports %d"
446 " pixel pipes!\n", caps
->num_frag_pipes
);
450 /* And, finally, reset it to normal... */
451 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
455 static void rv530_emit_query_single(struct r300_context
*r300
,
456 struct r300_query
*query
)
461 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
462 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
463 OUT_CS_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
464 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
468 static void rv530_emit_query_double(struct r300_context
*r300
,
469 struct r300_query
*query
)
474 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
475 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
476 OUT_CS_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
477 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
478 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
479 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
480 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
484 void r300_emit_query_end(struct r300_context
* r300
)
486 struct r300_capabilities
*caps
= r300_screen(r300
->context
.screen
)->caps
;
487 struct r300_query
*query
= r300
->query_current
;
492 if (query
->begin_emitted
== FALSE
)
495 if (caps
->family
== CHIP_FAMILY_RV530
) {
496 if (caps
->num_z_pipes
== 2)
497 rv530_emit_query_double(r300
, query
);
499 rv530_emit_query_single(r300
, query
);
501 r300_emit_query_finish(r300
, query
);
504 void r300_emit_rs_state(struct r300_context
* r300
, struct r300_rs_state
* rs
)
509 OUT_CS_REG(R300_VAP_CNTL_STATUS
, rs
->vap_control_status
);
510 OUT_CS_REG(R300_GA_POINT_SIZE
, rs
->point_size
);
511 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX
, 2);
512 OUT_CS(rs
->point_minmax
);
513 OUT_CS(rs
->line_control
);
514 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE
, 6);
515 OUT_CS(rs
->depth_scale_front
);
516 OUT_CS(rs
->depth_offset_front
);
517 OUT_CS(rs
->depth_scale_back
);
518 OUT_CS(rs
->depth_offset_back
);
519 OUT_CS(rs
->polygon_offset_enable
);
520 OUT_CS(rs
->cull_mode
);
521 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG
, rs
->line_stipple_config
);
522 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE
, rs
->line_stipple_value
);
523 OUT_CS_REG(R300_GA_COLOR_CONTROL
, rs
->color_control
);
524 OUT_CS_REG(R300_GA_POLY_MODE
, rs
->polygon_mode
);
528 void r300_emit_rs_block_state(struct r300_context
* r300
,
529 struct r300_rs_block
* rs
)
532 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
535 DBG(r300
, DBG_DRAW
, "r300: RS emit:\n");
538 if (r300screen
->caps
->is_r500
) {
539 OUT_CS_REG_SEQ(R500_RS_IP_0
, 8);
541 OUT_CS_REG_SEQ(R300_RS_IP_0
, 8);
543 for (i
= 0; i
< 8; i
++) {
545 DBG(r300
, DBG_DRAW
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
548 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
550 OUT_CS(rs
->inst_count
);
552 if (r300screen
->caps
->is_r500
) {
553 OUT_CS_REG_SEQ(R500_RS_INST_0
, 8);
555 OUT_CS_REG_SEQ(R300_RS_INST_0
, 8);
557 for (i
= 0; i
< 8; i
++) {
559 DBG(r300
, DBG_DRAW
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
562 DBG(r300
, DBG_DRAW
, " : count: 0x%08x inst_count: 0x%08x\n",
563 rs
->count
, rs
->inst_count
);
568 void r300_emit_scissor_state(struct r300_context
* r300
,
569 struct r300_scissor_state
* scissor
)
574 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
575 OUT_CS(scissor
->scissor_top_left
);
576 OUT_CS(scissor
->scissor_bottom_right
);
580 void r300_emit_texture(struct r300_context
* r300
,
581 struct r300_sampler_state
* sampler
,
582 struct r300_texture
* tex
,
585 uint32_t filter0
= sampler
->filter0
;
586 uint32_t format0
= tex
->state
.format0
;
587 unsigned min_level
, max_level
;
590 /* to emulate 1D textures through 2D ones correctly */
591 if (tex
->tex
.target
== PIPE_TEXTURE_1D
) {
592 filter0
&= ~R300_TX_WRAP_T_MASK
;
593 filter0
|= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE
);
596 /* determine min/max levels */
597 /* the MAX_MIP level is the largest (finest) one */
598 max_level
= MIN2(sampler
->max_lod
, tex
->tex
.last_level
);
599 min_level
= MIN2(sampler
->min_lod
, max_level
);
600 format0
|= R300_TX_NUM_LEVELS(max_level
);
601 filter0
|= R300_TX_MAX_MIP_LEVEL(min_level
);
604 OUT_CS_REG(R300_TX_FILTER0_0
+ (offset
* 4), filter0
|
606 OUT_CS_REG(R300_TX_FILTER1_0
+ (offset
* 4), sampler
->filter1
);
607 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (offset
* 4), sampler
->border_color
);
609 OUT_CS_REG(R300_TX_FORMAT0_0
+ (offset
* 4), format0
);
610 OUT_CS_REG(R300_TX_FORMAT1_0
+ (offset
* 4), tex
->state
.format1
);
611 OUT_CS_REG(R300_TX_FORMAT2_0
+ (offset
* 4), tex
->state
.format2
);
612 OUT_CS_REG_SEQ(R300_TX_OFFSET_0
+ (offset
* 4), 1);
613 OUT_CS_RELOC(tex
->buffer
, 0,
614 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0, 0);
618 /* XXX I can't read this and that's not good */
619 void r300_emit_aos(struct r300_context
* r300
, unsigned offset
)
621 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
622 struct pipe_vertex_element
*velem
= r300
->vertex_element
;
625 unsigned aos_count
= r300
->vertex_element_count
;
627 unsigned packet_size
= (aos_count
* 3 + 1) / 2;
628 BEGIN_CS(2 + packet_size
+ aos_count
* 2);
629 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
631 for (i
= 0; i
< aos_count
- 1; i
+= 2) {
632 int buf_num1
= velem
[i
].vertex_buffer_index
;
633 int buf_num2
= velem
[i
+1].vertex_buffer_index
;
634 assert(vbuf
[buf_num1
].stride
% 4 == 0 && pf_get_size(velem
[i
].src_format
) % 4 == 0);
635 assert(vbuf
[buf_num2
].stride
% 4 == 0 && pf_get_size(velem
[i
+1].src_format
) % 4 == 0);
636 OUT_CS((pf_get_size(velem
[i
].src_format
) >> 2) | (vbuf
[buf_num1
].stride
<< 6) |
637 (pf_get_size(velem
[i
+1].src_format
) << 14) | (vbuf
[buf_num2
].stride
<< 22));
638 OUT_CS(vbuf
[buf_num1
].buffer_offset
+ velem
[i
].src_offset
+
639 offset
* vbuf
[buf_num1
].stride
);
640 OUT_CS(vbuf
[buf_num2
].buffer_offset
+ velem
[i
+1].src_offset
+
641 offset
* vbuf
[buf_num2
].stride
);
644 int buf_num
= velem
[i
].vertex_buffer_index
;
645 assert(vbuf
[buf_num
].stride
% 4 == 0 && pf_get_size(velem
[i
].src_format
) % 4 == 0);
646 OUT_CS((pf_get_size(velem
[i
].src_format
) >> 2) | (vbuf
[buf_num
].stride
<< 6));
647 OUT_CS(vbuf
[buf_num
].buffer_offset
+ velem
[i
].src_offset
+
648 offset
* vbuf
[buf_num
].stride
);
651 /* XXX bare CS reloc */
652 for (i
= 0; i
< aos_count
; i
++) {
653 cs_winsys
->write_cs_reloc(cs_winsys
,
654 vbuf
[velem
[i
].vertex_buffer_index
].buffer
,
655 RADEON_GEM_DOMAIN_GTT
,
663 void r300_emit_draw_packet(struct r300_context
* r300
)
667 DBG(r300
, DBG_DRAW
, "r300: Preparing vertex buffer %p for render, "
668 "vertex size %d\n", r300
->vbo
,
669 r300
->vertex_info
->vinfo
.size
);
670 /* Set the pointer to our vertex buffer. The emitted values are this:
671 * PACKET3 [3D_LOAD_VBPNTR]
673 * FORMAT [size | stride << 8]
674 * OFFSET [offset into BO]
675 * VBPNTR [relocated BO]
678 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
680 OUT_CS(r300
->vertex_info
->vinfo
.size
|
681 (r300
->vertex_info
->vinfo
.size
<< 8));
682 OUT_CS(r300
->vbo_offset
);
683 OUT_CS_RELOC(r300
->vbo
, 0, RADEON_GEM_DOMAIN_GTT
, 0, 0);
688 void r300_emit_vertex_format_state(struct r300_context
* r300
)
693 DBG(r300
, DBG_DRAW
, "r300: VAP/PSC emit:\n");
696 OUT_CS_REG(R300_VAP_VTX_SIZE
, r300
->vertex_info
->vinfo
.size
);
698 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
699 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[0]);
700 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[1]);
701 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
702 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[2]);
703 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[3]);
704 for (i
= 0; i
< 4; i
++) {
705 DBG(r300
, DBG_DRAW
, " : hwfmt%d: 0x%08x\n", i
,
706 r300
->vertex_info
->vinfo
.hwfmt
[i
]);
709 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, 8);
710 for (i
= 0; i
< 8; i
++) {
711 OUT_CS(r300
->vertex_info
->vap_prog_stream_cntl
[i
]);
712 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl%d: 0x%08x\n", i
,
713 r300
->vertex_info
->vap_prog_stream_cntl
[i
]);
715 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, 8);
716 for (i
= 0; i
< 8; i
++) {
717 OUT_CS(r300
->vertex_info
->vap_prog_stream_cntl_ext
[i
]);
718 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
719 r300
->vertex_info
->vap_prog_stream_cntl_ext
[i
]);
724 /* XXX This should go to util ... */
725 /* Return the number of bits set in the given number. */
726 static unsigned bitcount(unsigned n
)
740 void r300_emit_vertex_program_code(struct r300_context
* r300
,
741 struct r300_vertex_program_code
* code
)
744 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
745 unsigned instruction_count
= code
->length
/ 4;
747 int vtx_mem_size
= r300screen
->caps
->is_r500
? 128 : 72;
748 int input_count
= MAX2(bitcount(code
->InputsRead
), 1);
749 int output_count
= MAX2(bitcount(code
->OutputsWritten
), 1);
750 int temp_count
= MAX2(code
->num_temporaries
, 1);
751 int pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
752 vtx_mem_size
/ output_count
, 10);
753 int pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 6);
757 if (!r300screen
->caps
->has_tcl
) {
758 debug_printf("r300: Implementation error: emit_vertex_shader called,"
759 " but has_tcl is FALSE!\n");
763 BEGIN_CS(9 + code
->length
);
764 /* R300_VAP_PVS_CODE_CNTL_0
765 * R300_VAP_PVS_CONST_CNTL
766 * R300_VAP_PVS_CODE_CNTL_1
767 * See the r5xx docs for instructions on how to use these. */
768 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0
, 3);
769 OUT_CS(R300_PVS_FIRST_INST(0) |
770 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
771 R300_PVS_LAST_INST(instruction_count
- 1));
772 OUT_CS(R300_PVS_MAX_CONST_ADDR(code
->constants
.Count
- 1));
773 OUT_CS(instruction_count
- 1);
775 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
776 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
777 for (i
= 0; i
< code
->length
; i
++)
778 OUT_CS(code
->body
.d
[i
]);
780 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
781 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
782 R300_PVS_NUM_FPUS(r300screen
->caps
->num_vert_fpus
) |
783 R300_PVS_VF_MAX_VTX_NUM(12) |
784 (r300screen
->caps
->is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
788 void r300_emit_vertex_shader(struct r300_context
* r300
,
789 struct r300_vertex_shader
* vs
)
791 r300_emit_vertex_program_code(r300
, &vs
->code
);
794 void r300_emit_vs_constant_buffer(struct r300_context
* r300
,
795 struct rc_constant_list
* constants
)
798 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
801 if (!r300screen
->caps
->has_tcl
) {
802 debug_printf("r300: Implementation error: emit_vertex_shader called,"
803 " but has_tcl is FALSE!\n");
807 if (constants
->Count
== 0)
810 BEGIN_CS(constants
->Count
* 4 + 3);
811 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
812 (r300screen
->caps
->is_r500
?
813 R500_PVS_CONST_START
: R300_PVS_CONST_START
));
814 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, constants
->Count
* 4);
815 for (i
= 0; i
< constants
->Count
; i
++) {
816 const float * data
= get_shader_constant(r300
,
817 &constants
->Constants
[i
],
818 &r300
->shader_constants
[PIPE_SHADER_VERTEX
]);
827 void r300_emit_viewport_state(struct r300_context
* r300
,
828 struct r300_viewport_state
* viewport
)
833 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
834 OUT_CS_32F(viewport
->xscale
);
835 OUT_CS_32F(viewport
->xoffset
);
836 OUT_CS_32F(viewport
->yscale
);
837 OUT_CS_32F(viewport
->yoffset
);
838 OUT_CS_32F(viewport
->zscale
);
839 OUT_CS_32F(viewport
->zoffset
);
841 if (r300
->rs_state
->enable_vte
) {
842 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
844 OUT_CS_REG(R300_VAP_VTE_CNTL
, 0);
849 void r300_emit_texture_count(struct r300_context
* r300
)
854 OUT_CS_REG(R300_TX_ENABLE
, (1 << r300
->texture_count
) - 1);
859 void r300_flush_textures(struct r300_context
* r300
)
864 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
868 static void r300_flush_pvs(struct r300_context
* r300
)
873 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
877 /* Emit all dirty state. */
878 void r300_emit_dirty_state(struct r300_context
* r300
)
880 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
881 struct r300_texture
* tex
;
882 int i
, dirty_tex
= 0;
883 boolean invalid
= FALSE
;
885 if (!(r300
->dirty_state
)) {
890 r300
->winsys
->reset_bos(r300
->winsys
);
894 /* Color buffers... */
895 for (i
= 0; i
< r300
->framebuffer_state
.nr_cbufs
; i
++) {
896 tex
= (struct r300_texture
*)r300
->framebuffer_state
.cbufs
[i
]->texture
;
897 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
898 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
899 0, RADEON_GEM_DOMAIN_VRAM
)) {
900 r300
->context
.flush(&r300
->context
, 0, NULL
);
904 /* ...depth buffer... */
905 if (r300
->framebuffer_state
.zsbuf
) {
906 tex
= (struct r300_texture
*)r300
->framebuffer_state
.zsbuf
->texture
;
907 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
908 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
909 0, RADEON_GEM_DOMAIN_VRAM
)) {
910 r300
->context
.flush(&r300
->context
, 0, NULL
);
915 for (i
= 0; i
< r300
->texture_count
; i
++) {
916 tex
= r300
->textures
[i
];
919 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
920 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0)) {
921 r300
->context
.flush(&r300
->context
, 0, NULL
);
925 /* ...occlusion query buffer... */
926 if (!r300
->winsys
->add_buffer(r300
->winsys
, r300
->oqbo
,
927 0, RADEON_GEM_DOMAIN_GTT
)) {
928 r300
->context
.flush(&r300
->context
, 0, NULL
);
931 /* ...and vertex buffer. */
933 if (!r300
->winsys
->add_buffer(r300
->winsys
, r300
->vbo
,
934 RADEON_GEM_DOMAIN_GTT
, 0)) {
935 r300
->context
.flush(&r300
->context
, 0, NULL
);
939 // debug_printf("No VBO while emitting dirty state!\n");
941 if (!r300
->winsys
->validate(r300
->winsys
)) {
942 r300
->context
.flush(&r300
->context
, 0, NULL
);
945 debug_printf("r300: Stuck in validation loop, gonna quit now.");
952 if (r300
->dirty_state
& R300_NEW_QUERY
) {
953 r300_emit_query_start(r300
);
954 r300
->dirty_state
&= ~R300_NEW_QUERY
;
957 if (r300
->dirty_state
& R300_NEW_BLEND
) {
958 r300_emit_blend_state(r300
, r300
->blend_state
);
959 r300
->dirty_state
&= ~R300_NEW_BLEND
;
962 if (r300
->dirty_state
& R300_NEW_BLEND_COLOR
) {
963 r300_emit_blend_color_state(r300
, r300
->blend_color_state
);
964 r300
->dirty_state
&= ~R300_NEW_BLEND_COLOR
;
967 if (r300
->dirty_state
& R300_NEW_CLIP
) {
968 r300_emit_clip_state(r300
, &r300
->clip_state
);
969 r300
->dirty_state
&= ~R300_NEW_CLIP
;
972 if (r300
->dirty_state
& R300_NEW_DSA
) {
973 r300_emit_dsa_state(r300
, r300
->dsa_state
);
974 r300
->dirty_state
&= ~R300_NEW_DSA
;
977 if (r300
->dirty_state
& R300_NEW_FRAGMENT_SHADER
) {
978 if (r300screen
->caps
->is_r500
) {
979 r500_emit_fragment_program_code(r300
, &r300
->fs
->code
);
981 r300_emit_fragment_program_code(r300
, &r300
->fs
->code
);
983 r300
->dirty_state
&= ~R300_NEW_FRAGMENT_SHADER
;
986 if (r300
->dirty_state
& R300_NEW_FRAGMENT_SHADER_CONSTANTS
) {
987 if (r300screen
->caps
->is_r500
) {
988 r500_emit_fs_constant_buffer(r300
, &r300
->fs
->code
.constants
);
990 r300_emit_fs_constant_buffer(r300
, &r300
->fs
->code
.constants
);
992 r300
->dirty_state
&= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS
;
995 if (r300
->dirty_state
& R300_NEW_FRAMEBUFFERS
) {
996 r300_emit_fb_state(r300
, &r300
->framebuffer_state
);
997 r300
->dirty_state
&= ~R300_NEW_FRAMEBUFFERS
;
1000 if (r300
->dirty_state
& R300_NEW_RASTERIZER
) {
1001 r300_emit_rs_state(r300
, r300
->rs_state
);
1002 r300
->dirty_state
&= ~R300_NEW_RASTERIZER
;
1005 if (r300
->dirty_state
& R300_NEW_RS_BLOCK
) {
1006 r300_emit_rs_block_state(r300
, r300
->rs_block
);
1007 r300
->dirty_state
&= ~R300_NEW_RS_BLOCK
;
1010 if (r300
->dirty_state
& R300_NEW_SCISSOR
) {
1011 r300_emit_scissor_state(r300
, r300
->scissor_state
);
1012 r300
->dirty_state
&= ~R300_NEW_SCISSOR
;
1015 /* Samplers and textures are tracked separately but emitted together. */
1016 if (r300
->dirty_state
&
1017 (R300_ANY_NEW_SAMPLERS
| R300_ANY_NEW_TEXTURES
)) {
1018 r300_emit_texture_count(r300
);
1020 for (i
= 0; i
< MIN2(r300
->sampler_count
, r300
->texture_count
); i
++) {
1021 if (r300
->dirty_state
&
1022 ((R300_NEW_SAMPLER
<< i
) | (R300_NEW_TEXTURE
<< i
))) {
1023 if (r300
->textures
[i
])
1024 r300_emit_texture(r300
,
1025 r300
->sampler_states
[i
],
1028 r300
->dirty_state
&=
1029 ~((R300_NEW_SAMPLER
<< i
) | (R300_NEW_TEXTURE
<< i
));
1033 r300
->dirty_state
&= ~(R300_ANY_NEW_SAMPLERS
| R300_ANY_NEW_TEXTURES
);
1036 if (r300
->dirty_state
& R300_NEW_VIEWPORT
) {
1037 r300_emit_viewport_state(r300
, r300
->viewport_state
);
1038 r300
->dirty_state
&= ~R300_NEW_VIEWPORT
;
1042 r300_flush_textures(r300
);
1045 if (r300
->dirty_state
& R300_NEW_VERTEX_FORMAT
) {
1046 r300_emit_vertex_format_state(r300
);
1047 r300
->dirty_state
&= ~R300_NEW_VERTEX_FORMAT
;
1050 if (r300
->dirty_state
& (R300_NEW_VERTEX_SHADER
| R300_NEW_VERTEX_SHADER_CONSTANTS
)) {
1051 r300_flush_pvs(r300
);
1054 if (r300
->dirty_state
& R300_NEW_VERTEX_SHADER
) {
1055 r300_emit_vertex_shader(r300
, r300
->vs
);
1056 r300
->dirty_state
&= ~R300_NEW_VERTEX_SHADER
;
1059 if (r300
->dirty_state
& R300_NEW_VERTEX_SHADER_CONSTANTS
) {
1060 r300_emit_vs_constant_buffer(r300
, &r300
->vs
->code
.constants
);
1061 r300
->dirty_state
&= ~R300_NEW_VERTEX_SHADER_CONSTANTS
;
1065 assert(r300->dirty_state == 0);
1068 /* Finally, emit the VBO. */
1069 //r300_emit_vertex_buffer(r300);