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[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300,
39 unsigned size, void* state)
40 {
41 struct r300_blend_state* blend = (struct r300_blend_state*)state;
42 struct pipe_framebuffer_state* fb =
43 (struct pipe_framebuffer_state*)r300->fb_state.state;
44 CS_LOCALS(r300);
45
46 BEGIN_CS(size);
47 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
48 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
49 if (fb->nr_cbufs) {
50 OUT_CS(blend->blend_control);
51 OUT_CS(blend->alpha_blend_control);
52 OUT_CS(blend->color_channel_mask);
53 } else {
54 OUT_CS(0);
55 OUT_CS(0);
56 OUT_CS(0);
57 /* XXX also disable fastfill here once it's supported */
58 }
59 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
60 END_CS;
61 }
62
63 void r300_emit_blend_color_state(struct r300_context* r300,
64 unsigned size, void* state)
65 {
66 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
67 CS_LOCALS(r300);
68
69 if (r300->screen->caps.is_r500) {
70 BEGIN_CS(size);
71 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
72 OUT_CS(bc->blend_color_red_alpha);
73 OUT_CS(bc->blend_color_green_blue);
74 END_CS;
75 } else {
76 BEGIN_CS(size);
77 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
78 END_CS;
79 }
80 }
81
82 void r300_emit_clip_state(struct r300_context* r300,
83 unsigned size, void* state)
84 {
85 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
86 int i;
87 CS_LOCALS(r300);
88
89 if (r300->screen->caps.has_tcl) {
90 BEGIN_CS(size);
91 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
92 (r300->screen->caps.is_r500 ?
93 R500_PVS_UCP_START : R300_PVS_UCP_START));
94 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
95 for (i = 0; i < 6; i++) {
96 OUT_CS_32F(clip->ucp[i][0]);
97 OUT_CS_32F(clip->ucp[i][1]);
98 OUT_CS_32F(clip->ucp[i][2]);
99 OUT_CS_32F(clip->ucp[i][3]);
100 }
101 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
102 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
103 END_CS;
104 } else {
105 BEGIN_CS(size);
106 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
107 END_CS;
108 }
109
110 }
111
112 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
113 {
114 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
115 struct pipe_framebuffer_state* fb =
116 (struct pipe_framebuffer_state*)r300->fb_state.state;
117 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
118 CS_LOCALS(r300);
119
120 BEGIN_CS(size);
121 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
122 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
123
124 if (fb->zsbuf) {
125 OUT_CS(dsa->z_buffer_control);
126 OUT_CS(dsa->z_stencil_control);
127 } else {
128 OUT_CS(0);
129 OUT_CS(0);
130 }
131
132 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
133
134 if (r300->screen->caps.is_r500) {
135 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
136 }
137 END_CS;
138 }
139
140 static const float * get_shader_constant(
141 struct r300_context * r300,
142 struct rc_constant * constant,
143 struct r300_constant_buffer * externals)
144 {
145 struct r300_viewport_state* viewport = r300->viewport_state.state;
146 struct r300_textures_state* texstate = r300->textures_state.state;
147 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
148 struct pipe_resource *tex;
149
150 switch(constant->Type) {
151 case RC_CONSTANT_EXTERNAL:
152 return externals->constants[constant->u.External];
153
154 case RC_CONSTANT_IMMEDIATE:
155 return constant->u.Immediate;
156
157 case RC_CONSTANT_STATE:
158 switch (constant->u.State[0]) {
159 /* Factor for converting rectangle coords to
160 * normalized coords. Should only show up on non-r500. */
161 case RC_STATE_R300_TEXRECT_FACTOR:
162 tex = texstate->sampler_views[constant->u.State[1]]->base.texture;
163 vec[0] = 1.0 / tex->width0;
164 vec[1] = 1.0 / tex->height0;
165 break;
166
167 /* Texture compare-fail value. Shouldn't ever show up, but if
168 * it does, we'll be ready. */
169 case RC_STATE_SHADOW_AMBIENT:
170 vec[3] = 0;
171 break;
172
173 case RC_STATE_R300_VIEWPORT_SCALE:
174 vec[0] = viewport->xscale;
175 vec[1] = viewport->yscale;
176 vec[2] = viewport->zscale;
177 break;
178
179 case RC_STATE_R300_VIEWPORT_OFFSET:
180 vec[0] = viewport->xoffset;
181 vec[1] = viewport->yoffset;
182 vec[2] = viewport->zoffset;
183 break;
184
185 default:
186 fprintf(stderr, "r300: Implementation error: "
187 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
188 }
189 break;
190
191 default:
192 fprintf(stderr, "r300: Implementation error: "
193 "Unhandled constant type %d\n", constant->Type);
194 }
195
196 /* This should either be (0, 0, 0, 1), which should be a relatively safe
197 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
198 * state factors. */
199 return vec;
200 }
201
202 /* Convert a normal single-precision float into the 7.16 format
203 * used by the R300 fragment shader.
204 */
205 static uint32_t pack_float24(float f)
206 {
207 union {
208 float fl;
209 uint32_t u;
210 } u;
211 float mantissa;
212 int exponent;
213 uint32_t float24 = 0;
214
215 if (f == 0.0)
216 return 0;
217
218 u.fl = f;
219
220 mantissa = frexpf(f, &exponent);
221
222 /* Handle -ve */
223 if (mantissa < 0) {
224 float24 |= (1 << 23);
225 mantissa = mantissa * -1.0;
226 }
227 /* Handle exponent, bias of 63 */
228 exponent += 62;
229 float24 |= (exponent << 16);
230 /* Kill 7 LSB of mantissa */
231 float24 |= (u.u & 0x7FFFFF) >> 7;
232
233 return float24;
234 }
235
236 unsigned r300_get_fs_atom_size(struct r300_context *r300)
237 {
238 struct r300_fragment_shader *fs = r300_fs(r300);
239 unsigned imm_count = fs->shader->immediates_count;
240 struct r300_fragment_program_code *code = &fs->shader->code.code.r300;
241
242 return 19 +
243 code->alu.length * 4 +
244 (code->tex.length ? (1 + code->tex.length) : 0) +
245 (imm_count ? imm_count * 5 : 0);
246 }
247
248 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
249 {
250 struct r300_fragment_shader *fs = r300_fs(r300);
251 struct rX00_fragment_program_code* generic_code = &fs->shader->code;
252 struct r300_fragment_program_code * code = &generic_code->code.r300;
253 unsigned i;
254 unsigned imm_count = fs->shader->immediates_count;
255 unsigned imm_first = fs->shader->externals_count;
256 unsigned imm_end = generic_code->constants.Count;
257 struct rc_constant *constants = generic_code->constants.Constants;
258 CS_LOCALS(r300);
259
260 BEGIN_CS(size);
261 OUT_CS_REG(R300_US_CONFIG, code->config);
262 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
263 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
264
265 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
266 for(i = 0; i < 4; ++i)
267 OUT_CS(code->code_addr[i]);
268
269 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
270 for (i = 0; i < code->alu.length; i++)
271 OUT_CS(code->alu.inst[i].rgb_inst);
272
273 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
274 for (i = 0; i < code->alu.length; i++)
275 OUT_CS(code->alu.inst[i].rgb_addr);
276
277 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
278 for (i = 0; i < code->alu.length; i++)
279 OUT_CS(code->alu.inst[i].alpha_inst);
280
281 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
282 for (i = 0; i < code->alu.length; i++)
283 OUT_CS(code->alu.inst[i].alpha_addr);
284
285 if (code->tex.length) {
286 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
287 for(i = 0; i < code->tex.length; ++i)
288 OUT_CS(code->tex.inst[i]);
289 }
290
291 /* Emit immediates. */
292 if (imm_count) {
293 for(i = imm_first; i < imm_end; ++i) {
294 if (constants[i].Type == RC_CONSTANT_IMMEDIATE) {
295 const float *data = constants[i].u.Immediate;
296
297 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
298 OUT_CS(pack_float24(data[0]));
299 OUT_CS(pack_float24(data[1]));
300 OUT_CS(pack_float24(data[2]));
301 OUT_CS(pack_float24(data[3]));
302 }
303 }
304 }
305
306 OUT_CS_REG(R300_FG_DEPTH_SRC, fs->shader->fg_depth_src);
307 OUT_CS_REG(R300_US_W_FMT, fs->shader->us_out_w);
308 END_CS;
309 }
310
311 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
312 {
313 struct r300_fragment_shader *fs = r300_fs(r300);
314 struct rc_constant_list *constants = &fs->shader->code.constants;
315 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
316 unsigned i, count = fs->shader->externals_count;
317 CS_LOCALS(r300);
318
319 if (count == 0)
320 return;
321
322 BEGIN_CS(size);
323 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
324 for(i = 0; i < count; ++i) {
325 const float *data;
326 assert(constants->Constants[i].Type == RC_CONSTANT_EXTERNAL);
327 data = buf->constants[i];
328 OUT_CS(pack_float24(data[0]));
329 OUT_CS(pack_float24(data[1]));
330 OUT_CS(pack_float24(data[2]));
331 OUT_CS(pack_float24(data[3]));
332 }
333 END_CS;
334 }
335
336 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
337 {
338 struct r300_fragment_shader *fs = r300_fs(r300);
339 struct rc_constant_list *constants = &fs->shader->code.constants;
340 unsigned i;
341 unsigned count = fs->shader->rc_state_count;
342 unsigned first = fs->shader->externals_count;
343 unsigned end = constants->Count;
344 CS_LOCALS(r300);
345
346 if (count == 0)
347 return;
348
349 BEGIN_CS(count * 5);
350 for(i = first; i < end; ++i) {
351 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
352 const float *data = get_shader_constant(r300,
353 &constants->Constants[i], 0);
354
355 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
356 OUT_CS(pack_float24(data[0]));
357 OUT_CS(pack_float24(data[1]));
358 OUT_CS(pack_float24(data[2]));
359 OUT_CS(pack_float24(data[3]));
360 }
361 }
362 END_CS;
363 }
364
365 unsigned r500_get_fs_atom_size(struct r300_context *r300)
366 {
367 struct r300_fragment_shader *fs = r300_fs(r300);
368 unsigned imm_count = fs->shader->immediates_count;
369 struct r500_fragment_program_code *code = &fs->shader->code.code.r500;
370
371 return 17 +
372 ((code->inst_end + 1) * 6) +
373 (imm_count ? imm_count * 7 : 0);
374 }
375
376 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
377 {
378 struct r300_fragment_shader *fs = r300_fs(r300);
379 struct rX00_fragment_program_code* generic_code = &fs->shader->code;
380 struct r500_fragment_program_code * code = &generic_code->code.r500;
381 unsigned i;
382 unsigned imm_count = fs->shader->immediates_count;
383 unsigned imm_first = fs->shader->externals_count;
384 unsigned imm_end = generic_code->constants.Count;
385 struct rc_constant *constants = generic_code->constants.Constants;
386 CS_LOCALS(r300);
387
388 BEGIN_CS(size);
389 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
390 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
391 OUT_CS_REG(R500_US_CODE_RANGE,
392 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
393 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
394 OUT_CS_REG(R500_US_CODE_ADDR,
395 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
396
397 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
398 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
399 for (i = 0; i <= code->inst_end; i++) {
400 OUT_CS(code->inst[i].inst0);
401 OUT_CS(code->inst[i].inst1);
402 OUT_CS(code->inst[i].inst2);
403 OUT_CS(code->inst[i].inst3);
404 OUT_CS(code->inst[i].inst4);
405 OUT_CS(code->inst[i].inst5);
406 }
407
408 /* Emit immediates. */
409 if (imm_count) {
410 for(i = imm_first; i < imm_end; ++i) {
411 if (constants[i].Type == RC_CONSTANT_IMMEDIATE) {
412 const float *data = constants[i].u.Immediate;
413
414 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
415 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
416 (i & R500_GA_US_VECTOR_INDEX_MASK));
417 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
418 OUT_CS_32F(data[0]);
419 OUT_CS_32F(data[1]);
420 OUT_CS_32F(data[2]);
421 OUT_CS_32F(data[3]);
422 }
423 }
424 }
425
426 OUT_CS_REG(R300_FG_DEPTH_SRC, fs->shader->fg_depth_src);
427 OUT_CS_REG(R300_US_W_FMT, fs->shader->us_out_w);
428 END_CS;
429 }
430
431 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
432 {
433 struct r300_fragment_shader *fs = r300_fs(r300);
434 struct rc_constant_list *constants = &fs->shader->code.constants;
435 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
436 unsigned i, count = fs->shader->externals_count;
437 CS_LOCALS(r300);
438
439 if (count == 0)
440 return;
441
442 BEGIN_CS(count * 4 + 3);
443 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
444 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
445 for(i = 0; i < count; ++i) {
446 const float *data;
447 assert(constants->Constants[i].Type == RC_CONSTANT_EXTERNAL);
448 data = buf->constants[i];
449
450 OUT_CS_32F(data[0]);
451 OUT_CS_32F(data[1]);
452 OUT_CS_32F(data[2]);
453 OUT_CS_32F(data[3]);
454 }
455 END_CS;
456 }
457
458 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
459 {
460 struct r300_fragment_shader *fs = r300_fs(r300);
461 struct rc_constant_list *constants = &fs->shader->code.constants;
462 unsigned i;
463 unsigned count = fs->shader->rc_state_count;
464 unsigned first = fs->shader->externals_count;
465 unsigned end = constants->Count;
466 CS_LOCALS(r300);
467
468 if (count == 0)
469 return;
470
471 BEGIN_CS(count * 7);
472 for(i = first; i < end; ++i) {
473 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
474 const float *data = get_shader_constant(r300,
475 &constants->Constants[i], 0);
476
477 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
478 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
479 (i & R500_GA_US_VECTOR_INDEX_MASK));
480 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
481 OUT_CS_32F(data[0]);
482 OUT_CS_32F(data[1]);
483 OUT_CS_32F(data[2]);
484 OUT_CS_32F(data[3]);
485 }
486 }
487 END_CS;
488 }
489
490 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
491 {
492 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
493 struct r300_texture* tex;
494 struct pipe_surface* surf;
495 int i;
496 CS_LOCALS(r300);
497
498 BEGIN_CS(size);
499
500 /* Flush and free renderbuffer caches. */
501 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
502 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
503 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
504 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
505 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
506 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
507
508 /* Set the number of colorbuffers. */
509 if (fb->nr_cbufs > 1) {
510 if (r300->screen->caps.is_r500) {
511 OUT_CS_REG(R300_RB3D_CCTL,
512 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
513 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
514 } else {
515 OUT_CS_REG(R300_RB3D_CCTL,
516 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
517 }
518 } else {
519 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
520 }
521
522 /* Set up colorbuffers. */
523 for (i = 0; i < fb->nr_cbufs; i++) {
524 surf = fb->cbufs[i];
525 tex = r300_texture(surf->texture);
526 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
527
528 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
529 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
530
531 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
532 OUT_CS_TEX_RELOC(tex, tex->fb_state.colorpitch[surf->level],
533 0, RADEON_GEM_DOMAIN_VRAM, 0);
534
535 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
536 }
537 for (; i < 4; i++) {
538 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
539 }
540
541 /* Set up a zbuffer. */
542 if (fb->zsbuf) {
543 surf = fb->zsbuf;
544 tex = r300_texture(surf->texture);
545 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
546
547 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
548 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
549
550 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
551
552 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
553 OUT_CS_TEX_RELOC(tex, tex->fb_state.depthpitch[surf->level],
554 0, RADEON_GEM_DOMAIN_VRAM, 0);
555 }
556
557 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
558 if (r300->screen->caps.is_r500) {
559 OUT_CS(0);
560 OUT_CS(((fb->width - 1) << R300_SCISSORS_X_SHIFT) |
561 ((fb->height - 1) << R300_SCISSORS_Y_SHIFT));
562 } else {
563 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
564 (1440 << R300_SCISSORS_Y_SHIFT));
565 OUT_CS(((fb->width + 1440-1) << R300_SCISSORS_X_SHIFT) |
566 ((fb->height + 1440-1) << R300_SCISSORS_Y_SHIFT));
567 }
568 OUT_CS_REG(R300_GA_POINT_MINMAX,
569 (MAX2(fb->width, fb->height) * 6) << R300_GA_POINT_MINMAX_MAX_SHIFT);
570 END_CS;
571 }
572
573 void r300_emit_query_start(struct r300_context *r300)
574 {
575 struct r300_query *query = r300->query_current;
576 CS_LOCALS(r300);
577
578 if (!query)
579 return;
580
581 BEGIN_CS(4);
582 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
583 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
584 } else {
585 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
586 }
587 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
588 END_CS;
589 query->begin_emitted = TRUE;
590 }
591
592
593 static void r300_emit_query_finish(struct r300_context *r300,
594 struct r300_query *query)
595 {
596 struct r300_capabilities* caps = &r300->screen->caps;
597 CS_LOCALS(r300);
598
599 assert(caps->num_frag_pipes);
600
601 BEGIN_CS(6 * caps->num_frag_pipes + 2);
602 /* I'm not so sure I like this switch, but it's hard to be elegant
603 * when there's so many special cases...
604 *
605 * So here's the basic idea. For each pipe, enable writes to it only,
606 * then put out the relocation for ZPASS_ADDR, taking into account a
607 * 4-byte offset for each pipe. RV380 and older are special; they have
608 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
609 * so there's a chipset cap for that. */
610 switch (caps->num_frag_pipes) {
611 case 4:
612 /* pipe 3 only */
613 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
614 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
615 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
616 0, RADEON_GEM_DOMAIN_GTT, 0);
617 case 3:
618 /* pipe 2 only */
619 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
620 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
621 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
622 0, RADEON_GEM_DOMAIN_GTT, 0);
623 case 2:
624 /* pipe 1 only */
625 /* As mentioned above, accomodate RV380 and older. */
626 OUT_CS_REG(R300_SU_REG_DEST,
627 1 << (caps->high_second_pipe ? 3 : 1));
628 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
629 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
630 0, RADEON_GEM_DOMAIN_GTT, 0);
631 case 1:
632 /* pipe 0 only */
633 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
634 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
635 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
636 0, RADEON_GEM_DOMAIN_GTT, 0);
637 break;
638 default:
639 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
640 " pixel pipes!\n", caps->num_frag_pipes);
641 abort();
642 }
643
644 /* And, finally, reset it to normal... */
645 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
646 END_CS;
647 }
648
649 static void rv530_emit_query_single(struct r300_context *r300,
650 struct r300_query *query)
651 {
652 CS_LOCALS(r300);
653
654 BEGIN_CS(8);
655 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
656 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
657 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
658 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
659 END_CS;
660 }
661
662 static void rv530_emit_query_double(struct r300_context *r300,
663 struct r300_query *query)
664 {
665 CS_LOCALS(r300);
666
667 BEGIN_CS(14);
668 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
669 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
670 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
671 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
672 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
673 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
674 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
675 END_CS;
676 }
677
678 void r300_emit_query_end(struct r300_context* r300)
679 {
680 struct r300_capabilities *caps = &r300->screen->caps;
681 struct r300_query *query = r300->query_current;
682
683 if (!query)
684 return;
685
686 if (query->begin_emitted == FALSE)
687 return;
688
689 if (caps->family == CHIP_FAMILY_RV530) {
690 if (caps->num_z_pipes == 2)
691 rv530_emit_query_double(r300, query);
692 else
693 rv530_emit_query_single(r300, query);
694 } else
695 r300_emit_query_finish(r300, query);
696 }
697
698 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
699 {
700 struct r300_rs_state* rs = (struct r300_rs_state*)state;
701 float scale, offset;
702 CS_LOCALS(r300);
703
704 BEGIN_CS(size);
705 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
706
707 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
708
709 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
710 OUT_CS_REG(R300_GA_LINE_CNTL, rs->line_control);
711
712 if (rs->polygon_offset_enable) {
713 scale = rs->depth_scale * 12;
714 offset = rs->depth_offset;
715
716 switch (r300->zbuffer_bpp) {
717 case 16:
718 offset *= 4;
719 break;
720 case 24:
721 offset *= 2;
722 break;
723 }
724
725 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
726 OUT_CS_32F(scale);
727 OUT_CS_32F(offset);
728 OUT_CS_32F(scale);
729 OUT_CS_32F(offset);
730 }
731
732 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
733 OUT_CS(rs->polygon_offset_enable);
734 OUT_CS(rs->cull_mode);
735 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
736 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
737 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
738 OUT_CS_REG(R300_SC_CLIP_RULE, rs->clip_rule);
739 OUT_CS_REG(R300_GB_ENABLE, rs->stuffing_enable);
740 OUT_CS_REG_SEQ(R300_GA_POINT_S0, 4);
741 OUT_CS_32F(rs->point_texcoord_left);
742 OUT_CS_32F(rs->point_texcoord_bottom);
743 OUT_CS_32F(rs->point_texcoord_right);
744 OUT_CS_32F(rs->point_texcoord_top);
745 END_CS;
746 }
747
748 void r300_emit_rs_block_state(struct r300_context* r300,
749 unsigned size, void* state)
750 {
751 struct r300_rs_block* rs = (struct r300_rs_block*)state;
752 unsigned i;
753 /* It's the same for both INST and IP tables */
754 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
755 CS_LOCALS(r300);
756
757 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
758
759 BEGIN_CS(size);
760 if (r300->screen->caps.is_r500) {
761 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
762 } else {
763 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
764 }
765 for (i = 0; i < count; i++) {
766 OUT_CS(rs->ip[i]);
767 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
768 }
769
770 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
771 OUT_CS(rs->count);
772 OUT_CS(rs->inst_count);
773
774 if (r300->screen->caps.is_r500) {
775 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
776 } else {
777 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
778 }
779 for (i = 0; i < count; i++) {
780 OUT_CS(rs->inst[i]);
781 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
782 }
783
784 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
785 rs->count, rs->inst_count);
786
787 END_CS;
788 }
789
790 void r300_emit_scissor_state(struct r300_context* r300,
791 unsigned size, void* state)
792 {
793 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
794 CS_LOCALS(r300);
795
796 BEGIN_CS(size);
797 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
798 if (r300->screen->caps.is_r500) {
799 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
800 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
801 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
802 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
803 } else {
804 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
805 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
806 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
807 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
808 }
809 END_CS;
810 }
811
812 void r300_emit_textures_state(struct r300_context *r300,
813 unsigned size, void *state)
814 {
815 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
816 struct r300_texture_sampler_state *texstate;
817 unsigned i;
818 CS_LOCALS(r300);
819
820 BEGIN_CS(size);
821 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
822
823 for (i = 0; i < allstate->count; i++) {
824 if ((1 << i) & allstate->tx_enable) {
825 texstate = &allstate->regs[i];
826
827 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
828 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
829 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
830 texstate->border_color);
831
832 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
833 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
834 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
835
836 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
837 OUT_CS_TEX_RELOC(r300_texture(allstate->sampler_views[i]->base.texture),
838 texstate->format.tile_config,
839 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
840 }
841 }
842 END_CS;
843 }
844
845 void r300_emit_aos(struct r300_context* r300, unsigned offset)
846 {
847 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
848 struct pipe_vertex_element *velem = r300->velems->velem;
849 int i;
850 unsigned size1, size2, aos_count = r300->velems->count;
851 unsigned packet_size = (aos_count * 3 + 1) / 2;
852 CS_LOCALS(r300);
853
854 BEGIN_CS(2 + packet_size + aos_count * 2);
855 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
856 OUT_CS(aos_count);
857
858 for (i = 0; i < aos_count - 1; i += 2) {
859 vb1 = &vbuf[velem[i].vertex_buffer_index];
860 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
861 size1 = util_format_get_blocksize(velem[i].src_format);
862 size2 = util_format_get_blocksize(velem[i+1].src_format);
863
864 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
865 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
866 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
867 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
868 }
869
870 if (aos_count & 1) {
871 vb1 = &vbuf[velem[i].vertex_buffer_index];
872 size1 = util_format_get_blocksize(velem[i].src_format);
873
874 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
875 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
876 }
877
878 for (i = 0; i < aos_count; i++) {
879 OUT_CS_BUF_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
880 RADEON_GEM_DOMAIN_GTT, 0, 0);
881 }
882 END_CS;
883 }
884
885 void r300_emit_vertex_buffer(struct r300_context* r300)
886 {
887 CS_LOCALS(r300);
888
889 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
890 "vertex size %d\n", r300->vbo,
891 r300->vertex_info.size);
892 /* Set the pointer to our vertex buffer. The emitted values are this:
893 * PACKET3 [3D_LOAD_VBPNTR]
894 * COUNT [1]
895 * FORMAT [size | stride << 8]
896 * OFFSET [offset into BO]
897 * VBPNTR [relocated BO]
898 */
899 BEGIN_CS(7);
900 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
901 OUT_CS(1);
902 OUT_CS(r300->vertex_info.size |
903 (r300->vertex_info.size << 8));
904 OUT_CS(r300->vbo_offset);
905 OUT_CS_BUF_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
906 END_CS;
907 }
908
909 void r300_emit_vertex_stream_state(struct r300_context* r300,
910 unsigned size, void* state)
911 {
912 struct r300_vertex_stream_state *streams =
913 (struct r300_vertex_stream_state*)state;
914 unsigned i;
915 CS_LOCALS(r300);
916
917 DBG(r300, DBG_DRAW, "r300: PSC emit:\n");
918
919 BEGIN_CS(size);
920 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
921 for (i = 0; i < streams->count; i++) {
922 OUT_CS(streams->vap_prog_stream_cntl[i]);
923 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
924 streams->vap_prog_stream_cntl[i]);
925 }
926 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
927 for (i = 0; i < streams->count; i++) {
928 OUT_CS(streams->vap_prog_stream_cntl_ext[i]);
929 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
930 streams->vap_prog_stream_cntl_ext[i]);
931 }
932 END_CS;
933 }
934
935 void r300_emit_vap_output_state(struct r300_context* r300,
936 unsigned size, void* state)
937 {
938 struct r300_vap_output_state *vap_out_state =
939 (struct r300_vap_output_state*)state;
940 CS_LOCALS(r300);
941
942 DBG(r300, DBG_DRAW, "r300: VAP emit:\n");
943
944 BEGIN_CS(size);
945 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
946 OUT_CS(vap_out_state->vap_vtx_state_cntl);
947 OUT_CS(vap_out_state->vap_vsm_vtx_assm);
948 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
949 OUT_CS(vap_out_state->vap_out_vtx_fmt[0]);
950 OUT_CS(vap_out_state->vap_out_vtx_fmt[1]);
951 END_CS;
952 }
953
954 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
955 {
956 CS_LOCALS(r300);
957
958 BEGIN_CS(size);
959 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
960 END_CS;
961 }
962
963 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
964 {
965 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
966 struct r300_vertex_program_code* code = &vs->code;
967 struct r300_screen* r300screen = r300->screen;
968 unsigned instruction_count = code->length / 4;
969 unsigned i;
970
971 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
972 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
973 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
974 unsigned temp_count = MAX2(code->num_temporaries, 1);
975
976 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
977 vtx_mem_size / output_count, 10);
978 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
979
980 unsigned imm_first = vs->externals_count;
981 unsigned imm_end = vs->code.constants.Count;
982 unsigned imm_count = vs->immediates_count;
983
984 CS_LOCALS(r300);
985
986 BEGIN_CS(size);
987 /* R300_VAP_PVS_CODE_CNTL_0
988 * R300_VAP_PVS_CONST_CNTL
989 * R300_VAP_PVS_CODE_CNTL_1
990 * See the r5xx docs for instructions on how to use these. */
991 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
992 OUT_CS(R300_PVS_FIRST_INST(0) |
993 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
994 R300_PVS_LAST_INST(instruction_count - 1));
995 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
996 OUT_CS(instruction_count - 1);
997
998 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
999 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
1000 for (i = 0; i < code->length; i++) {
1001 OUT_CS(code->body.d[i]);
1002 }
1003
1004 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
1005 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
1006 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
1007 R300_PVS_VF_MAX_VTX_NUM(12) |
1008 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
1009
1010 /* Emit immediates. */
1011 if (imm_count) {
1012 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1013 (r300->screen->caps.is_r500 ?
1014 R500_PVS_CONST_START : R300_PVS_CONST_START) +
1015 imm_first);
1016 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
1017 for (i = imm_first; i < imm_end; i++) {
1018 const float *data = vs->code.constants.Constants[i].u.Immediate;
1019 OUT_CS_32F(data[0]);
1020 OUT_CS_32F(data[1]);
1021 OUT_CS_32F(data[2]);
1022 OUT_CS_32F(data[3]);
1023 }
1024 }
1025 END_CS;
1026 }
1027
1028 void r300_emit_vs_constant_buffer(struct r300_context* r300,
1029 struct rc_constant_list* constants)
1030 {
1031 unsigned i;
1032 unsigned count = ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
1033 CS_LOCALS(r300);
1034
1035 BEGIN_CS(count * 4 + 3);
1036 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1037 (r300->screen->caps.is_r500 ?
1038 R500_PVS_CONST_START : R300_PVS_CONST_START));
1039 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1040 for (i = 0; i < count; i++) {
1041 const float *data =
1042 r300->shader_constants[PIPE_SHADER_VERTEX].constants[i];
1043 OUT_CS_32F(data[0]);
1044 OUT_CS_32F(data[1]);
1045 OUT_CS_32F(data[2]);
1046 OUT_CS_32F(data[3]);
1047 }
1048 END_CS;
1049 }
1050
1051 void r300_emit_viewport_state(struct r300_context* r300,
1052 unsigned size, void* state)
1053 {
1054 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1055 CS_LOCALS(r300);
1056
1057 BEGIN_CS(size);
1058 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1059 OUT_CS_32F(viewport->xscale);
1060 OUT_CS_32F(viewport->xoffset);
1061 OUT_CS_32F(viewport->yscale);
1062 OUT_CS_32F(viewport->yoffset);
1063 OUT_CS_32F(viewport->zscale);
1064 OUT_CS_32F(viewport->zoffset);
1065 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1066 END_CS;
1067 }
1068
1069 void r300_emit_ztop_state(struct r300_context* r300,
1070 unsigned size, void* state)
1071 {
1072 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1073 CS_LOCALS(r300);
1074
1075 BEGIN_CS(size);
1076 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1077 END_CS;
1078 }
1079
1080 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1081 {
1082 CS_LOCALS(r300);
1083
1084 BEGIN_CS(size);
1085 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1086 END_CS;
1087 }
1088
1089 void r300_emit_buffer_validate(struct r300_context *r300,
1090 boolean do_validate_vertex_buffers,
1091 struct pipe_resource *index_buffer)
1092 {
1093 struct pipe_framebuffer_state* fb =
1094 (struct pipe_framebuffer_state*)r300->fb_state.state;
1095 struct r300_textures_state *texstate =
1096 (struct r300_textures_state*)r300->textures_state.state;
1097 struct r300_texture* tex;
1098 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1099 struct pipe_vertex_element *velem = r300->velems->velem;
1100 struct pipe_resource *pbuf;
1101 unsigned i;
1102 boolean invalid = FALSE;
1103
1104 /* upload buffers first */
1105 if (r300->any_user_vbs) {
1106 r300_upload_user_buffers(r300);
1107 r300->any_user_vbs = false;
1108 }
1109
1110 /* Clean out BOs. */
1111 r300->rws->reset_bos(r300->rws);
1112
1113 validate:
1114 /* Color buffers... */
1115 for (i = 0; i < fb->nr_cbufs; i++) {
1116 tex = r300_texture(fb->cbufs[i]->texture);
1117 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1118 if (!r300_add_texture(r300->rws, tex,
1119 0, RADEON_GEM_DOMAIN_VRAM)) {
1120 r300->context.flush(&r300->context, 0, NULL);
1121 goto validate;
1122 }
1123 }
1124 /* ...depth buffer... */
1125 if (fb->zsbuf) {
1126 tex = r300_texture(fb->zsbuf->texture);
1127 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1128 if (!r300_add_texture(r300->rws, tex,
1129 0, RADEON_GEM_DOMAIN_VRAM)) {
1130 r300->context.flush(&r300->context, 0, NULL);
1131 goto validate;
1132 }
1133 }
1134 /* ...textures... */
1135 for (i = 0; i < texstate->count; i++) {
1136 if (!(texstate->tx_enable & (1 << i))) {
1137 continue;
1138 }
1139
1140 tex = r300_texture(texstate->sampler_views[i]->base.texture);
1141 if (!r300_add_texture(r300->rws, tex,
1142 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1143 r300->context.flush(&r300->context, 0, NULL);
1144 goto validate;
1145 }
1146 }
1147 /* ...occlusion query buffer... */
1148 if (r300->dirty_state & R300_NEW_QUERY) {
1149 if (!r300_add_buffer(r300->rws, r300->oqbo,
1150 0, RADEON_GEM_DOMAIN_GTT)) {
1151 r300->context.flush(&r300->context, 0, NULL);
1152 goto validate;
1153 }
1154 }
1155 /* ...vertex buffer for SWTCL path... */
1156 if (r300->vbo) {
1157 if (!r300_add_buffer(r300->rws, r300->vbo,
1158 RADEON_GEM_DOMAIN_GTT, 0)) {
1159 r300->context.flush(&r300->context, 0, NULL);
1160 goto validate;
1161 }
1162 }
1163 /* ...vertex buffers for HWTCL path... */
1164 if (do_validate_vertex_buffers) {
1165 for (i = 0; i < r300->velems->count; i++) {
1166 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1167
1168 if (!r300_add_buffer(r300->rws, pbuf,
1169 RADEON_GEM_DOMAIN_GTT, 0)) {
1170 r300->context.flush(&r300->context, 0, NULL);
1171 goto validate;
1172 }
1173 }
1174 }
1175 /* ...and index buffer for HWTCL path. */
1176 if (index_buffer) {
1177 if (!r300_add_buffer(r300->rws, index_buffer,
1178 RADEON_GEM_DOMAIN_GTT, 0)) {
1179 r300->context.flush(&r300->context, 0, NULL);
1180 goto validate;
1181 }
1182 }
1183 if (!r300->rws->validate(r300->rws)) {
1184 r300->context.flush(&r300->context, 0, NULL);
1185 if (invalid) {
1186 /* Well, hell. */
1187 fprintf(stderr, "r300: Stuck in validation loop, gonna quit now.\n");
1188 abort();
1189 }
1190 invalid = TRUE;
1191 goto validate;
1192 }
1193 }
1194
1195 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1196 {
1197 struct r300_atom* atom;
1198 unsigned dwords = 0;
1199
1200 foreach(atom, &r300->atom_list) {
1201 if (atom->dirty || atom->always_dirty) {
1202 dwords += atom->size;
1203 }
1204 }
1205
1206 /* XXX This is the compensation for the non-atomized states. */
1207 dwords += 1024;
1208
1209 return dwords;
1210 }
1211
1212 /* Emit all dirty state. */
1213 void r300_emit_dirty_state(struct r300_context* r300)
1214 {
1215 struct r300_screen* r300screen = r300->screen;
1216 struct r300_atom* atom;
1217
1218 if (r300->dirty_state & R300_NEW_QUERY) {
1219 r300_emit_query_start(r300);
1220 r300->dirty_state &= ~R300_NEW_QUERY;
1221 }
1222
1223 foreach(atom, &r300->atom_list) {
1224 if (atom->dirty || atom->always_dirty) {
1225 atom->emit(r300, atom->size, atom->state);
1226 atom->dirty = FALSE;
1227 }
1228 }
1229
1230 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1231 struct r300_vertex_shader* vs = r300->vs_state.state;
1232 if (vs->code.constants.Count) {
1233 r300_emit_vs_constant_buffer(r300, &vs->code.constants);
1234 }
1235 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1236 }
1237
1238 /* Emit the VBO for SWTCL. */
1239 if (!r300screen->caps.has_tcl) {
1240 r300_emit_vertex_buffer(r300);
1241 }
1242
1243 r300->dirty_hw++;
1244 }