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[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300,
39 unsigned size, void* state)
40 {
41 struct r300_blend_state* blend = (struct r300_blend_state*)state;
42 struct pipe_framebuffer_state* fb =
43 (struct pipe_framebuffer_state*)r300->fb_state.state;
44 CS_LOCALS(r300);
45
46 if (fb->nr_cbufs) {
47 WRITE_CS_TABLE(blend->cb, size);
48 } else {
49 WRITE_CS_TABLE(blend->cb_no_readwrite, size);
50 }
51 }
52
53 void r300_emit_blend_color_state(struct r300_context* r300,
54 unsigned size, void* state)
55 {
56 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
57 CS_LOCALS(r300);
58
59 WRITE_CS_TABLE(bc->cb, size);
60 }
61
62 void r300_emit_clip_state(struct r300_context* r300,
63 unsigned size, void* state)
64 {
65 struct r300_clip_state* clip = (struct r300_clip_state*)state;
66 CS_LOCALS(r300);
67
68 WRITE_CS_TABLE(clip->cb, size);
69 }
70
71 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
72 {
73 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
74 struct pipe_framebuffer_state* fb =
75 (struct pipe_framebuffer_state*)r300->fb_state.state;
76 CS_LOCALS(r300);
77
78 if (fb->zsbuf) {
79 WRITE_CS_TABLE(&dsa->cb_begin, size);
80 } else {
81 WRITE_CS_TABLE(dsa->cb_no_readwrite, size);
82 }
83 }
84
85 static const float * get_rc_constant_state(
86 struct r300_context * r300,
87 struct rc_constant * constant)
88 {
89 struct r300_textures_state* texstate = r300->textures_state.state;
90 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
91 struct pipe_resource *tex;
92
93 assert(constant->Type == RC_CONSTANT_STATE);
94
95 switch (constant->u.State[0]) {
96 /* Factor for converting rectangle coords to
97 * normalized coords. Should only show up on non-r500. */
98 case RC_STATE_R300_TEXRECT_FACTOR:
99 tex = texstate->sampler_views[constant->u.State[1]]->base.texture;
100 vec[0] = 1.0 / tex->width0;
101 vec[1] = 1.0 / tex->height0;
102 break;
103
104 case RC_STATE_R300_VIEWPORT_SCALE:
105 vec[0] = r300->viewport.scale[0];
106 vec[1] = r300->viewport.scale[1];
107 vec[2] = r300->viewport.scale[2];
108 break;
109
110 case RC_STATE_R300_VIEWPORT_OFFSET:
111 vec[0] = r300->viewport.translate[0];
112 vec[1] = r300->viewport.translate[1];
113 vec[2] = r300->viewport.translate[2];
114 break;
115
116 default:
117 fprintf(stderr, "r300: Implementation error: "
118 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
119 }
120
121 /* This should either be (0, 0, 0, 1), which should be a relatively safe
122 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
123 * state factors. */
124 return vec;
125 }
126
127 /* Convert a normal single-precision float into the 7.16 format
128 * used by the R300 fragment shader.
129 */
130 uint32_t pack_float24(float f)
131 {
132 union {
133 float fl;
134 uint32_t u;
135 } u;
136 float mantissa;
137 int exponent;
138 uint32_t float24 = 0;
139
140 if (f == 0.0)
141 return 0;
142
143 u.fl = f;
144
145 mantissa = frexpf(f, &exponent);
146
147 /* Handle -ve */
148 if (mantissa < 0) {
149 float24 |= (1 << 23);
150 mantissa = mantissa * -1.0;
151 }
152 /* Handle exponent, bias of 63 */
153 exponent += 62;
154 float24 |= (exponent << 16);
155 /* Kill 7 LSB of mantissa */
156 float24 |= (u.u & 0x7FFFFF) >> 7;
157
158 return float24;
159 }
160
161 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
162 {
163 struct r300_fragment_shader *fs = r300_fs(r300);
164 CS_LOCALS(r300);
165
166 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
167 }
168
169 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
170 {
171 struct r300_fragment_shader *fs = r300_fs(r300);
172 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
173 unsigned count = fs->shader->externals_count * 4;
174 CS_LOCALS(r300);
175
176 if (count == 0)
177 return;
178
179 BEGIN_CS(size);
180 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count);
181 OUT_CS_TABLE(buf->constants, count);
182 END_CS;
183 }
184
185 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
186 {
187 struct r300_fragment_shader *fs = r300_fs(r300);
188 struct rc_constant_list *constants = &fs->shader->code.constants;
189 unsigned i;
190 unsigned count = fs->shader->rc_state_count;
191 unsigned first = fs->shader->externals_count;
192 unsigned end = constants->Count;
193 uint32_t cdata[4];
194 unsigned j;
195 CS_LOCALS(r300);
196
197 if (count == 0)
198 return;
199
200 BEGIN_CS(size);
201 for(i = first; i < end; ++i) {
202 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
203 const float *data =
204 get_rc_constant_state(r300, &constants->Constants[i]);
205
206 for (j = 0; j < 4; j++)
207 cdata[j] = pack_float24(data[j]);
208
209 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
210 OUT_CS_TABLE(cdata, 4);
211 }
212 }
213 END_CS;
214 }
215
216 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
217 {
218 struct r300_fragment_shader *fs = r300_fs(r300);
219 CS_LOCALS(r300);
220
221 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
222 }
223
224 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
225 {
226 struct r300_fragment_shader *fs = r300_fs(r300);
227 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
228 unsigned count = fs->shader->externals_count * 4;
229 CS_LOCALS(r300);
230
231 if (count == 0)
232 return;
233
234 BEGIN_CS(size);
235 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
236 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count);
237 OUT_CS_TABLE(buf->constants, count);
238 END_CS;
239 }
240
241 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
242 {
243 struct r300_fragment_shader *fs = r300_fs(r300);
244 struct rc_constant_list *constants = &fs->shader->code.constants;
245 unsigned i;
246 unsigned count = fs->shader->rc_state_count;
247 unsigned first = fs->shader->externals_count;
248 unsigned end = constants->Count;
249 CS_LOCALS(r300);
250
251 if (count == 0)
252 return;
253
254 BEGIN_CS(size);
255 for(i = first; i < end; ++i) {
256 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
257 const float *data =
258 get_rc_constant_state(r300, &constants->Constants[i]);
259
260 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
261 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
262 (i & R500_GA_US_VECTOR_INDEX_MASK));
263 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
264 OUT_CS_TABLE(data, 4);
265 }
266 }
267 END_CS;
268 }
269
270 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
271 {
272 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
273 struct pipe_framebuffer_state* fb =
274 (struct pipe_framebuffer_state*)r300->fb_state.state;
275 CS_LOCALS(r300);
276
277 BEGIN_CS(size);
278
279 /* Set up scissors.
280 * By writing to the SC registers, SC & US assert idle. */
281 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
282 if (r300->screen->caps.is_r500) {
283 OUT_CS(0);
284 OUT_CS(((fb->width - 1) << R300_SCISSORS_X_SHIFT) |
285 ((fb->height - 1) << R300_SCISSORS_Y_SHIFT));
286 } else {
287 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
288 (1440 << R300_SCISSORS_Y_SHIFT));
289 OUT_CS(((fb->width + 1440-1) << R300_SCISSORS_X_SHIFT) |
290 ((fb->height + 1440-1) << R300_SCISSORS_Y_SHIFT));
291 }
292
293 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
294 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
295 END_CS;
296 }
297
298 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
299 {
300 struct r300_aa_state *aa = (struct r300_aa_state*)state;
301 CS_LOCALS(r300);
302
303 BEGIN_CS(size);
304 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
305
306 if (aa->dest) {
307 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET, 1);
308 OUT_CS_RELOC(aa->dest->buffer, aa->dest->offset, 0, aa->dest->domain, 0);
309
310 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_PITCH, 1);
311 OUT_CS_RELOC(aa->dest->buffer, aa->dest->pitch, 0, aa->dest->domain, 0);
312 }
313
314 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, aa->aaresolve_ctl);
315 END_CS;
316 }
317
318 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
319 {
320 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
321 struct r300_surface* surf;
322 unsigned i;
323 CS_LOCALS(r300);
324
325 BEGIN_CS(size);
326
327 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
328 * what we usually want. */
329 if (r300->screen->caps.is_r500) {
330 OUT_CS_REG(R300_RB3D_CCTL,
331 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
332 } else {
333 OUT_CS_REG(R300_RB3D_CCTL, 0);
334 }
335
336 /* Set up colorbuffers. */
337 for (i = 0; i < fb->nr_cbufs; i++) {
338 surf = r300_surface(fb->cbufs[i]);
339
340 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
341 OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain, 0);
342
343 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
344 OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain, 0);
345 }
346
347 /* Set up a zbuffer. */
348 if (fb->zsbuf) {
349 surf = r300_surface(fb->zsbuf);
350
351 OUT_CS_REG(R300_ZB_FORMAT, surf->format);
352 OUT_CS_REG(R300_ZB_BW_CNTL, 0);
353
354 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
355 OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain, 0);
356
357 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
358 OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain, 0);
359
360 OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0);
361
362 /* HiZ RAM. */
363 if (r300->screen->caps.has_hiz) {
364 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
365 OUT_CS_REG(R300_ZB_HIZ_PITCH, 0);
366 }
367
368 /* Z Mask RAM. (compressed zbuffer) */
369 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
370 OUT_CS_REG(R300_ZB_ZMASK_PITCH, 0);
371 }
372
373 /* Colorbuffer format in the US block.
374 * (must be written after unpipelined regs) */
375 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
376 for (i = 0; i < fb->nr_cbufs; i++) {
377 OUT_CS(r300_surface(fb->cbufs[i])->format);
378 }
379 for (; i < 4; i++) {
380 OUT_CS(R300_US_OUT_FMT_UNUSED);
381 }
382
383 /* Multisampling. Depends on framebuffer sample count.
384 * These are pipelined regs and as such cannot be moved
385 * to the AA state. */
386 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
387 unsigned mspos0 = 0x66666666;
388 unsigned mspos1 = 0x6666666;
389
390 if (fb->nr_cbufs && fb->cbufs[0]->texture->nr_samples > 1) {
391 /* Subsample placement. These may not be optimal. */
392 switch (fb->cbufs[0]->texture->nr_samples) {
393 case 2:
394 mspos0 = 0x33996633;
395 mspos1 = 0x6666663;
396 break;
397 case 3:
398 mspos0 = 0x33936933;
399 mspos1 = 0x6666663;
400 break;
401 case 4:
402 mspos0 = 0x33939933;
403 mspos1 = 0x3966663;
404 break;
405 case 6:
406 mspos0 = 0x22a2aa22;
407 mspos1 = 0x2a65672;
408 break;
409 default:
410 debug_printf("r300: Bad number of multisamples!\n");
411 }
412 }
413
414 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
415 OUT_CS(mspos0);
416 OUT_CS(mspos1);
417 }
418 END_CS;
419 }
420
421 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
422 {
423 struct r300_query *query = r300->query_current;
424 CS_LOCALS(r300);
425
426 if (!query)
427 return;
428
429 BEGIN_CS(size);
430 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
431 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
432 } else {
433 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
434 }
435 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
436 END_CS;
437 query->begin_emitted = TRUE;
438 query->flushed = FALSE;
439 }
440
441 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
442 struct r300_query *query)
443 {
444 struct r300_capabilities* caps = &r300->screen->caps;
445 struct r300_winsys_buffer *buf = r300->query_current->buffer;
446 CS_LOCALS(r300);
447
448 assert(caps->num_frag_pipes);
449
450 BEGIN_CS(6 * caps->num_frag_pipes + 2);
451 /* I'm not so sure I like this switch, but it's hard to be elegant
452 * when there's so many special cases...
453 *
454 * So here's the basic idea. For each pipe, enable writes to it only,
455 * then put out the relocation for ZPASS_ADDR, taking into account a
456 * 4-byte offset for each pipe. RV380 and older are special; they have
457 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
458 * so there's a chipset cap for that. */
459 switch (caps->num_frag_pipes) {
460 case 4:
461 /* pipe 3 only */
462 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
463 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
464 OUT_CS_RELOC(buf, (query->num_results + 3) * 4,
465 0, query->domain, 0);
466 case 3:
467 /* pipe 2 only */
468 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
469 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
470 OUT_CS_RELOC(buf, (query->num_results + 2) * 4,
471 0, query->domain, 0);
472 case 2:
473 /* pipe 1 only */
474 /* As mentioned above, accomodate RV380 and older. */
475 OUT_CS_REG(R300_SU_REG_DEST,
476 1 << (caps->high_second_pipe ? 3 : 1));
477 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
478 OUT_CS_RELOC(buf, (query->num_results + 1) * 4,
479 0, query->domain, 0);
480 case 1:
481 /* pipe 0 only */
482 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
483 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
484 OUT_CS_RELOC(buf, (query->num_results + 0) * 4,
485 0, query->domain, 0);
486 break;
487 default:
488 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
489 " pixel pipes!\n", caps->num_frag_pipes);
490 abort();
491 }
492
493 /* And, finally, reset it to normal... */
494 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
495 END_CS;
496 }
497
498 static void rv530_emit_query_end_single_z(struct r300_context *r300,
499 struct r300_query *query)
500 {
501 struct r300_winsys_buffer *buf = r300->query_current->buffer;
502 CS_LOCALS(r300);
503
504 BEGIN_CS(8);
505 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
506 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
507 OUT_CS_RELOC(buf, query->num_results * 4, 0, query->domain, 0);
508 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
509 END_CS;
510 }
511
512 static void rv530_emit_query_end_double_z(struct r300_context *r300,
513 struct r300_query *query)
514 {
515 struct r300_winsys_buffer *buf = r300->query_current->buffer;
516 CS_LOCALS(r300);
517
518 BEGIN_CS(14);
519 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
520 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
521 OUT_CS_RELOC(buf, (query->num_results + 0) * 4, 0, query->domain, 0);
522 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
523 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
524 OUT_CS_RELOC(buf, (query->num_results + 1) * 4, 0, query->domain, 0);
525 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
526 END_CS;
527 }
528
529 void r300_emit_query_end(struct r300_context* r300)
530 {
531 struct r300_capabilities *caps = &r300->screen->caps;
532 struct r300_query *query = r300->query_current;
533
534 if (!query)
535 return;
536
537 if (query->begin_emitted == FALSE)
538 return;
539
540 if (caps->family == CHIP_FAMILY_RV530) {
541 if (caps->num_z_pipes == 2)
542 rv530_emit_query_end_double_z(r300, query);
543 else
544 rv530_emit_query_end_single_z(r300, query);
545 } else
546 r300_emit_query_end_frag_pipes(r300, query);
547
548 query->begin_emitted = FALSE;
549 query->num_results += query->num_pipes;
550
551 /* XXX grab all the results and reset the counter. */
552 if (query->num_results >= query->buffer_size / 4 - 4) {
553 query->num_results = (query->buffer_size / 4) / 2;
554 fprintf(stderr, "r300: Rewinding OQBO...\n");
555 }
556 }
557
558 void r300_emit_invariant_state(struct r300_context *r300,
559 unsigned size, void *state)
560 {
561 CS_LOCALS(r300);
562 WRITE_CS_TABLE(state, size);
563 }
564
565 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
566 {
567 struct r300_rs_state* rs = state;
568 CS_LOCALS(r300);
569
570 BEGIN_CS(size);
571 OUT_CS_TABLE(rs->cb_main, 25);
572 if (rs->polygon_offset_enable) {
573 if (r300->zbuffer_bpp == 16) {
574 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5);
575 } else {
576 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5);
577 }
578 }
579 END_CS;
580 }
581
582 void r300_emit_rs_block_state(struct r300_context* r300,
583 unsigned size, void* state)
584 {
585 struct r300_rs_block* rs = (struct r300_rs_block*)state;
586 unsigned i;
587 /* It's the same for both INST and IP tables */
588 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
589 CS_LOCALS(r300);
590
591 if (SCREEN_DBG_ON(r300->screen, DBG_DRAW)) {
592 r500_dump_rs_block(rs);
593
594 fprintf(stderr, "r300: RS emit:\n");
595
596 for (i = 0; i < count; i++)
597 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]);
598
599 for (i = 0; i < count; i++)
600 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]);
601
602 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n",
603 rs->count, rs->inst_count);
604 }
605
606 BEGIN_CS(size);
607 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
608 OUT_CS(rs->vap_vtx_state_cntl);
609 OUT_CS(rs->vap_vsm_vtx_assm);
610 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
611 OUT_CS(rs->vap_out_vtx_fmt[0]);
612 OUT_CS(rs->vap_out_vtx_fmt[1]);
613
614 if (r300->screen->caps.is_r500) {
615 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
616 } else {
617 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
618 }
619 OUT_CS_TABLE(rs->ip, count);
620
621 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
622 OUT_CS(rs->count);
623 OUT_CS(rs->inst_count);
624
625 if (r300->screen->caps.is_r500) {
626 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
627 } else {
628 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
629 }
630 OUT_CS_TABLE(rs->inst, count);
631 END_CS;
632 }
633
634 void r300_emit_scissor_state(struct r300_context* r300,
635 unsigned size, void* state)
636 {
637 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
638 CS_LOCALS(r300);
639
640 BEGIN_CS(size);
641 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
642 if (r300->screen->caps.is_r500) {
643 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
644 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
645 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
646 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
647 } else {
648 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
649 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
650 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
651 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
652 }
653 END_CS;
654 }
655
656 void r300_emit_textures_state(struct r300_context *r300,
657 unsigned size, void *state)
658 {
659 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
660 struct r300_texture_sampler_state *texstate;
661 struct r300_texture *tex;
662 unsigned i;
663 CS_LOCALS(r300);
664
665 BEGIN_CS(size);
666 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
667
668 for (i = 0; i < allstate->count; i++) {
669 if ((1 << i) & allstate->tx_enable) {
670 texstate = &allstate->regs[i];
671 tex = r300_texture(allstate->sampler_views[i]->base.texture);
672
673 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
674 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
675 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
676 texstate->border_color);
677
678 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
679 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
680 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
681
682 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
683 OUT_CS_TEX_RELOC(tex, texstate->format.tile_config, tex->domain,
684 0, 0);
685 }
686 }
687 END_CS;
688 }
689
690 void r300_emit_aos(struct r300_context* r300, int offset, boolean indexed)
691 {
692 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
693 struct pipe_vertex_element *velem = r300->velems->velem;
694 struct r300_buffer *buf;
695 int i;
696 unsigned *hw_format_size = r300->velems->hw_format_size;
697 unsigned size1, size2, aos_count = r300->velems->count;
698 unsigned packet_size = (aos_count * 3 + 1) / 2;
699 CS_LOCALS(r300);
700
701 BEGIN_CS(2 + packet_size + aos_count * 2);
702 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
703 OUT_CS(aos_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
704
705 for (i = 0; i < aos_count - 1; i += 2) {
706 vb1 = &vbuf[velem[i].vertex_buffer_index];
707 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
708 size1 = hw_format_size[i];
709 size2 = hw_format_size[i+1];
710
711 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
712 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
713 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
714 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
715 }
716
717 if (aos_count & 1) {
718 vb1 = &vbuf[velem[i].vertex_buffer_index];
719 size1 = hw_format_size[i];
720
721 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
722 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
723 }
724
725 for (i = 0; i < aos_count; i++) {
726 buf = r300_buffer(vbuf[velem[i].vertex_buffer_index].buffer);
727 OUT_CS_BUF_RELOC_NO_OFFSET(&buf->b.b, buf->domain, 0, 0);
728 }
729 END_CS;
730 }
731
732 void r300_emit_aos_swtcl(struct r300_context *r300, boolean indexed)
733 {
734 CS_LOCALS(r300);
735
736 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
737 "vertex size %d\n", r300->vbo,
738 r300->vertex_info.size);
739 /* Set the pointer to our vertex buffer. The emitted values are this:
740 * PACKET3 [3D_LOAD_VBPNTR]
741 * COUNT [1]
742 * FORMAT [size | stride << 8]
743 * OFFSET [offset into BO]
744 * VBPNTR [relocated BO]
745 */
746 BEGIN_CS(7);
747 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
748 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
749 OUT_CS(r300->vertex_info.size |
750 (r300->vertex_info.size << 8));
751 OUT_CS(r300->vbo_offset);
752 OUT_CS_BUF_RELOC(r300->vbo, 0, r300_buffer(r300->vbo)->domain, 0, 0);
753 END_CS;
754 }
755
756 void r300_emit_vertex_stream_state(struct r300_context* r300,
757 unsigned size, void* state)
758 {
759 struct r300_vertex_stream_state *streams =
760 (struct r300_vertex_stream_state*)state;
761 unsigned i;
762 CS_LOCALS(r300);
763
764 if (DBG_ON(r300, DBG_DRAW)) {
765 fprintf(stderr, "r300: PSC emit:\n");
766
767 for (i = 0; i < streams->count; i++) {
768 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i,
769 streams->vap_prog_stream_cntl[i]);
770 }
771
772 for (i = 0; i < streams->count; i++) {
773 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
774 streams->vap_prog_stream_cntl_ext[i]);
775 }
776 }
777
778 BEGIN_CS(size);
779 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
780 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
781 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
782 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
783 END_CS;
784 }
785
786 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
787 {
788 CS_LOCALS(r300);
789
790 BEGIN_CS(size);
791 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
792 END_CS;
793 }
794
795 void r300_emit_vap_invariant_state(struct r300_context *r300,
796 unsigned size, void *state)
797 {
798 CS_LOCALS(r300);
799 WRITE_CS_TABLE(state, size);
800 }
801
802 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
803 {
804 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
805 struct r300_vertex_program_code* code = &vs->code;
806 struct r300_screen* r300screen = r300->screen;
807 unsigned instruction_count = code->length / 4;
808 unsigned i;
809
810 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
811 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
812 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
813 unsigned temp_count = MAX2(code->num_temporaries, 1);
814
815 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
816 vtx_mem_size / output_count, 10);
817 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
818
819 unsigned imm_first = vs->externals_count;
820 unsigned imm_end = vs->code.constants.Count;
821 unsigned imm_count = vs->immediates_count;
822
823 CS_LOCALS(r300);
824
825 BEGIN_CS(size);
826
827 /* R300_VAP_PVS_CODE_CNTL_0
828 * R300_VAP_PVS_CONST_CNTL
829 * R300_VAP_PVS_CODE_CNTL_1
830 * See the r5xx docs for instructions on how to use these. */
831 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
832 OUT_CS(R300_PVS_FIRST_INST(0) |
833 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
834 R300_PVS_LAST_INST(instruction_count - 1));
835 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
836 OUT_CS(instruction_count - 1);
837
838 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
839 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
840 OUT_CS_TABLE(code->body.d, code->length);
841
842 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
843 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
844 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
845 R300_PVS_VF_MAX_VTX_NUM(12) |
846 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
847
848 /* Emit immediates. */
849 if (imm_count) {
850 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
851 (r300->screen->caps.is_r500 ?
852 R500_PVS_CONST_START : R300_PVS_CONST_START) +
853 imm_first);
854 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
855 for (i = imm_first; i < imm_end; i++) {
856 const float *data = vs->code.constants.Constants[i].u.Immediate;
857 OUT_CS_TABLE(data, 4);
858 }
859 }
860 END_CS;
861 }
862
863 void r300_emit_vs_constants(struct r300_context* r300,
864 unsigned size, void *state)
865 {
866 unsigned count =
867 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
868 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
869 CS_LOCALS(r300);
870
871 if (!count)
872 return;
873
874 BEGIN_CS(size);
875 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
876 (r300->screen->caps.is_r500 ?
877 R500_PVS_CONST_START : R300_PVS_CONST_START));
878 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
879 OUT_CS_TABLE(buf->constants, count * 4);
880 END_CS;
881 }
882
883 void r300_emit_viewport_state(struct r300_context* r300,
884 unsigned size, void* state)
885 {
886 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
887 CS_LOCALS(r300);
888
889 BEGIN_CS(size);
890 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
891 OUT_CS_TABLE(&viewport->xscale, 6);
892 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
893 END_CS;
894 }
895
896 void r300_emit_ztop_state(struct r300_context* r300,
897 unsigned size, void* state)
898 {
899 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
900 CS_LOCALS(r300);
901
902 BEGIN_CS(size);
903 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
904 END_CS;
905 }
906
907 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
908 {
909 CS_LOCALS(r300);
910
911 BEGIN_CS(size);
912 OUT_CS_REG(R300_TX_INVALTAGS, 0);
913 END_CS;
914 }
915
916 void r300_emit_buffer_validate(struct r300_context *r300,
917 boolean do_validate_vertex_buffers,
918 struct pipe_resource *index_buffer)
919 {
920 struct pipe_framebuffer_state* fb =
921 (struct pipe_framebuffer_state*)r300->fb_state.state;
922 struct r300_textures_state *texstate =
923 (struct r300_textures_state*)r300->textures_state.state;
924 struct r300_texture* tex;
925 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
926 struct pipe_vertex_element *velem = r300->velems->velem;
927 struct pipe_resource *pbuf;
928 unsigned i;
929 boolean invalid = FALSE;
930
931 /* upload buffers first */
932 if (r300->screen->caps.has_tcl && r300->any_user_vbs) {
933 r300_upload_user_buffers(r300);
934 r300->any_user_vbs = false;
935 }
936
937 /* Clean out BOs. */
938 r300->rws->reset_bos(r300->rws);
939
940 validate:
941 /* Color buffers... */
942 for (i = 0; i < fb->nr_cbufs; i++) {
943 tex = r300_texture(fb->cbufs[i]->texture);
944 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
945 if (!r300_add_texture(r300->rws, tex, 0, tex->domain)) {
946 r300->context.flush(&r300->context, 0, NULL);
947 goto validate;
948 }
949 }
950 /* ...depth buffer... */
951 if (fb->zsbuf) {
952 tex = r300_texture(fb->zsbuf->texture);
953 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
954 if (!r300_add_texture(r300->rws, tex,
955 0, tex->domain)) {
956 r300->context.flush(&r300->context, 0, NULL);
957 goto validate;
958 }
959 }
960 /* ...textures... */
961 for (i = 0; i < texstate->count; i++) {
962 if (!(texstate->tx_enable & (1 << i))) {
963 continue;
964 }
965
966 tex = r300_texture(texstate->sampler_views[i]->base.texture);
967 if (!r300_add_texture(r300->rws, tex, tex->domain, 0)) {
968 r300->context.flush(&r300->context, 0, NULL);
969 goto validate;
970 }
971 }
972 /* ...occlusion query buffer... */
973 if (r300->query_current) {
974 if (!r300->rws->add_buffer(r300->rws, r300->query_current->buffer,
975 0, r300->query_current->domain)) {
976 r300->context.flush(&r300->context, 0, NULL);
977 goto validate;
978 }
979 }
980 /* ...vertex buffer for SWTCL path... */
981 if (r300->vbo) {
982 if (!r300_add_buffer(r300->rws, r300->vbo,
983 r300_buffer(r300->vbo)->domain, 0)) {
984 r300->context.flush(&r300->context, 0, NULL);
985 goto validate;
986 }
987 }
988 /* ...vertex buffers for HWTCL path... */
989 if (do_validate_vertex_buffers) {
990 for (i = 0; i < r300->velems->count; i++) {
991 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
992
993 if (!r300_add_buffer(r300->rws, pbuf,
994 r300_buffer(pbuf)->domain, 0)) {
995 r300->context.flush(&r300->context, 0, NULL);
996 goto validate;
997 }
998 }
999 }
1000 /* ...and index buffer for HWTCL path. */
1001 if (index_buffer) {
1002 if (!r300_add_buffer(r300->rws, index_buffer,
1003 r300_buffer(index_buffer)->domain, 0)) {
1004 r300->context.flush(&r300->context, 0, NULL);
1005 goto validate;
1006 }
1007 }
1008 if (!r300->rws->validate(r300->rws)) {
1009 r300->context.flush(&r300->context, 0, NULL);
1010 if (invalid) {
1011 /* Well, hell. */
1012 fprintf(stderr, "r300: Stuck in validation loop, gonna quit now.\n");
1013 abort();
1014 }
1015 invalid = TRUE;
1016 goto validate;
1017 }
1018 }
1019
1020 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1021 {
1022 struct r300_atom* atom;
1023 unsigned dwords = 0;
1024
1025 foreach(atom, &r300->atom_list) {
1026 if (atom->dirty) {
1027 dwords += atom->size;
1028 }
1029 }
1030
1031 /* let's reserve some more, just in case */
1032 dwords += 32;
1033
1034 return dwords;
1035 }
1036
1037 /* Emit all dirty state. */
1038 void r300_emit_dirty_state(struct r300_context* r300)
1039 {
1040 struct r300_atom* atom;
1041
1042 foreach(atom, &r300->atom_list) {
1043 if (atom->dirty) {
1044 atom->emit(r300, atom->size, atom->state);
1045 if (SCREEN_DBG_ON(r300->screen, DBG_STATS)) {
1046 atom->counter++;
1047 }
1048 atom->dirty = FALSE;
1049 }
1050 }
1051
1052 r300->dirty_hw++;
1053 }