projects / mesa.git / blob
? search:


dd6cc4d4f84f10547214f616093bf1875573bfee
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300,
39 unsigned size, void* state)
40 {
41 struct r300_blend_state* blend = (struct r300_blend_state*)state;
42 struct pipe_framebuffer_state* fb =
43 (struct pipe_framebuffer_state*)r300->fb_state.state;
44 CS_LOCALS(r300);
45
46 if (fb->nr_cbufs) {
47 WRITE_CS_TABLE(blend->cb, size);
48 } else {
49 WRITE_CS_TABLE(blend->cb_no_readwrite, size);
50 }
51 }
52
53 void r300_emit_blend_color_state(struct r300_context* r300,
54 unsigned size, void* state)
55 {
56 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
57 CS_LOCALS(r300);
58
59 WRITE_CS_TABLE(bc->cb, size);
60 }
61
62 void r300_emit_clip_state(struct r300_context* r300,
63 unsigned size, void* state)
64 {
65 struct r300_clip_state* clip = (struct r300_clip_state*)state;
66 CS_LOCALS(r300);
67
68 WRITE_CS_TABLE(clip->cb, size);
69 }
70
71 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
72 {
73 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
74 struct pipe_framebuffer_state* fb =
75 (struct pipe_framebuffer_state*)r300->fb_state.state;
76 CS_LOCALS(r300);
77
78 if (fb->zsbuf) {
79 WRITE_CS_TABLE(&dsa->cb_begin, size);
80 } else {
81 WRITE_CS_TABLE(dsa->cb_no_readwrite, size);
82 }
83 }
84
85 static const float * get_rc_constant_state(
86 struct r300_context * r300,
87 struct rc_constant * constant)
88 {
89 struct r300_textures_state* texstate = r300->textures_state.state;
90 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
91 struct pipe_resource *tex;
92
93 assert(constant->Type == RC_CONSTANT_STATE);
94
95 switch (constant->u.State[0]) {
96 /* Factor for converting rectangle coords to
97 * normalized coords. Should only show up on non-r500. */
98 case RC_STATE_R300_TEXRECT_FACTOR:
99 tex = texstate->sampler_views[constant->u.State[1]]->base.texture;
100 vec[0] = 1.0 / tex->width0;
101 vec[1] = 1.0 / tex->height0;
102 break;
103
104 case RC_STATE_R300_VIEWPORT_SCALE:
105 vec[0] = r300->viewport.scale[0];
106 vec[1] = r300->viewport.scale[1];
107 vec[2] = r300->viewport.scale[2];
108 break;
109
110 case RC_STATE_R300_VIEWPORT_OFFSET:
111 vec[0] = r300->viewport.translate[0];
112 vec[1] = r300->viewport.translate[1];
113 vec[2] = r300->viewport.translate[2];
114 break;
115
116 default:
117 fprintf(stderr, "r300: Implementation error: "
118 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
119 }
120
121 /* This should either be (0, 0, 0, 1), which should be a relatively safe
122 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
123 * state factors. */
124 return vec;
125 }
126
127 /* Convert a normal single-precision float into the 7.16 format
128 * used by the R300 fragment shader.
129 */
130 uint32_t pack_float24(float f)
131 {
132 union {
133 float fl;
134 uint32_t u;
135 } u;
136 float mantissa;
137 int exponent;
138 uint32_t float24 = 0;
139
140 if (f == 0.0)
141 return 0;
142
143 u.fl = f;
144
145 mantissa = frexpf(f, &exponent);
146
147 /* Handle -ve */
148 if (mantissa < 0) {
149 float24 |= (1 << 23);
150 mantissa = mantissa * -1.0;
151 }
152 /* Handle exponent, bias of 63 */
153 exponent += 62;
154 float24 |= (exponent << 16);
155 /* Kill 7 LSB of mantissa */
156 float24 |= (u.u & 0x7FFFFF) >> 7;
157
158 return float24;
159 }
160
161 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
162 {
163 struct r300_fragment_shader *fs = r300_fs(r300);
164 CS_LOCALS(r300);
165
166 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
167 }
168
169 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
170 {
171 struct r300_fragment_shader *fs = r300_fs(r300);
172 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
173 unsigned count = fs->shader->externals_count * 4;
174 CS_LOCALS(r300);
175
176 if (count == 0)
177 return;
178
179 BEGIN_CS(size);
180 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count);
181 OUT_CS_TABLE(buf->constants, count);
182 END_CS;
183 }
184
185 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
186 {
187 struct r300_fragment_shader *fs = r300_fs(r300);
188 struct rc_constant_list *constants = &fs->shader->code.constants;
189 unsigned i;
190 unsigned count = fs->shader->rc_state_count;
191 unsigned first = fs->shader->externals_count;
192 unsigned end = constants->Count;
193 uint32_t cdata[4];
194 unsigned j;
195 CS_LOCALS(r300);
196
197 if (count == 0)
198 return;
199
200 BEGIN_CS(size);
201 for(i = first; i < end; ++i) {
202 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
203 const float *data =
204 get_rc_constant_state(r300, &constants->Constants[i]);
205
206 for (j = 0; j < 4; j++)
207 cdata[j] = pack_float24(data[j]);
208
209 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
210 OUT_CS_TABLE(cdata, 4);
211 }
212 }
213 END_CS;
214 }
215
216 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
217 {
218 struct r300_fragment_shader *fs = r300_fs(r300);
219 CS_LOCALS(r300);
220
221 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
222 }
223
224 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
225 {
226 struct r300_fragment_shader *fs = r300_fs(r300);
227 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
228 unsigned count = fs->shader->externals_count * 4;
229 CS_LOCALS(r300);
230
231 if (count == 0)
232 return;
233
234 BEGIN_CS(size);
235 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
236 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count);
237 OUT_CS_TABLE(buf->constants, count);
238 END_CS;
239 }
240
241 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
242 {
243 struct r300_fragment_shader *fs = r300_fs(r300);
244 struct rc_constant_list *constants = &fs->shader->code.constants;
245 unsigned i;
246 unsigned count = fs->shader->rc_state_count;
247 unsigned first = fs->shader->externals_count;
248 unsigned end = constants->Count;
249 CS_LOCALS(r300);
250
251 if (count == 0)
252 return;
253
254 BEGIN_CS(size);
255 for(i = first; i < end; ++i) {
256 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
257 const float *data =
258 get_rc_constant_state(r300, &constants->Constants[i]);
259
260 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
261 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
262 (i & R500_GA_US_VECTOR_INDEX_MASK));
263 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
264 OUT_CS_TABLE(data, 4);
265 }
266 }
267 END_CS;
268 }
269
270 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
271 {
272 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
273 struct pipe_framebuffer_state* fb =
274 (struct pipe_framebuffer_state*)r300->fb_state.state;
275 CS_LOCALS(r300);
276
277 BEGIN_CS(size);
278
279 /* Set up scissors.
280 * By writing to the SC registers, SC & US assert idle. */
281 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
282 if (r300->screen->caps.is_r500) {
283 OUT_CS(0);
284 OUT_CS(((fb->width - 1) << R300_SCISSORS_X_SHIFT) |
285 ((fb->height - 1) << R300_SCISSORS_Y_SHIFT));
286 } else {
287 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
288 (1440 << R300_SCISSORS_Y_SHIFT));
289 OUT_CS(((fb->width + 1440-1) << R300_SCISSORS_X_SHIFT) |
290 ((fb->height + 1440-1) << R300_SCISSORS_Y_SHIFT));
291 }
292
293 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
294 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
295 END_CS;
296 }
297
298 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
299 {
300 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
301 struct r300_surface* surf;
302 unsigned i;
303 CS_LOCALS(r300);
304
305 BEGIN_CS(size);
306
307 /* XXX unpipelined regs
308 rb3d_aaresolve_ctl
309 rb3d_aaresolve_offset
310 rb3d_aaresolve_pitch
311 gb_aa_config
312 */
313
314 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
315 * what we usually want. */
316 if (r300->screen->caps.is_r500) {
317 OUT_CS_REG(R300_RB3D_CCTL,
318 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
319 } else {
320 OUT_CS_REG(R300_RB3D_CCTL, 0);
321 }
322
323 /* Set up colorbuffers. */
324 for (i = 0; i < fb->nr_cbufs; i++) {
325 surf = r300_surface(fb->cbufs[i]);
326
327 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
328 OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain, 0);
329
330 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
331 OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain, 0);
332 }
333
334 /* Set up a zbuffer. */
335 if (fb->zsbuf) {
336 surf = r300_surface(fb->zsbuf);
337
338 OUT_CS_REG(R300_ZB_FORMAT, surf->format);
339 OUT_CS_REG(R300_ZB_BW_CNTL, 0);
340
341 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
342 OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain, 0);
343
344 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
345 OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain, 0);
346
347 OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0);
348
349 /* HiZ RAM. */
350 if (r300->screen->caps.has_hiz) {
351 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
352 OUT_CS_REG(R300_ZB_HIZ_PITCH, 0);
353 }
354
355 /* Z Mask RAM. (compressed zbuffer) */
356 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
357 OUT_CS_REG(R300_ZB_ZMASK_PITCH, 0);
358 }
359
360 /* Colorbuffer format in the US block.
361 * (must be written after unpipelined regs) */
362 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
363 for (i = 0; i < fb->nr_cbufs; i++) {
364 OUT_CS(r300_surface(fb->cbufs[i])->format);
365 }
366 for (; i < 4; i++) {
367 OUT_CS(R300_US_OUT_FMT_UNUSED);
368 }
369 END_CS;
370 }
371
372 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
373 {
374 struct r300_query *query = r300->query_current;
375 CS_LOCALS(r300);
376
377 if (!query)
378 return;
379
380 BEGIN_CS(size);
381 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
382 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
383 } else {
384 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
385 }
386 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
387 END_CS;
388 query->begin_emitted = TRUE;
389 query->flushed = FALSE;
390 }
391
392 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
393 struct r300_query *query)
394 {
395 struct r300_capabilities* caps = &r300->screen->caps;
396 struct r300_winsys_buffer *buf = r300->query_current->buffer;
397 CS_LOCALS(r300);
398
399 assert(caps->num_frag_pipes);
400
401 BEGIN_CS(6 * caps->num_frag_pipes + 2);
402 /* I'm not so sure I like this switch, but it's hard to be elegant
403 * when there's so many special cases...
404 *
405 * So here's the basic idea. For each pipe, enable writes to it only,
406 * then put out the relocation for ZPASS_ADDR, taking into account a
407 * 4-byte offset for each pipe. RV380 and older are special; they have
408 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
409 * so there's a chipset cap for that. */
410 switch (caps->num_frag_pipes) {
411 case 4:
412 /* pipe 3 only */
413 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
414 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
415 OUT_CS_RELOC(buf, (query->num_results + 3) * 4,
416 0, query->domain, 0);
417 case 3:
418 /* pipe 2 only */
419 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
420 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
421 OUT_CS_RELOC(buf, (query->num_results + 2) * 4,
422 0, query->domain, 0);
423 case 2:
424 /* pipe 1 only */
425 /* As mentioned above, accomodate RV380 and older. */
426 OUT_CS_REG(R300_SU_REG_DEST,
427 1 << (caps->high_second_pipe ? 3 : 1));
428 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
429 OUT_CS_RELOC(buf, (query->num_results + 1) * 4,
430 0, query->domain, 0);
431 case 1:
432 /* pipe 0 only */
433 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
434 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
435 OUT_CS_RELOC(buf, (query->num_results + 0) * 4,
436 0, query->domain, 0);
437 break;
438 default:
439 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
440 " pixel pipes!\n", caps->num_frag_pipes);
441 abort();
442 }
443
444 /* And, finally, reset it to normal... */
445 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
446 END_CS;
447 }
448
449 static void rv530_emit_query_end_single_z(struct r300_context *r300,
450 struct r300_query *query)
451 {
452 struct r300_winsys_buffer *buf = r300->query_current->buffer;
453 CS_LOCALS(r300);
454
455 BEGIN_CS(8);
456 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
457 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
458 OUT_CS_RELOC(buf, query->num_results * 4, 0, query->domain, 0);
459 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
460 END_CS;
461 }
462
463 static void rv530_emit_query_end_double_z(struct r300_context *r300,
464 struct r300_query *query)
465 {
466 struct r300_winsys_buffer *buf = r300->query_current->buffer;
467 CS_LOCALS(r300);
468
469 BEGIN_CS(14);
470 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
471 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
472 OUT_CS_RELOC(buf, (query->num_results + 0) * 4, 0, query->domain, 0);
473 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
474 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
475 OUT_CS_RELOC(buf, (query->num_results + 1) * 4, 0, query->domain, 0);
476 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
477 END_CS;
478 }
479
480 void r300_emit_query_end(struct r300_context* r300)
481 {
482 struct r300_capabilities *caps = &r300->screen->caps;
483 struct r300_query *query = r300->query_current;
484
485 if (!query)
486 return;
487
488 if (query->begin_emitted == FALSE)
489 return;
490
491 if (caps->family == CHIP_FAMILY_RV530) {
492 if (caps->num_z_pipes == 2)
493 rv530_emit_query_end_double_z(r300, query);
494 else
495 rv530_emit_query_end_single_z(r300, query);
496 } else
497 r300_emit_query_end_frag_pipes(r300, query);
498
499 query->begin_emitted = FALSE;
500 query->num_results += query->num_pipes;
501
502 /* XXX grab all the results and reset the counter. */
503 if (query->num_results >= query->buffer_size / 4 - 4) {
504 query->num_results = (query->buffer_size / 4) / 2;
505 fprintf(stderr, "r300: Rewinding OQBO...\n");
506 }
507 }
508
509 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
510 {
511 struct r300_rs_state* rs = state;
512 struct pipe_framebuffer_state* fb = r300->fb_state.state;
513 float scale, offset;
514 unsigned mspos0, mspos1, aa_config;
515 CS_LOCALS(r300);
516
517 BEGIN_CS(size);
518 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
519
520 /* Multisampling. Depends on framebuffer sample count. */
521 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
522 if (fb->nr_cbufs && fb->cbufs[0]->texture->nr_samples > 1) {
523 aa_config = R300_GB_AA_CONFIG_AA_ENABLE;
524 /* Subsample placement. These may not be optimal. */
525 switch (fb->cbufs[0]->texture->nr_samples) {
526 case 2:
527 aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2;
528 mspos0 = 0x33996633;
529 mspos1 = 0x6666663;
530 break;
531 case 3:
532 aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3;
533 mspos0 = 0x33936933;
534 mspos1 = 0x6666663;
535 break;
536 case 4:
537 aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4;
538 mspos0 = 0x33939933;
539 mspos1 = 0x3966663;
540 break;
541 case 6:
542 aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6;
543 mspos0 = 0x22a2aa22;
544 mspos1 = 0x2a65672;
545 break;
546 default:
547 debug_printf("r300: Bad number of multisamples!\n");
548 mspos0 = rs->multisample_position_0;
549 mspos1 = rs->multisample_position_1;
550 break;
551 }
552
553 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
554 OUT_CS(mspos0);
555 OUT_CS(mspos1);
556
557 OUT_CS_REG(R300_GB_AA_CONFIG, aa_config);
558 } else {
559 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
560 OUT_CS(rs->multisample_position_0);
561 OUT_CS(rs->multisample_position_1);
562
563 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
564 }
565 }
566
567 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
568 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
569 OUT_CS(rs->point_minmax);
570 OUT_CS(rs->line_control);
571
572 if (rs->polygon_offset_enable) {
573 scale = rs->depth_scale * 12;
574 offset = rs->depth_offset;
575
576 switch (r300->zbuffer_bpp) {
577 case 16:
578 offset *= 4;
579 break;
580 case 24:
581 offset *= 2;
582 break;
583 }
584
585 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
586 OUT_CS_32F(scale);
587 OUT_CS_32F(offset);
588 OUT_CS_32F(scale);
589 OUT_CS_32F(offset);
590 }
591
592 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
593 OUT_CS(rs->polygon_offset_enable);
594 OUT_CS(rs->cull_mode);
595 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
596 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
597 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
598 OUT_CS_REG(R300_SC_CLIP_RULE, rs->clip_rule);
599 OUT_CS_REG(R300_GB_ENABLE, rs->stuffing_enable);
600 OUT_CS_REG_SEQ(R300_GA_POINT_S0, 4);
601 OUT_CS_32F(rs->point_texcoord_left);
602 OUT_CS_32F(rs->point_texcoord_bottom);
603 OUT_CS_32F(rs->point_texcoord_right);
604 OUT_CS_32F(rs->point_texcoord_top);
605 END_CS;
606 }
607
608 void r300_emit_rs_block_state(struct r300_context* r300,
609 unsigned size, void* state)
610 {
611 struct r300_rs_block* rs = (struct r300_rs_block*)state;
612 unsigned i;
613 /* It's the same for both INST and IP tables */
614 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
615 CS_LOCALS(r300);
616
617 if (SCREEN_DBG_ON(r300->screen, DBG_DRAW)) {
618 r500_dump_rs_block(rs);
619 }
620
621 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
622
623 BEGIN_CS(size);
624 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
625 OUT_CS(rs->vap_vtx_state_cntl);
626 OUT_CS(rs->vap_vsm_vtx_assm);
627 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
628 OUT_CS(rs->vap_out_vtx_fmt[0]);
629 OUT_CS(rs->vap_out_vtx_fmt[1]);
630
631 if (r300->screen->caps.is_r500) {
632 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
633 } else {
634 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
635 }
636 OUT_CS_TABLE(rs->ip, count);
637 for (i = 0; i < count; i++) {
638 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
639 }
640
641 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
642 OUT_CS(rs->count);
643 OUT_CS(rs->inst_count);
644
645 if (r300->screen->caps.is_r500) {
646 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
647 } else {
648 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
649 }
650 OUT_CS_TABLE(rs->inst, count);
651 for (i = 0; i < count; i++) {
652 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
653 }
654
655 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
656 rs->count, rs->inst_count);
657
658 END_CS;
659 }
660
661 void r300_emit_scissor_state(struct r300_context* r300,
662 unsigned size, void* state)
663 {
664 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
665 CS_LOCALS(r300);
666
667 BEGIN_CS(size);
668 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
669 if (r300->screen->caps.is_r500) {
670 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
671 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
672 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
673 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
674 } else {
675 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
676 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
677 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
678 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
679 }
680 END_CS;
681 }
682
683 void r300_emit_textures_state(struct r300_context *r300,
684 unsigned size, void *state)
685 {
686 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
687 struct r300_texture_sampler_state *texstate;
688 struct r300_texture *tex;
689 unsigned i;
690 CS_LOCALS(r300);
691
692 BEGIN_CS(size);
693 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
694
695 for (i = 0; i < allstate->count; i++) {
696 if ((1 << i) & allstate->tx_enable) {
697 texstate = &allstate->regs[i];
698 tex = r300_texture(allstate->sampler_views[i]->base.texture);
699
700 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
701 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
702 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
703 texstate->border_color);
704
705 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
706 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
707 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
708
709 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
710 OUT_CS_TEX_RELOC(tex, texstate->format.tile_config, tex->domain,
711 0, 0);
712 }
713 }
714 END_CS;
715 }
716
717 void r300_emit_aos(struct r300_context* r300, int offset, boolean indexed)
718 {
719 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
720 struct pipe_vertex_element *velem = r300->velems->velem;
721 struct r300_buffer *buf;
722 int i;
723 unsigned *hw_format_size = r300->velems->hw_format_size;
724 unsigned size1, size2, aos_count = r300->velems->count;
725 unsigned packet_size = (aos_count * 3 + 1) / 2;
726 CS_LOCALS(r300);
727
728 BEGIN_CS(2 + packet_size + aos_count * 2);
729 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
730 OUT_CS(aos_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
731
732 for (i = 0; i < aos_count - 1; i += 2) {
733 vb1 = &vbuf[velem[i].vertex_buffer_index];
734 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
735 size1 = hw_format_size[i];
736 size2 = hw_format_size[i+1];
737
738 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
739 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
740 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
741 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
742 }
743
744 if (aos_count & 1) {
745 vb1 = &vbuf[velem[i].vertex_buffer_index];
746 size1 = hw_format_size[i];
747
748 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
749 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
750 }
751
752 for (i = 0; i < aos_count; i++) {
753 buf = r300_buffer(vbuf[velem[i].vertex_buffer_index].buffer);
754 OUT_CS_BUF_RELOC_NO_OFFSET(&buf->b.b, buf->domain, 0, 0);
755 }
756 END_CS;
757 }
758
759 void r300_emit_aos_swtcl(struct r300_context *r300, boolean indexed)
760 {
761 CS_LOCALS(r300);
762
763 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
764 "vertex size %d\n", r300->vbo,
765 r300->vertex_info.size);
766 /* Set the pointer to our vertex buffer. The emitted values are this:
767 * PACKET3 [3D_LOAD_VBPNTR]
768 * COUNT [1]
769 * FORMAT [size | stride << 8]
770 * OFFSET [offset into BO]
771 * VBPNTR [relocated BO]
772 */
773 BEGIN_CS(7);
774 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
775 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
776 OUT_CS(r300->vertex_info.size |
777 (r300->vertex_info.size << 8));
778 OUT_CS(r300->vbo_offset);
779 OUT_CS_BUF_RELOC(r300->vbo, 0, r300_buffer(r300->vbo)->domain, 0, 0);
780 END_CS;
781 }
782
783 void r300_emit_vertex_stream_state(struct r300_context* r300,
784 unsigned size, void* state)
785 {
786 struct r300_vertex_stream_state *streams =
787 (struct r300_vertex_stream_state*)state;
788 unsigned i;
789 CS_LOCALS(r300);
790
791 DBG(r300, DBG_DRAW, "r300: PSC emit:\n");
792
793 BEGIN_CS(size);
794 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
795 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
796 for (i = 0; i < streams->count; i++) {
797 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
798 streams->vap_prog_stream_cntl[i]);
799 }
800 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
801 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
802 for (i = 0; i < streams->count; i++) {
803 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
804 streams->vap_prog_stream_cntl_ext[i]);
805 }
806 END_CS;
807 }
808
809 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
810 {
811 CS_LOCALS(r300);
812
813 BEGIN_CS(size);
814 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
815 END_CS;
816 }
817
818 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
819 {
820 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
821 struct r300_vertex_program_code* code = &vs->code;
822 struct r300_screen* r300screen = r300->screen;
823 unsigned instruction_count = code->length / 4;
824 unsigned i;
825
826 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
827 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
828 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
829 unsigned temp_count = MAX2(code->num_temporaries, 1);
830
831 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
832 vtx_mem_size / output_count, 10);
833 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
834
835 unsigned imm_first = vs->externals_count;
836 unsigned imm_end = vs->code.constants.Count;
837 unsigned imm_count = vs->immediates_count;
838
839 CS_LOCALS(r300);
840
841 BEGIN_CS(size);
842 /* Amount of time to wait for vertex fetches in PVS */
843 OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
844
845 OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
846 OUT_CS_32F(1.0);
847 OUT_CS_32F(1.0);
848 OUT_CS_32F(1.0);
849 OUT_CS_32F(1.0);
850
851 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
852
853 /* R300_VAP_PVS_CODE_CNTL_0
854 * R300_VAP_PVS_CONST_CNTL
855 * R300_VAP_PVS_CODE_CNTL_1
856 * See the r5xx docs for instructions on how to use these. */
857 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
858 OUT_CS(R300_PVS_FIRST_INST(0) |
859 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
860 R300_PVS_LAST_INST(instruction_count - 1));
861 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
862 OUT_CS(instruction_count - 1);
863
864 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
865 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
866 OUT_CS_TABLE(code->body.d, code->length);
867
868 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
869 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
870 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
871 R300_PVS_VF_MAX_VTX_NUM(12) |
872 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
873
874 /* Emit immediates. */
875 if (imm_count) {
876 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
877 (r300->screen->caps.is_r500 ?
878 R500_PVS_CONST_START : R300_PVS_CONST_START) +
879 imm_first);
880 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
881 for (i = imm_first; i < imm_end; i++) {
882 const float *data = vs->code.constants.Constants[i].u.Immediate;
883 OUT_CS_TABLE(data, 4);
884 }
885 }
886 END_CS;
887 }
888
889 void r300_emit_vs_constants(struct r300_context* r300,
890 unsigned size, void *state)
891 {
892 unsigned count =
893 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
894 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
895 CS_LOCALS(r300);
896
897 if (!count)
898 return;
899
900 BEGIN_CS(size);
901 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
902 (r300->screen->caps.is_r500 ?
903 R500_PVS_CONST_START : R300_PVS_CONST_START));
904 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
905 OUT_CS_TABLE(buf->constants, count * 4);
906 END_CS;
907 }
908
909 void r300_emit_viewport_state(struct r300_context* r300,
910 unsigned size, void* state)
911 {
912 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
913 CS_LOCALS(r300);
914
915 BEGIN_CS(size);
916 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
917 OUT_CS_TABLE(&viewport->xscale, 6);
918 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
919 END_CS;
920 }
921
922 void r300_emit_ztop_state(struct r300_context* r300,
923 unsigned size, void* state)
924 {
925 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
926 CS_LOCALS(r300);
927
928 BEGIN_CS(size);
929 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
930 END_CS;
931 }
932
933 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
934 {
935 CS_LOCALS(r300);
936
937 BEGIN_CS(size);
938 OUT_CS_REG(R300_TX_INVALTAGS, 0);
939 END_CS;
940 }
941
942 void r300_emit_buffer_validate(struct r300_context *r300,
943 boolean do_validate_vertex_buffers,
944 struct pipe_resource *index_buffer)
945 {
946 struct pipe_framebuffer_state* fb =
947 (struct pipe_framebuffer_state*)r300->fb_state.state;
948 struct r300_textures_state *texstate =
949 (struct r300_textures_state*)r300->textures_state.state;
950 struct r300_texture* tex;
951 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
952 struct pipe_vertex_element *velem = r300->velems->velem;
953 struct pipe_resource *pbuf;
954 unsigned i;
955 boolean invalid = FALSE;
956
957 /* upload buffers first */
958 if (r300->screen->caps.has_tcl && r300->any_user_vbs) {
959 r300_upload_user_buffers(r300);
960 r300->any_user_vbs = false;
961 }
962
963 /* Clean out BOs. */
964 r300->rws->reset_bos(r300->rws);
965
966 validate:
967 /* Color buffers... */
968 for (i = 0; i < fb->nr_cbufs; i++) {
969 tex = r300_texture(fb->cbufs[i]->texture);
970 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
971 if (!r300_add_texture(r300->rws, tex, 0, tex->domain)) {
972 r300->context.flush(&r300->context, 0, NULL);
973 goto validate;
974 }
975 }
976 /* ...depth buffer... */
977 if (fb->zsbuf) {
978 tex = r300_texture(fb->zsbuf->texture);
979 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
980 if (!r300_add_texture(r300->rws, tex,
981 0, tex->domain)) {
982 r300->context.flush(&r300->context, 0, NULL);
983 goto validate;
984 }
985 }
986 /* ...textures... */
987 for (i = 0; i < texstate->count; i++) {
988 if (!(texstate->tx_enable & (1 << i))) {
989 continue;
990 }
991
992 tex = r300_texture(texstate->sampler_views[i]->base.texture);
993 if (!r300_add_texture(r300->rws, tex, tex->domain, 0)) {
994 r300->context.flush(&r300->context, 0, NULL);
995 goto validate;
996 }
997 }
998 /* ...occlusion query buffer... */
999 if (r300->query_current) {
1000 if (!r300->rws->add_buffer(r300->rws, r300->query_current->buffer,
1001 0, r300->query_current->domain)) {
1002 r300->context.flush(&r300->context, 0, NULL);
1003 goto validate;
1004 }
1005 }
1006 /* ...vertex buffer for SWTCL path... */
1007 if (r300->vbo) {
1008 if (!r300_add_buffer(r300->rws, r300->vbo,
1009 r300_buffer(r300->vbo)->domain, 0)) {
1010 r300->context.flush(&r300->context, 0, NULL);
1011 goto validate;
1012 }
1013 }
1014 /* ...vertex buffers for HWTCL path... */
1015 if (do_validate_vertex_buffers) {
1016 for (i = 0; i < r300->velems->count; i++) {
1017 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1018
1019 if (!r300_add_buffer(r300->rws, pbuf,
1020 r300_buffer(pbuf)->domain, 0)) {
1021 r300->context.flush(&r300->context, 0, NULL);
1022 goto validate;
1023 }
1024 }
1025 }
1026 /* ...and index buffer for HWTCL path. */
1027 if (index_buffer) {
1028 if (!r300_add_buffer(r300->rws, index_buffer,
1029 r300_buffer(index_buffer)->domain, 0)) {
1030 r300->context.flush(&r300->context, 0, NULL);
1031 goto validate;
1032 }
1033 }
1034 if (!r300->rws->validate(r300->rws)) {
1035 r300->context.flush(&r300->context, 0, NULL);
1036 if (invalid) {
1037 /* Well, hell. */
1038 fprintf(stderr, "r300: Stuck in validation loop, gonna quit now.\n");
1039 abort();
1040 }
1041 invalid = TRUE;
1042 goto validate;
1043 }
1044 }
1045
1046 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1047 {
1048 struct r300_atom* atom;
1049 unsigned dwords = 0;
1050
1051 foreach(atom, &r300->atom_list) {
1052 if (atom->dirty) {
1053 dwords += atom->size;
1054 }
1055 }
1056
1057 /* let's reserve some more, just in case */
1058 dwords += 32;
1059
1060 return dwords;
1061 }
1062
1063 /* Emit all dirty state. */
1064 void r300_emit_dirty_state(struct r300_context* r300)
1065 {
1066 struct r300_atom* atom;
1067
1068 foreach(atom, &r300->atom_list) {
1069 if (atom->dirty) {
1070 atom->emit(r300, atom->size, atom->state);
1071 if (SCREEN_DBG_ON(r300->screen, DBG_STATS)) {
1072 atom->counter++;
1073 }
1074 atom->dirty = FALSE;
1075 }
1076 }
1077
1078 r300->dirty_hw++;
1079 }