src/gallium/drivers/r300/r300_emit.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  22
  23 /* r300_emit: Functions for emitting state. */
  24
  25 #include "util/u_math.h"
  26
  27 #include "r300_context.h"
  28 #include "r300_cs.h"
  29 #include "r300_emit.h"
  30 #include "r300_fs.h"
  31 #include "r300_screen.h"
  32 #include "r300_state_derived.h"
  33 #include "r300_state_inlines.h"
  34 #include "r300_texture.h"
  35 #include "r300_vs.h"
  36
  37 void r300_emit_blend_state(struct r300_context* r300,
  38                            struct r300_blend_state* blend)
  39 {
  40     CS_LOCALS(r300);
  41     BEGIN_CS(7);
  42     OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 2);
  43     OUT_CS(blend->blend_control);
  44     OUT_CS(blend->alpha_blend_control);
  45     OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
  46     OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
  47     END_CS;
  48 }
  49
  50 void r300_emit_blend_color_state(struct r300_context* r300,
  51                                  struct r300_blend_color_state* bc)
  52 {
  53     struct r300_screen* r300screen = r300_screen(r300->context.screen);
  54     CS_LOCALS(r300);
  55
  56     if (r300screen->caps->is_r500) {
  57         BEGIN_CS(3);
  58         OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
  59         OUT_CS(bc->blend_color_red_alpha);
  60         OUT_CS(bc->blend_color_green_blue);
  61         END_CS;
  62     } else {
  63         BEGIN_CS(2);
  64         OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
  65         END_CS;
  66     }
  67 }
  68
  69 void r300_emit_clip_state(struct r300_context* r300,
  70                           struct pipe_clip_state* clip)
  71 {
  72     int i;
  73     struct r300_screen* r300screen = r300_screen(r300->context.screen);
  74     CS_LOCALS(r300);
  75
  76     if (r300screen->caps->has_tcl) {
  77         BEGIN_CS(5 + (6 * 4));
  78         OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
  79                 (r300screen->caps->is_r500 ?
  80                  R500_PVS_UCP_START : R300_PVS_UCP_START));
  81         OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
  82         for (i = 0; i < 6; i++) {
  83             OUT_CS_32F(clip->ucp[i][0]);
  84             OUT_CS_32F(clip->ucp[i][1]);
  85             OUT_CS_32F(clip->ucp[i][2]);
  86             OUT_CS_32F(clip->ucp[i][3]);
  87         }
  88         OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
  89                 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
  90         END_CS;
  91     } else {
  92         BEGIN_CS(2);
  93         OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
  94         END_CS;
  95     }
  96
  97 }
  98
  99 void r300_emit_dsa_state(struct r300_context* r300,
 100                            struct r300_dsa_state* dsa)
 101 {
 102     struct r300_screen* r300screen = r300_screen(r300->context.screen);
 103     CS_LOCALS(r300);
 104
 105     BEGIN_CS(r300screen->caps->is_r500 ? 8 : 8);
 106     OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
 107     /* XXX figure out the r300 counterpart for this */
 108     if (r300screen->caps->is_r500) {
 109         /* OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference); */
 110     }
 111     OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
 112     OUT_CS(dsa->z_buffer_control);
 113     OUT_CS(dsa->z_stencil_control);
 114     OUT_CS(dsa->stencil_ref_mask);
 115     OUT_CS_REG(R300_ZB_ZTOP, r300->ztop_state.z_buffer_top);
 116     if (r300screen->caps->is_r500) {
 117         /* OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); */
 118     }
 119     END_CS;
 120 }
 121
 122 static const float * get_shader_constant(
 123     struct r300_context * r300,
 124     struct rc_constant * constant,
 125     struct r300_constant_buffer * externals)
 126 {
 127     static const float zero[4] = { 0.0, 0.0, 0.0, 0.0 };
 128     switch(constant->Type) {
 129         case RC_CONSTANT_EXTERNAL:
 130             return externals->constants[constant->u.External];
 131
 132         case RC_CONSTANT_IMMEDIATE:
 133             return constant->u.Immediate;
 134
 135         default:
 136             debug_printf("r300: Implementation error: Unhandled constant type %i\n",
 137                 constant->Type);
 138             return zero;
 139     }
 140 }
 141
 142 /* Convert a normal single-precision float into the 7.16 format
 143  * used by the R300 fragment shader.
 144  */
 145 static uint32_t pack_float24(float f)
 146 {
 147     union {
 148         float fl;
 149         uint32_t u;
 150     } u;
 151     float mantissa;
 152     int exponent;
 153     uint32_t float24 = 0;
 154
 155     if (f == 0.0)
 156         return 0;
 157
 158     u.fl = f;
 159
 160     mantissa = frexpf(f, &exponent);
 161
 162     /* Handle -ve */
 163     if (mantissa < 0) {
 164         float24 |= (1 << 23);
 165         mantissa = mantissa * -1.0;
 166     }
 167     /* Handle exponent, bias of 63 */
 168     exponent += 62;
 169     float24 |= (exponent << 16);
 170     /* Kill 7 LSB of mantissa */
 171     float24 |= (u.u & 0x7FFFFF) >> 7;
 172
 173     return float24;
 174 }
 175
 176 void r300_emit_fragment_program_code(struct r300_context* r300,
 177                                      struct rX00_fragment_program_code* generic_code,
 178                                      struct r300_constant_buffer* externals)
 179 {
 180     struct r300_fragment_program_code * code = &generic_code->code.r300;
 181     struct rc_constant_list * constants = &generic_code->constants;
 182     int i;
 183     CS_LOCALS(r300);
 184
 185     BEGIN_CS(15 +
 186              code->alu.length * 4 +
 187              (code->tex.length ? (1 + code->tex.length) : 0) +
 188              (constants->Count ? (1 + constants->Count * 4) : 0));
 189
 190     OUT_CS_REG(R300_US_CONFIG, code->config);
 191     OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
 192     OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
 193
 194     OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
 195     for(i = 0; i < 4; ++i)
 196         OUT_CS(code->code_addr[i]);
 197
 198     OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
 199     for (i = 0; i < code->alu.length; i++)
 200         OUT_CS(code->alu.inst[i].rgb_inst);
 201
 202     OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
 203     for (i = 0; i < code->alu.length; i++)
 204         OUT_CS(code->alu.inst[i].rgb_addr);
 205
 206     OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
 207     for (i = 0; i < code->alu.length; i++)
 208         OUT_CS(code->alu.inst[i].alpha_inst);
 209
 210     OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
 211     for (i = 0; i < code->alu.length; i++)
 212         OUT_CS(code->alu.inst[i].alpha_addr);
 213
 214     if (code->tex.length) {
 215         OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
 216         for(i = 0; i < code->tex.length; ++i)
 217             OUT_CS(code->tex.inst[i]);
 218     }
 219
 220     if (constants->Count) {
 221         OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
 222         for(i = 0; i < constants->Count; ++i) {
 223             const float * data = get_shader_constant(r300, &constants->Constants[i], externals);
 224             OUT_CS(pack_float24(data[0]));
 225             OUT_CS(pack_float24(data[1]));
 226             OUT_CS(pack_float24(data[2]));
 227             OUT_CS(pack_float24(data[3]));
 228         }
 229     }
 230
 231     END_CS;
 232 }
 233
 234 void r500_emit_fragment_program_code(struct r300_context* r300,
 235                                      struct rX00_fragment_program_code* generic_code,
 236                                      struct r300_constant_buffer* externals)
 237 {
 238     struct r500_fragment_program_code * code = &generic_code->code.r500;
 239     struct rc_constant_list * constants = &generic_code->constants;
 240     int i;
 241     CS_LOCALS(r300);
 242
 243     BEGIN_CS(13 +
 244              ((code->inst_end + 1) * 6) +
 245              (constants->Count ? (3 + (constants->Count * 4)) : 0));
 246     OUT_CS_REG(R500_US_CONFIG, 0);
 247     OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
 248     OUT_CS_REG(R500_US_CODE_RANGE,
 249                R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
 250     OUT_CS_REG(R500_US_CODE_OFFSET, 0);
 251     OUT_CS_REG(R500_US_CODE_ADDR,
 252                R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
 253
 254     OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
 255     OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
 256     for (i = 0; i <= code->inst_end; i++) {
 257         OUT_CS(code->inst[i].inst0);
 258         OUT_CS(code->inst[i].inst1);
 259         OUT_CS(code->inst[i].inst2);
 260         OUT_CS(code->inst[i].inst3);
 261         OUT_CS(code->inst[i].inst4);
 262         OUT_CS(code->inst[i].inst5);
 263     }
 264
 265     if (constants->Count) {
 266         OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
 267         OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
 268         for (i = 0; i < constants->Count; i++) {
 269             const float * data = get_shader_constant(r300, &constants->Constants[i], externals);
 270             OUT_CS_32F(data[0]);
 271             OUT_CS_32F(data[1]);
 272             OUT_CS_32F(data[2]);
 273             OUT_CS_32F(data[3]);
 274         }
 275     }
 276
 277     END_CS;
 278 }
 279
 280 void r300_emit_fb_state(struct r300_context* r300,
 281                         struct pipe_framebuffer_state* fb)
 282 {
 283     struct r300_texture* tex;
 284     unsigned pixpitch;
 285     int i;
 286     CS_LOCALS(r300);
 287
 288     BEGIN_CS((10 * fb->nr_cbufs) + (fb->zsbuf ? 10 : 0) + 4);
 289     for (i = 0; i < fb->nr_cbufs; i++) {
 290         tex = (struct r300_texture*)fb->cbufs[i]->texture;
 291         assert(tex && tex->buffer && "cbuf is marked, but NULL!");
 292         pixpitch = r300_texture_get_stride(tex, 0) / tex->tex.block.size;
 293
 294         OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
 295         OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 296
 297         OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
 298         OUT_CS_RELOC(tex->buffer, pixpitch |
 299                      r300_translate_colorformat(tex->tex.format), 0,
 300                      RADEON_GEM_DOMAIN_VRAM, 0);
 301
 302         OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
 303             r300_translate_out_fmt(fb->cbufs[i]->format));
 304     }
 305
 306     if (fb->zsbuf) {
 307         tex = (struct r300_texture*)fb->zsbuf->texture;
 308         assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
 309         pixpitch = r300_texture_get_stride(tex, 0) / tex->tex.block.size;
 310
 311         OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
 312         OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 313
 314         OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
 315
 316         OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
 317         OUT_CS_RELOC(tex->buffer, pixpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 318     }
 319
 320     OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
 321         R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
 322         R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 323     OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
 324         R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
 325         R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
 326     END_CS;
 327 }
 328
 329 static void r300_emit_query_start(struct r300_context *r300)
 330 {
 331     struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
 332     struct r300_query *query = r300->query_current;
 333     CS_LOCALS(r300);
 334
 335     if (!query)
 336         return;
 337
 338     /* XXX This will almost certainly not return good results
 339      * for overlapping queries. */
 340     BEGIN_CS(4);
 341     if (caps->family == CHIP_FAMILY_RV530) {
 342         OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 343     } else {
 344         OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 345     }
 346     OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
 347     END_CS;
 348     query->begin_emitted = TRUE;
 349 }
 350
 351
 352 static void r300_emit_query_finish(struct r300_context *r300,
 353                                    struct r300_query *query)
 354 {
 355     struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
 356     CS_LOCALS(r300);
 357
 358     assert(caps->num_frag_pipes);
 359
 360     BEGIN_CS(6 * caps->num_frag_pipes + 2);
 361     /* I'm not so sure I like this switch, but it's hard to be elegant
 362      * when there's so many special cases...
 363      *
 364      * So here's the basic idea. For each pipe, enable writes to it only,
 365      * then put out the relocation for ZPASS_ADDR, taking into account a
 366      * 4-byte offset for each pipe. RV380 and older are special; they have
 367      * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
 368      * so there's a chipset cap for that. */
 369     switch (caps->num_frag_pipes) {
 370         case 4:
 371             /* pipe 3 only */
 372             OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
 373             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 374             OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
 375                     0, RADEON_GEM_DOMAIN_GTT, 0);
 376         case 3:
 377             /* pipe 2 only */
 378             OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
 379             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 380             OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
 381                     0, RADEON_GEM_DOMAIN_GTT, 0);
 382         case 2:
 383             /* pipe 1 only */
 384             /* As mentioned above, accomodate RV380 and older. */
 385             OUT_CS_REG(R300_SU_REG_DEST,
 386                     1 << (caps->high_second_pipe ? 3 : 1));
 387             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 388             OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
 389                     0, RADEON_GEM_DOMAIN_GTT, 0);
 390         case 1:
 391             /* pipe 0 only */
 392             OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
 393             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 394             OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
 395                     0, RADEON_GEM_DOMAIN_GTT, 0);
 396             break;
 397         default:
 398             debug_printf("r300: Implementation error: Chipset reports %d"
 399                     " pixel pipes!\n", caps->num_frag_pipes);
 400             assert(0);
 401     }
 402
 403     /* And, finally, reset it to normal... */
 404     OUT_CS_REG(R300_SU_REG_DEST, 0xF);
 405     END_CS;
 406 }
 407
 408 static void rv530_emit_query_single(struct r300_context *r300,
 409                                     struct r300_query *query)
 410 {
 411     CS_LOCALS(r300);
 412
 413     BEGIN_CS(8);
 414     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 415     OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 416     OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 417     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 418     END_CS;
 419 }
 420
 421 static void rv530_emit_query_double(struct r300_context *r300,
 422                                     struct r300_query *query)
 423 {
 424     CS_LOCALS(r300);
 425
 426     BEGIN_CS(14);
 427     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 428     OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 429     OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 430     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 431     OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 432     OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 433     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 434     END_CS;
 435 }
 436
 437 void r300_emit_query_end(struct r300_context* r300)
 438 {
 439     struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
 440     struct r300_query *query = r300->query_current;
 441
 442     if (!query)
 443         return;
 444
 445     if (query->begin_emitted == FALSE)
 446         return;
 447
 448     if (caps->family == CHIP_FAMILY_RV530) {
 449         if (caps->num_z_pipes == 2)
 450             rv530_emit_query_double(r300, query);
 451         else
 452             rv530_emit_query_single(r300, query);
 453     } else
 454         r300_emit_query_finish(r300, query);
 455 }
 456
 457 void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs)
 458 {
 459     CS_LOCALS(r300);
 460
 461     BEGIN_CS(20);
 462     OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
 463     OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
 464     OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
 465     OUT_CS(rs->point_minmax);
 466     OUT_CS(rs->line_control);
 467     OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
 468     OUT_CS(rs->depth_scale_front);
 469     OUT_CS(rs->depth_offset_front);
 470     OUT_CS(rs->depth_scale_back);
 471     OUT_CS(rs->depth_offset_back);
 472     OUT_CS(rs->polygon_offset_enable);
 473     OUT_CS(rs->cull_mode);
 474     OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
 475     OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
 476     OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
 477     END_CS;
 478 }
 479
 480 void r300_emit_rs_block_state(struct r300_context* r300,
 481                               struct r300_rs_block* rs)
 482 {
 483     int i;
 484     struct r300_screen* r300screen = r300_screen(r300->context.screen);
 485     CS_LOCALS(r300);
 486
 487     BEGIN_CS(21);
 488     if (r300screen->caps->is_r500) {
 489         OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
 490     } else {
 491         OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
 492     }
 493     for (i = 0; i < 8; i++) {
 494         OUT_CS(rs->ip[i]);
 495         /* debug_printf("ip %d: 0x%08x\n", i, rs->ip[i]); */
 496     }
 497
 498     OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
 499     OUT_CS(rs->count);
 500     OUT_CS(rs->inst_count);
 501
 502     if (r300screen->caps->is_r500) {
 503         OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
 504     } else {
 505         OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
 506     }
 507     for (i = 0; i < 8; i++) {
 508         OUT_CS(rs->inst[i]);
 509         /* debug_printf("inst %d: 0x%08x\n", i, rs->inst[i]); */
 510     }
 511
 512     /* debug_printf("count: 0x%08x inst_count: 0x%08x\n", rs->count,
 513      *        rs->inst_count); */
 514
 515     END_CS;
 516 }
 517
 518 void r300_emit_scissor_state(struct r300_context* r300,
 519                              struct r300_scissor_state* scissor)
 520 {
 521     CS_LOCALS(r300);
 522
 523     BEGIN_CS(3);
 524     OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
 525     OUT_CS(scissor->scissor_top_left);
 526     OUT_CS(scissor->scissor_bottom_right);
 527     END_CS;
 528 }
 529
 530 void r300_emit_texture(struct r300_context* r300,
 531                        struct r300_sampler_state* sampler,
 532                        struct r300_texture* tex,
 533                        unsigned offset)
 534 {
 535     CS_LOCALS(r300);
 536
 537     BEGIN_CS(16);
 538     OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), sampler->filter0 |
 539         (offset << 28));
 540     OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
 541     OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
 542
 543     OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), tex->state.format0);
 544     OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
 545     OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
 546     OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
 547     OUT_CS_RELOC(tex->buffer, 0,
 548             RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
 549     END_CS;
 550 }
 551
 552 void r300_emit_vertex_buffer(struct r300_context* r300)
 553 {
 554     CS_LOCALS(r300);
 555
 556     DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
 557             "vertex size %d\n", r300->vbo,
 558             r300->vertex_info->vinfo.size);
 559     /* Set the pointer to our vertex buffer. The emitted values are this:
 560      * PACKET3 [3D_LOAD_VBPNTR]
 561      * COUNT   [1]
 562      * FORMAT  [size | stride << 8]
 563      * OFFSET  [offset into BO]
 564      * VBPNTR  [relocated BO]
 565      */
 566     BEGIN_CS(7);
 567     OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
 568     OUT_CS(1);
 569     OUT_CS(r300->vertex_info->vinfo.size |
 570             (r300->vertex_info->vinfo.size << 8));
 571     OUT_CS(r300->vbo_offset);
 572     OUT_CS_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
 573     END_CS;
 574 }
 575
 576 void r300_emit_vertex_format_state(struct r300_context* r300)
 577 {
 578     int i;
 579     CS_LOCALS(r300);
 580
 581     BEGIN_CS(26);
 582     OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info->vinfo.size);
 583
 584     OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
 585     OUT_CS(r300->vertex_info->vinfo.hwfmt[0]);
 586     OUT_CS(r300->vertex_info->vinfo.hwfmt[1]);
 587     OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 588     OUT_CS(r300->vertex_info->vinfo.hwfmt[2]);
 589     OUT_CS(r300->vertex_info->vinfo.hwfmt[3]);
 590     /* for (i = 0; i < 4; i++) {
 591      *    debug_printf("hwfmt%d: 0x%08x\n", i,
 592      *            r300->vertex_info->vinfo.hwfmt[i]);
 593      * } */
 594
 595     OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
 596     for (i = 0; i < 8; i++) {
 597         OUT_CS(r300->vertex_info->vap_prog_stream_cntl[i]);
 598         /* debug_printf("prog_stream_cntl%d: 0x%08x\n", i,
 599          *        r300->vertex_info->vap_prog_stream_cntl[i]); */
 600     }
 601     OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
 602     for (i = 0; i < 8; i++) {
 603         OUT_CS(r300->vertex_info->vap_prog_stream_cntl_ext[i]);
 604         /* debug_printf("prog_stream_cntl_ext%d: 0x%08x\n", i,
 605          *        r300->vertex_info->vap_prog_stream_cntl_ext[i]); */
 606     }
 607     END_CS;
 608 }
 609
 610 void r300_emit_vertex_program_code(struct r300_context* r300,
 611                                    struct r300_vertex_program_code* code,
 612                                    struct r300_constant_buffer* constants)
 613 {
 614     int i;
 615     struct r300_screen* r300screen = r300_screen(r300->context.screen);
 616     unsigned instruction_count = code->length / 4;
 617     CS_LOCALS(r300);
 618
 619     if (!r300screen->caps->has_tcl) {
 620         debug_printf("r300: Implementation error: emit_vertex_shader called,"
 621                 " but has_tcl is FALSE!\n");
 622         return;
 623     }
 624
 625     if (code->constants.Count) {
 626         BEGIN_CS(14 + code->length + (code->constants.Count * 4));
 627     } else {
 628         BEGIN_CS(11 + code->length);
 629     }
 630
 631     /* R300_VAP_PVS_CODE_CNTL_0
 632      * R300_VAP_PVS_CONST_CNTL
 633      * R300_VAP_PVS_CODE_CNTL_1
 634      * See the r5xx docs for instructions on how to use these.
 635      * XXX these could be optimized to select better values... */
 636     OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
 637     OUT_CS(R300_PVS_FIRST_INST(0) |
 638             R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
 639             R300_PVS_LAST_INST(instruction_count - 1));
 640     OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
 641     OUT_CS(instruction_count - 1);
 642
 643     OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
 644     OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
 645     for (i = 0; i < code->length; i++)
 646         OUT_CS(code->body.d[i]);
 647
 648     if (code->constants.Count) {
 649         OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
 650                 (r300screen->caps->is_r500 ?
 651                  R500_PVS_CONST_START : R300_PVS_CONST_START));
 652         OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->constants.Count * 4);
 653         for (i = 0; i < code->constants.Count; i++) {
 654             const float * data = get_shader_constant(r300, &code->constants.Constants[i], constants);
 655             OUT_CS_32F(data[0]);
 656             OUT_CS_32F(data[1]);
 657             OUT_CS_32F(data[2]);
 658             OUT_CS_32F(data[3]);
 659         }
 660     }
 661
 662     OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(10) |
 663             R300_PVS_NUM_CNTLRS(5) |
 664             R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
 665             R300_PVS_VF_MAX_VTX_NUM(12));
 666     OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
 667     END_CS;
 668 }
 669
 670 void r300_emit_vertex_shader(struct r300_context* r300,
 671                              struct r300_vertex_shader* vs)
 672 {
 673     r300_emit_vertex_program_code(r300, &vs->code, &r300->shader_constants[PIPE_SHADER_VERTEX]);
 674 }
 675
 676 void r300_emit_viewport_state(struct r300_context* r300,
 677                               struct r300_viewport_state* viewport)
 678 {
 679     CS_LOCALS(r300);
 680
 681     BEGIN_CS(9);
 682     OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
 683     OUT_CS_32F(viewport->xscale);
 684     OUT_CS_32F(viewport->xoffset);
 685     OUT_CS_32F(viewport->yscale);
 686     OUT_CS_32F(viewport->yoffset);
 687     OUT_CS_32F(viewport->zscale);
 688     OUT_CS_32F(viewport->zoffset);
 689
 690     if (r300->rs_state->enable_vte) {
 691         OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
 692     } else {
 693         OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
 694     }
 695     END_CS;
 696 }
 697
 698 void r300_flush_textures(struct r300_context* r300)
 699 {
 700     CS_LOCALS(r300);
 701
 702     BEGIN_CS(4);
 703     OUT_CS_REG(R300_TX_INVALTAGS, 0);
 704     OUT_CS_REG(R300_TX_ENABLE, (1 << r300->texture_count) - 1);
 705     END_CS;
 706 }
 707
 708 /* Emit all dirty state. */
 709 void r300_emit_dirty_state(struct r300_context* r300)
 710 {
 711     struct r300_screen* r300screen = r300_screen(r300->context.screen);
 712     struct r300_texture* tex;
 713     int i, dirty_tex = 0;
 714     boolean invalid = FALSE;
 715
 716     if (!(r300->dirty_state)) {
 717         return;
 718     }
 719
 720     r300_update_derived_state(r300);
 721
 722     /* Clean out BOs. */
 723     r300->winsys->reset_bos(r300->winsys);
 724
 725     /* XXX check size */
 726 validate:
 727     /* Color buffers... */
 728     for (i = 0; i < r300->framebuffer_state.nr_cbufs; i++) {
 729         tex = (struct r300_texture*)r300->framebuffer_state.cbufs[i]->texture;
 730         assert(tex && tex->buffer && "cbuf is marked, but NULL!");
 731         if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
 732                     0, RADEON_GEM_DOMAIN_VRAM)) {
 733             r300->context.flush(&r300->context, 0, NULL);
 734             goto validate;
 735         }
 736     }
 737     /* ...depth buffer... */
 738     if (r300->framebuffer_state.zsbuf) {
 739         tex = (struct r300_texture*)r300->framebuffer_state.zsbuf->texture;
 740         assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
 741         if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
 742                     0, RADEON_GEM_DOMAIN_VRAM)) {
 743             r300->context.flush(&r300->context, 0, NULL);
 744             goto validate;
 745         }
 746     }
 747     /* ...textures... */
 748     for (i = 0; i < r300->texture_count; i++) {
 749         tex = r300->textures[i];
 750         if (!tex)
 751             continue;
 752         if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
 753                     RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
 754             r300->context.flush(&r300->context, 0, NULL);
 755             goto validate;
 756         }
 757     }
 758     /* ...occlusion query buffer... */
 759     if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
 760                 0, RADEON_GEM_DOMAIN_GTT)) {
 761         r300->context.flush(&r300->context, 0, NULL);
 762         goto validate;
 763     }
 764     /* ...and vertex buffer. */
 765     if (r300->vbo) {
 766         if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
 767                     RADEON_GEM_DOMAIN_GTT, 0)) {
 768             r300->context.flush(&r300->context, 0, NULL);
 769             goto validate;
 770         }
 771     } else {
 772         debug_printf("No VBO while emitting dirty state!\n");
 773     }
 774     if (!r300->winsys->validate(r300->winsys)) {
 775         r300->context.flush(&r300->context, 0, NULL);
 776         if (invalid) {
 777             /* Well, hell. */
 778             debug_printf("r300: Stuck in validation loop, gonna quit now.");
 779             exit(1);
 780         }
 781         invalid = TRUE;
 782         goto validate;
 783     }
 784
 785     if (r300->dirty_state & R300_NEW_QUERY) {
 786         r300_emit_query_start(r300);
 787         r300->dirty_state &= ~R300_NEW_QUERY;
 788     }
 789
 790     if (r300->dirty_state & R300_NEW_BLEND) {
 791         r300_emit_blend_state(r300, r300->blend_state);
 792         r300->dirty_state &= ~R300_NEW_BLEND;
 793     }
 794
 795     if (r300->dirty_state & R300_NEW_BLEND_COLOR) {
 796         r300_emit_blend_color_state(r300, r300->blend_color_state);
 797         r300->dirty_state &= ~R300_NEW_BLEND_COLOR;
 798     }
 799
 800     if (r300->dirty_state & R300_NEW_CLIP) {
 801         r300_emit_clip_state(r300, &r300->clip_state);
 802         r300->dirty_state &= ~R300_NEW_CLIP;
 803     }
 804
 805     if (r300->dirty_state & R300_NEW_DSA) {
 806         r300_emit_dsa_state(r300, r300->dsa_state);
 807         r300->dirty_state &= ~R300_NEW_DSA;
 808     }
 809
 810     if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
 811         if (r300screen->caps->is_r500) {
 812             r500_emit_fragment_program_code(r300, &r300->fs->code, &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
 813         } else {
 814             r300_emit_fragment_program_code(r300, &r300->fs->code, &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
 815         }
 816         r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
 817     }
 818
 819     if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
 820         r300_emit_fb_state(r300, &r300->framebuffer_state);
 821         r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
 822     }
 823
 824     if (r300->dirty_state & R300_NEW_RASTERIZER) {
 825         r300_emit_rs_state(r300, r300->rs_state);
 826         r300->dirty_state &= ~R300_NEW_RASTERIZER;
 827     }
 828
 829     if (r300->dirty_state & R300_NEW_RS_BLOCK) {
 830         r300_emit_rs_block_state(r300, r300->rs_block);
 831         r300->dirty_state &= ~R300_NEW_RS_BLOCK;
 832     }
 833
 834     if (r300->dirty_state & R300_NEW_SCISSOR) {
 835         r300_emit_scissor_state(r300, r300->scissor_state);
 836         r300->dirty_state &= ~R300_NEW_SCISSOR;
 837     }
 838
 839     /* Samplers and textures are tracked separately but emitted together. */
 840     if (r300->dirty_state &
 841             (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
 842         for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
 843             if (r300->dirty_state &
 844                 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
 845                 if (r300->textures[i])
 846                     r300_emit_texture(r300,
 847                                       r300->sampler_states[i],
 848                                       r300->textures[i],
 849                                       i);
 850                 r300->dirty_state &=
 851                     ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
 852                 dirty_tex++;
 853             }
 854         }
 855         r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
 856     }
 857
 858     if (r300->dirty_state & R300_NEW_VIEWPORT) {
 859         r300_emit_viewport_state(r300, r300->viewport_state);
 860         r300->dirty_state &= ~R300_NEW_VIEWPORT;
 861     }
 862
 863     if (dirty_tex) {
 864         r300_flush_textures(r300);
 865     }
 866
 867     if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
 868         r300_emit_vertex_format_state(r300);
 869         r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
 870     }
 871
 872     if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
 873         r300_emit_vertex_shader(r300, r300->vs);
 874         r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
 875     }
 876
 877     /* XXX
 878     assert(r300->dirty_state == 0);
 879     */
 880
 881     /* Finally, emit the VBO. */
 882     r300_emit_vertex_buffer(r300);
 883
 884     r300->dirty_hw++;
 885 }