2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
30 #include "r300_context.h"
33 #include "r300_emit.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
39 void r300_emit_blend_state(struct r300_context
* r300
,
40 unsigned size
, void* state
)
42 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
43 struct pipe_framebuffer_state
* fb
=
44 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
48 WRITE_CS_TABLE(blend
->cb
, size
);
50 WRITE_CS_TABLE(blend
->cb_no_readwrite
, size
);
54 void r300_emit_blend_color_state(struct r300_context
* r300
,
55 unsigned size
, void* state
)
57 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
60 WRITE_CS_TABLE(bc
->cb
, size
);
63 void r300_emit_clip_state(struct r300_context
* r300
,
64 unsigned size
, void* state
)
66 struct r300_clip_state
* clip
= (struct r300_clip_state
*)state
;
69 WRITE_CS_TABLE(clip
->cb
, size
);
72 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
74 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
75 struct pipe_framebuffer_state
* fb
=
76 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
80 if (fb
->nr_cbufs
&& fb
->cbufs
[0]->format
== PIPE_FORMAT_R16G16B16A16_FLOAT
)
81 WRITE_CS_TABLE(&dsa
->cb_begin_fp16
, size
);
83 WRITE_CS_TABLE(&dsa
->cb_begin
, size
);
85 if (fb
->nr_cbufs
&& fb
->cbufs
[0]->format
== PIPE_FORMAT_R16G16B16A16_FLOAT
)
86 WRITE_CS_TABLE(dsa
->cb_fp16_zb_no_readwrite
, size
);
88 WRITE_CS_TABLE(dsa
->cb_zb_no_readwrite
, size
);
92 static void get_rc_constant_state(
94 struct r300_context
* r300
,
95 struct rc_constant
* constant
)
97 struct r300_textures_state
* texstate
= r300
->textures_state
.state
;
98 struct r300_resource
*tex
;
100 assert(constant
->Type
== RC_CONSTANT_STATE
);
102 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
103 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
106 switch (constant
->u
.State
[0]) {
107 /* Factor for converting rectangle coords to
108 * normalized coords. Should only show up on non-r500. */
109 case RC_STATE_R300_TEXRECT_FACTOR
:
110 tex
= r300_resource(texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
);
111 vec
[0] = 1.0 / tex
->tex
.width0
;
112 vec
[1] = 1.0 / tex
->tex
.height0
;
117 case RC_STATE_R300_TEXSCALE_FACTOR
:
118 tex
= r300_resource(texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
);
119 /* Add a small number to the texture size to work around rounding errors in hw. */
120 vec
[0] = tex
->b
.b
.b
.width0
/ (tex
->tex
.width0
+ 0.001f
);
121 vec
[1] = tex
->b
.b
.b
.height0
/ (tex
->tex
.height0
+ 0.001f
);
122 vec
[2] = tex
->b
.b
.b
.depth0
/ (tex
->tex
.depth0
+ 0.001f
);
126 case RC_STATE_R300_VIEWPORT_SCALE
:
127 vec
[0] = r300
->viewport
.scale
[0];
128 vec
[1] = r300
->viewport
.scale
[1];
129 vec
[2] = r300
->viewport
.scale
[2];
133 case RC_STATE_R300_VIEWPORT_OFFSET
:
134 vec
[0] = r300
->viewport
.translate
[0];
135 vec
[1] = r300
->viewport
.translate
[1];
136 vec
[2] = r300
->viewport
.translate
[2];
141 fprintf(stderr
, "r300: Implementation error: "
142 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
150 /* Convert a normal single-precision float into the 7.16 format
151 * used by the R300 fragment shader.
153 uint32_t pack_float24(float f
)
161 uint32_t float24
= 0;
168 mantissa
= frexpf(f
, &exponent
);
172 float24
|= (1 << 23);
173 mantissa
= mantissa
* -1.0;
175 /* Handle exponent, bias of 63 */
177 float24
|= (exponent
<< 16);
178 /* Kill 7 LSB of mantissa */
179 float24
|= (u
.u
& 0x7FFFFF) >> 7;
184 void r300_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
186 struct r300_fragment_shader
*fs
= r300_fs(r300
);
189 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
192 void r300_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
194 struct r300_fragment_shader
*fs
= r300_fs(r300
);
195 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
196 unsigned count
= fs
->shader
->externals_count
;
204 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, count
* 4);
205 if (buf
->remap_table
){
206 for (i
= 0; i
< count
; i
++) {
207 float *data
= (float*)&buf
->ptr
[buf
->remap_table
[i
]*4];
208 for (j
= 0; j
< 4; j
++)
209 OUT_CS(pack_float24(data
[j
]));
212 for (i
= 0; i
< count
; i
++)
213 for (j
= 0; j
< 4; j
++)
214 OUT_CS(pack_float24(*(float*)&buf
->ptr
[i
*4+j
]));
220 void r300_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
222 struct r300_fragment_shader
*fs
= r300_fs(r300
);
223 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
225 unsigned count
= fs
->shader
->rc_state_count
;
226 unsigned first
= fs
->shader
->externals_count
;
227 unsigned end
= constants
->Count
;
235 for(i
= first
; i
< end
; ++i
) {
236 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
239 get_rc_constant_state(data
, r300
, &constants
->Constants
[i
]);
241 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
242 for (j
= 0; j
< 4; j
++)
243 OUT_CS(pack_float24(data
[j
]));
249 void r500_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
251 struct r300_fragment_shader
*fs
= r300_fs(r300
);
254 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
257 void r500_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
259 struct r300_fragment_shader
*fs
= r300_fs(r300
);
260 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
261 unsigned count
= fs
->shader
->externals_count
;
268 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
269 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, count
* 4);
270 if (buf
->remap_table
){
271 for (unsigned i
= 0; i
< count
; i
++) {
272 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
273 OUT_CS_TABLE(data
, 4);
276 OUT_CS_TABLE(buf
->ptr
, count
* 4);
281 void r500_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
283 struct r300_fragment_shader
*fs
= r300_fs(r300
);
284 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
286 unsigned count
= fs
->shader
->rc_state_count
;
287 unsigned first
= fs
->shader
->externals_count
;
288 unsigned end
= constants
->Count
;
295 for(i
= first
; i
< end
; ++i
) {
296 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
299 get_rc_constant_state(data
, r300
, &constants
->Constants
[i
]);
301 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
302 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
303 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
304 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
305 OUT_CS_TABLE(data
, 4);
311 void r300_emit_gpu_flush(struct r300_context
*r300
, unsigned size
, void *state
)
313 struct r300_gpu_flush
*gpuflush
= (struct r300_gpu_flush
*)state
;
314 struct pipe_framebuffer_state
* fb
=
315 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
316 uint32_t height
= fb
->height
;
317 uint32_t width
= fb
->width
;
320 if (r300
->cbzb_clear
) {
321 struct r300_surface
*surf
= r300_surface(fb
->cbufs
[0]);
323 height
= surf
->cbzb_height
;
324 width
= surf
->cbzb_width
;
327 DBG(r300
, DBG_SCISSOR
,
328 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
329 width
, height
, r300
->cbzb_clear
? "YES" : "NO");
334 * By writing to the SC registers, SC & US assert idle. */
335 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
336 if (r300
->screen
->caps
.is_r500
) {
338 OUT_CS(((width
- 1) << R300_SCISSORS_X_SHIFT
) |
339 ((height
- 1) << R300_SCISSORS_Y_SHIFT
));
341 OUT_CS((1440 << R300_SCISSORS_X_SHIFT
) |
342 (1440 << R300_SCISSORS_Y_SHIFT
));
343 OUT_CS(((width
+ 1440-1) << R300_SCISSORS_X_SHIFT
) |
344 ((height
+ 1440-1) << R300_SCISSORS_Y_SHIFT
));
347 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
348 OUT_CS_TABLE(gpuflush
->cb_flush_clean
, 6);
352 void r300_emit_aa_state(struct r300_context
*r300
, unsigned size
, void *state
)
354 struct r300_aa_state
*aa
= (struct r300_aa_state
*)state
;
358 OUT_CS_REG(R300_GB_AA_CONFIG
, aa
->aa_config
);
361 OUT_CS_REG(R300_RB3D_AARESOLVE_OFFSET
, aa
->dest
->offset
);
362 OUT_CS_RELOC(aa
->dest
);
363 OUT_CS_REG(R300_RB3D_AARESOLVE_PITCH
, aa
->dest
->pitch
);
366 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL
, aa
->aaresolve_ctl
);
370 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
372 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
373 struct r300_surface
* surf
;
375 boolean can_hyperz
= r300
->rws
->get_value(r300
->rws
, R300_CAN_HYPERZ
);
376 uint32_t rb3d_cctl
= 0;
382 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
383 * what we usually want. */
384 if (r300
->screen
->caps
.is_r500
) {
385 rb3d_cctl
= R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
;
388 r300_fragment_shader_writes_all(r300_fs(r300
))) {
389 rb3d_cctl
|= R300_RB3D_CCTL_NUM_MULTIWRITES(fb
->nr_cbufs
);
392 OUT_CS_REG(R300_RB3D_CCTL
, rb3d_cctl
);
394 /* Set up colorbuffers. */
395 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
396 surf
= r300_surface(fb
->cbufs
[i
]);
398 OUT_CS_REG(R300_RB3D_COLOROFFSET0
+ (4 * i
), surf
->offset
);
401 OUT_CS_REG(R300_RB3D_COLORPITCH0
+ (4 * i
), surf
->pitch
);
405 /* Set up the ZB part of the CBZB clear. */
406 if (r300
->cbzb_clear
) {
407 surf
= r300_surface(fb
->cbufs
[0]);
409 OUT_CS_REG(R300_ZB_FORMAT
, surf
->cbzb_format
);
411 OUT_CS_REG(R300_ZB_DEPTHOFFSET
, surf
->cbzb_midpoint_offset
);
414 OUT_CS_REG(R300_ZB_DEPTHPITCH
, surf
->cbzb_pitch
);
418 "CBZB clearing cbuf %08x %08x\n", surf
->cbzb_format
,
421 /* Set up a zbuffer. */
422 else if (fb
->zsbuf
) {
423 surf
= r300_surface(fb
->zsbuf
);
425 OUT_CS_REG(R300_ZB_FORMAT
, surf
->format
);
427 OUT_CS_REG(R300_ZB_DEPTHOFFSET
, surf
->offset
);
430 OUT_CS_REG(R300_ZB_DEPTHPITCH
, surf
->pitch
);
435 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, 0);
436 OUT_CS_REG(R300_ZB_HIZ_PITCH
, surf
->pitch_hiz
);
437 /* Z Mask RAM. (compressed zbuffer) */
438 OUT_CS_REG(R300_ZB_ZMASK_OFFSET
, 0);
439 OUT_CS_REG(R300_ZB_ZMASK_PITCH
, surf
->pitch_zmask
);
446 void r300_emit_hyperz_state(struct r300_context
*r300
,
447 unsigned size
, void *state
)
449 struct r300_hyperz_state
*z
= state
;
453 WRITE_CS_TABLE(&z
->cb_flush_begin
, size
);
455 WRITE_CS_TABLE(&z
->cb_begin
, size
- 2);
458 void r300_emit_hyperz_end(struct r300_context
*r300
)
460 struct r300_hyperz_state z
=
461 *(struct r300_hyperz_state
*)r300
->hyperz_state
.state
;
465 z
.zb_depthclearvalue
= 0;
466 z
.sc_hyperz
= R300_SC_HYPERZ_ADJ_2
;
467 z
.gb_z_peq_config
= 0;
469 r300_emit_hyperz_state(r300
, r300
->hyperz_state
.size
, &z
);
472 void r300_emit_fb_state_pipelined(struct r300_context
*r300
,
473 unsigned size
, void *state
)
475 struct pipe_framebuffer_state
* fb
=
476 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
477 unsigned i
, num_cbufs
= fb
->nr_cbufs
;
478 unsigned mspos0
, mspos1
;
481 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be
482 * marked as UNUSED in the US block. */
483 if (r300_fragment_shader_writes_all(r300_fs(r300
))) {
484 num_cbufs
= MIN2(num_cbufs
, 1);
489 /* Colorbuffer format in the US block.
490 * (must be written after unpipelined regs) */
491 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0
, 4);
492 for (i
= 0; i
< num_cbufs
; i
++) {
493 OUT_CS(r300_surface(fb
->cbufs
[i
])->format
);
496 OUT_CS(R300_US_OUT_FMT_UNUSED
);
499 /* Multisampling. Depends on framebuffer sample count.
500 * These are pipelined regs and as such cannot be moved
501 * to the AA state. */
505 if (fb
->nr_cbufs
&& fb
->cbufs
[0]->texture
->nr_samples
> 1) {
506 /* Subsample placement. These may not be optimal. */
507 switch (fb
->cbufs
[0]->texture
->nr_samples
) {
525 debug_printf("r300: Bad number of multisamples!\n");
529 OUT_CS_REG_SEQ(R300_GB_MSPOS0
, 2);
535 void r300_emit_query_start(struct r300_context
*r300
, unsigned size
, void*state
)
537 struct r300_query
*query
= r300
->query_current
;
544 if (r300
->screen
->caps
.family
== CHIP_FAMILY_RV530
) {
545 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
547 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
549 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
551 query
->begin_emitted
= TRUE
;
554 static void r300_emit_query_end_frag_pipes(struct r300_context
*r300
,
555 struct r300_query
*query
)
557 struct r300_capabilities
* caps
= &r300
->screen
->caps
;
560 assert(caps
->num_frag_pipes
);
562 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
563 /* I'm not so sure I like this switch, but it's hard to be elegant
564 * when there's so many special cases...
566 * So here's the basic idea. For each pipe, enable writes to it only,
567 * then put out the relocation for ZPASS_ADDR, taking into account a
568 * 4-byte offset for each pipe. RV380 and older are special; they have
569 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
570 * so there's a chipset cap for that. */
571 switch (caps
->num_frag_pipes
) {
574 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
575 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 3) * 4);
576 OUT_CS_RELOC(r300
->query_current
);
579 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
580 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 2) * 4);
581 OUT_CS_RELOC(r300
->query_current
);
584 /* As mentioned above, accomodate RV380 and older. */
585 OUT_CS_REG(R300_SU_REG_DEST
,
586 1 << (caps
->high_second_pipe
? 3 : 1));
587 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 1) * 4);
588 OUT_CS_RELOC(r300
->query_current
);
591 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
592 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 0) * 4);
593 OUT_CS_RELOC(r300
->query_current
);
596 fprintf(stderr
, "r300: Implementation error: Chipset reports %d"
597 " pixel pipes!\n", caps
->num_frag_pipes
);
601 /* And, finally, reset it to normal... */
602 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
606 static void rv530_emit_query_end_single_z(struct r300_context
*r300
,
607 struct r300_query
*query
)
612 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
613 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, query
->num_results
* 4);
614 OUT_CS_RELOC(r300
->query_current
);
615 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
619 static void rv530_emit_query_end_double_z(struct r300_context
*r300
,
620 struct r300_query
*query
)
625 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
626 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 0) * 4);
627 OUT_CS_RELOC(r300
->query_current
);
628 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
629 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 1) * 4);
630 OUT_CS_RELOC(r300
->query_current
);
631 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
635 void r300_emit_query_end(struct r300_context
* r300
)
637 struct r300_capabilities
*caps
= &r300
->screen
->caps
;
638 struct r300_query
*query
= r300
->query_current
;
643 if (query
->begin_emitted
== FALSE
)
646 if (caps
->family
== CHIP_FAMILY_RV530
) {
647 if (caps
->num_z_pipes
== 2)
648 rv530_emit_query_end_double_z(r300
, query
);
650 rv530_emit_query_end_single_z(r300
, query
);
652 r300_emit_query_end_frag_pipes(r300
, query
);
654 query
->begin_emitted
= FALSE
;
655 query
->num_results
+= query
->num_pipes
;
657 /* XXX grab all the results and reset the counter. */
658 if (query
->num_results
>= query
->buffer_size
/ 4 - 4) {
659 query
->num_results
= (query
->buffer_size
/ 4) / 2;
660 fprintf(stderr
, "r300: Rewinding OQBO...\n");
664 void r300_emit_invariant_state(struct r300_context
*r300
,
665 unsigned size
, void *state
)
668 WRITE_CS_TABLE(state
, size
);
671 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
673 struct r300_rs_state
* rs
= state
;
677 OUT_CS_TABLE(rs
->cb_main
, RS_STATE_MAIN_SIZE
);
678 if (rs
->polygon_offset_enable
) {
679 if (r300
->zbuffer_bpp
== 16) {
680 OUT_CS_TABLE(rs
->cb_poly_offset_zb16
, 5);
682 OUT_CS_TABLE(rs
->cb_poly_offset_zb24
, 5);
688 void r300_emit_rs_block_state(struct r300_context
* r300
,
689 unsigned size
, void* state
)
691 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
693 /* It's the same for both INST and IP tables */
694 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
697 if (DBG_ON(r300
, DBG_RS_BLOCK
)) {
698 r500_dump_rs_block(rs
);
700 fprintf(stderr
, "r300: RS emit:\n");
702 for (i
= 0; i
< count
; i
++)
703 fprintf(stderr
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
705 for (i
= 0; i
< count
; i
++)
706 fprintf(stderr
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
708 fprintf(stderr
, " : count: 0x%08x inst_count: 0x%08x\n",
709 rs
->count
, rs
->inst_count
);
713 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
714 OUT_CS(rs
->vap_vtx_state_cntl
);
715 OUT_CS(rs
->vap_vsm_vtx_assm
);
716 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
717 OUT_CS(rs
->vap_out_vtx_fmt
[0]);
718 OUT_CS(rs
->vap_out_vtx_fmt
[1]);
719 OUT_CS_REG_SEQ(R300_GB_ENABLE
, 1);
720 OUT_CS(rs
->gb_enable
);
722 if (r300
->screen
->caps
.is_r500
) {
723 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
725 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
727 OUT_CS_TABLE(rs
->ip
, count
);
729 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
731 OUT_CS(rs
->inst_count
);
733 if (r300
->screen
->caps
.is_r500
) {
734 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
736 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
738 OUT_CS_TABLE(rs
->inst
, count
);
742 void r300_emit_scissor_state(struct r300_context
* r300
,
743 unsigned size
, void* state
)
745 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
749 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0
, 2);
750 if (r300
->screen
->caps
.is_r500
) {
751 OUT_CS((scissor
->minx
<< R300_CLIPRECT_X_SHIFT
) |
752 (scissor
->miny
<< R300_CLIPRECT_Y_SHIFT
));
753 OUT_CS(((scissor
->maxx
- 1) << R300_CLIPRECT_X_SHIFT
) |
754 ((scissor
->maxy
- 1) << R300_CLIPRECT_Y_SHIFT
));
756 OUT_CS(((scissor
->minx
+ 1440) << R300_CLIPRECT_X_SHIFT
) |
757 ((scissor
->miny
+ 1440) << R300_CLIPRECT_Y_SHIFT
));
758 OUT_CS(((scissor
->maxx
+ 1440-1) << R300_CLIPRECT_X_SHIFT
) |
759 ((scissor
->maxy
+ 1440-1) << R300_CLIPRECT_Y_SHIFT
));
764 void r300_emit_textures_state(struct r300_context
*r300
,
765 unsigned size
, void *state
)
767 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
768 struct r300_texture_sampler_state
*texstate
;
769 struct r300_resource
*tex
;
774 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
776 for (i
= 0; i
< allstate
->count
; i
++) {
777 if ((1 << i
) & allstate
->tx_enable
) {
778 texstate
= &allstate
->regs
[i
];
779 tex
= r300_resource(allstate
->sampler_views
[i
]->base
.texture
);
781 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter0
);
782 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter1
);
783 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
784 texstate
->border_color
);
786 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
.format0
);
787 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
.format1
);
788 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
.format2
);
790 OUT_CS_REG(R300_TX_OFFSET_0
+ (i
* 4), texstate
->format
.tile_config
);
797 void r300_emit_vertex_arrays(struct r300_context
* r300
, int offset
, boolean indexed
)
799 struct pipe_vertex_buffer
*vbuf
= r300
->vbuf_mgr
->vertex_buffer
;
800 struct pipe_resource
**valid_vbuf
= r300
->vbuf_mgr
->real_vertex_buffer
;
801 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
802 struct r300_resource
*buf
;
804 unsigned vertex_array_count
= r300
->velems
->count
;
805 unsigned packet_size
= (vertex_array_count
* 3 + 1) / 2;
806 struct pipe_vertex_buffer
*vb1
, *vb2
;
807 unsigned *hw_format_size
;
808 unsigned size1
, size2
;
811 BEGIN_CS(2 + packet_size
+ vertex_array_count
* 2);
812 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
813 OUT_CS(vertex_array_count
| (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
815 hw_format_size
= r300
->velems
->format_size
;
817 for (i
= 0; i
< vertex_array_count
- 1; i
+= 2) {
818 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
819 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
820 size1
= hw_format_size
[i
];
821 size2
= hw_format_size
[i
+1];
823 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
824 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
825 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
826 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
829 if (vertex_array_count
& 1) {
830 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
831 size1
= hw_format_size
[i
];
833 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
834 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
837 for (i
= 0; i
< vertex_array_count
; i
++) {
838 buf
= r300_resource(valid_vbuf
[velem
[i
].vertex_buffer_index
]);
844 void r300_emit_vertex_arrays_swtcl(struct r300_context
*r300
, boolean indexed
)
848 DBG(r300
, DBG_SWTCL
, "r300: Preparing vertex buffer %p for render, "
849 "vertex size %d\n", r300
->vbo
,
850 r300
->vertex_info
.size
);
851 /* Set the pointer to our vertex buffer. The emitted values are this:
852 * PACKET3 [3D_LOAD_VBPNTR]
854 * FORMAT [size | stride << 8]
855 * OFFSET [offset into BO]
856 * VBPNTR [relocated BO]
859 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
860 OUT_CS(1 | (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
861 OUT_CS(r300
->vertex_info
.size
|
862 (r300
->vertex_info
.size
<< 8));
863 OUT_CS(r300
->draw_vbo_offset
);
865 OUT_CS_RELOC(r300_resource(r300
->vbo
));
869 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
870 unsigned size
, void* state
)
872 struct r300_vertex_stream_state
*streams
=
873 (struct r300_vertex_stream_state
*)state
;
877 if (DBG_ON(r300
, DBG_PSC
)) {
878 fprintf(stderr
, "r300: PSC emit:\n");
880 for (i
= 0; i
< streams
->count
; i
++) {
881 fprintf(stderr
, " : prog_stream_cntl%d: 0x%08x\n", i
,
882 streams
->vap_prog_stream_cntl
[i
]);
885 for (i
= 0; i
< streams
->count
; i
++) {
886 fprintf(stderr
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
887 streams
->vap_prog_stream_cntl_ext
[i
]);
892 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
893 OUT_CS_TABLE(streams
->vap_prog_stream_cntl
, streams
->count
);
894 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
895 OUT_CS_TABLE(streams
->vap_prog_stream_cntl_ext
, streams
->count
);
899 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
904 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
908 void r300_emit_vap_invariant_state(struct r300_context
*r300
,
909 unsigned size
, void *state
)
912 WRITE_CS_TABLE(state
, size
);
915 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
917 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
918 struct r300_vertex_program_code
* code
= &vs
->code
;
919 struct r300_screen
* r300screen
= r300
->screen
;
920 unsigned instruction_count
= code
->length
/ 4;
922 unsigned vtx_mem_size
= r300screen
->caps
.is_r500
? 128 : 72;
923 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
924 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
925 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
927 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
928 vtx_mem_size
/ output_count
, 10);
929 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 5);
935 /* R300_VAP_PVS_CODE_CNTL_0
936 * R300_VAP_PVS_CONST_CNTL
937 * R300_VAP_PVS_CODE_CNTL_1
938 * See the r5xx docs for instructions on how to use these. */
939 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0
, R300_PVS_FIRST_INST(0) |
940 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
941 R300_PVS_LAST_INST(instruction_count
- 1));
942 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1
, instruction_count
- 1);
944 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
945 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
946 OUT_CS_TABLE(code
->body
.d
, code
->length
);
948 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
949 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
950 R300_PVS_NUM_FPUS(r300screen
->caps
.num_vert_fpus
) |
951 R300_PVS_VF_MAX_VTX_NUM(12) |
952 (r300screen
->caps
.is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
954 /* Emit flow control instructions. */
955 if (code
->num_fc_ops
) {
957 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC
, code
->fc_ops
);
958 if (r300screen
->caps
.is_r500
) {
959 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0
, code
->num_fc_ops
* 2);
960 OUT_CS_TABLE(code
->fc_op_addrs
.r500
, code
->num_fc_ops
* 2);
962 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0
, code
->num_fc_ops
);
963 OUT_CS_TABLE(code
->fc_op_addrs
.r300
, code
->num_fc_ops
);
965 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
, code
->num_fc_ops
);
966 OUT_CS_TABLE(code
->fc_loop_index
, code
->num_fc_ops
);
972 void r300_emit_vs_constants(struct r300_context
* r300
,
973 unsigned size
, void *state
)
976 ((struct r300_vertex_shader
*)r300
->vs_state
.state
)->externals_count
;
977 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
978 struct r300_vertex_shader
*vs
= (struct r300_vertex_shader
*)r300
->vs_state
.state
;
980 int imm_first
= vs
->externals_count
;
981 int imm_end
= vs
->code
.constants
.Count
;
982 int imm_count
= vs
->immediates_count
;
986 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL
,
987 R300_PVS_CONST_BASE_OFFSET(buf
->buffer_base
) |
988 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end
- 1, 0)));
989 if (vs
->externals_count
) {
990 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
991 (r300
->screen
->caps
.is_r500
?
992 R500_PVS_CONST_START
: R300_PVS_CONST_START
) + buf
->buffer_base
);
993 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, count
* 4);
994 if (buf
->remap_table
){
995 for (i
= 0; i
< count
; i
++) {
996 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
997 OUT_CS_TABLE(data
, 4);
1000 OUT_CS_TABLE(buf
->ptr
, count
* 4);
1004 /* Emit immediates. */
1006 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1007 (r300
->screen
->caps
.is_r500
?
1008 R500_PVS_CONST_START
: R300_PVS_CONST_START
) +
1009 buf
->buffer_base
+ imm_first
);
1010 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, imm_count
* 4);
1011 for (i
= imm_first
; i
< imm_end
; i
++) {
1012 const float *data
= vs
->code
.constants
.Constants
[i
].u
.Immediate
;
1013 OUT_CS_TABLE(data
, 4);
1019 void r300_emit_viewport_state(struct r300_context
* r300
,
1020 unsigned size
, void* state
)
1022 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
1026 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
1027 OUT_CS_TABLE(&viewport
->xscale
, 6);
1028 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
1032 void r300_emit_hiz_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1034 struct pipe_framebuffer_state
*fb
=
1035 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1036 struct r300_resource
* tex
;
1039 tex
= r300_resource(fb
->zsbuf
->texture
);
1042 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ
, 2);
1044 OUT_CS(tex
->tex
.hiz_dwords
[fb
->zsbuf
->u
.tex
.level
]);
1045 OUT_CS(r300
->hiz_clear_value
);
1048 /* Mark the current zbuffer's hiz ram as in use. */
1049 r300
->hiz_in_use
= TRUE
;
1050 r300
->hiz_func
= HIZ_FUNC_NONE
;
1051 r300_mark_atom_dirty(r300
, &r300
->hyperz_state
);
1054 void r300_emit_zmask_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1056 struct pipe_framebuffer_state
*fb
=
1057 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1058 struct r300_resource
*tex
;
1061 tex
= r300_resource(fb
->zsbuf
->texture
);
1064 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK
, 2);
1066 OUT_CS(tex
->tex
.zmask_dwords
[fb
->zsbuf
->u
.tex
.level
]);
1070 /* Mark the current zbuffer's zmask as in use. */
1071 r300
->zmask_in_use
= TRUE
;
1072 r300_mark_atom_dirty(r300
, &r300
->hyperz_state
);
1075 void r300_emit_ztop_state(struct r300_context
* r300
,
1076 unsigned size
, void* state
)
1078 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
1082 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
1086 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
1091 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
1095 boolean
r300_emit_buffer_validate(struct r300_context
*r300
,
1096 boolean do_validate_vertex_buffers
,
1097 struct pipe_resource
*index_buffer
)
1099 struct pipe_framebuffer_state
*fb
=
1100 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1101 struct r300_textures_state
*texstate
=
1102 (struct r300_textures_state
*)r300
->textures_state
.state
;
1103 struct r300_resource
*tex
;
1105 boolean flushed
= FALSE
;
1108 if (r300
->fb_state
.dirty
) {
1109 /* Color buffers... */
1110 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1111 tex
= r300_resource(fb
->cbufs
[i
]->texture
);
1112 assert(tex
&& tex
->buf
&& "cbuf is marked, but NULL!");
1113 r300
->rws
->cs_add_reloc(r300
->cs
, tex
->cs_buf
, 0,
1114 r300_surface(fb
->cbufs
[i
])->domain
);
1116 /* ...depth buffer... */
1118 tex
= r300_resource(fb
->zsbuf
->texture
);
1119 assert(tex
&& tex
->buf
&& "zsbuf is marked, but NULL!");
1120 r300
->rws
->cs_add_reloc(r300
->cs
, tex
->cs_buf
, 0,
1121 r300_surface(fb
->zsbuf
)->domain
);
1124 if (r300
->textures_state
.dirty
) {
1125 /* ...textures... */
1126 for (i
= 0; i
< texstate
->count
; i
++) {
1127 if (!(texstate
->tx_enable
& (1 << i
))) {
1131 tex
= r300_resource(texstate
->sampler_views
[i
]->base
.texture
);
1132 r300
->rws
->cs_add_reloc(r300
->cs
, tex
->cs_buf
, tex
->domain
, 0);
1135 /* ...occlusion query buffer... */
1136 if (r300
->query_current
)
1137 r300
->rws
->cs_add_reloc(r300
->cs
, r300
->query_current
->cs_buf
,
1138 0, r300
->query_current
->domain
);
1139 /* ...vertex buffer for SWTCL path... */
1141 r300
->rws
->cs_add_reloc(r300
->cs
, r300_resource(r300
->vbo
)->cs_buf
,
1142 r300_resource(r300
->vbo
)->domain
, 0);
1143 /* ...vertex buffers for HWTCL path... */
1144 if (do_validate_vertex_buffers
&& r300
->vertex_arrays_dirty
) {
1145 struct pipe_resource
**buf
= r300
->vbuf_mgr
->real_vertex_buffer
;
1146 struct pipe_resource
**last
= r300
->vbuf_mgr
->real_vertex_buffer
+
1147 r300
->vbuf_mgr
->nr_real_vertex_buffers
;
1148 for (; buf
!= last
; buf
++) {
1152 r300
->rws
->cs_add_reloc(r300
->cs
, r300_resource(*buf
)->cs_buf
,
1153 r300_resource(*buf
)->domain
, 0);
1156 /* ...and index buffer for HWTCL path. */
1158 r300
->rws
->cs_add_reloc(r300
->cs
, r300_resource(index_buffer
)->cs_buf
,
1159 r300_resource(index_buffer
)->domain
, 0);
1161 /* Now do the validation. */
1162 if (!r300
->rws
->cs_validate(r300
->cs
)) {
1163 /* Ooops, an infinite loop, give up. */
1167 r300
->context
.flush(&r300
->context
, 0, NULL
);
1175 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
1177 struct r300_atom
* atom
;
1178 unsigned dwords
= 0;
1180 foreach_dirty_atom(r300
, atom
) {
1182 dwords
+= atom
->size
;
1186 /* let's reserve some more, just in case */
1192 unsigned r300_get_num_cs_end_dwords(struct r300_context
*r300
)
1194 unsigned dwords
= 0;
1196 /* Emitted in flush. */
1197 dwords
+= 26; /* emit_query_end */
1198 dwords
+= r300
->hyperz_state
.size
+ 2; /* emit_hyperz_end + zcache flush */
1199 if (r300
->screen
->caps
.is_r500
)
1205 /* Emit all dirty state. */
1206 void r300_emit_dirty_state(struct r300_context
* r300
)
1208 struct r300_atom
*atom
;
1210 foreach_dirty_atom(r300
, atom
) {
1212 atom
->emit(r300
, atom
->size
, atom
->state
);
1213 atom
->dirty
= FALSE
;
1217 r300
->first_dirty
= NULL
;
1218 r300
->last_dirty
= NULL
;