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r300g: Remove unnecessary header.
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300,
39 unsigned size, void* state)
40 {
41 struct r300_blend_state* blend = (struct r300_blend_state*)state;
42 struct pipe_framebuffer_state* fb =
43 (struct pipe_framebuffer_state*)r300->fb_state.state;
44 CS_LOCALS(r300);
45
46 BEGIN_CS(size);
47 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
48 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
49 if (fb->nr_cbufs) {
50 OUT_CS(blend->blend_control);
51 OUT_CS(blend->alpha_blend_control);
52 OUT_CS(blend->color_channel_mask);
53 } else {
54 OUT_CS(0);
55 OUT_CS(0);
56 OUT_CS(0);
57 /* XXX also disable fastfill here once it's supported */
58 }
59 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
60 END_CS;
61 }
62
63 void r300_emit_blend_color_state(struct r300_context* r300,
64 unsigned size, void* state)
65 {
66 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
67 struct r300_screen* r300screen = r300_screen(r300->context.screen);
68 CS_LOCALS(r300);
69
70 if (r300screen->caps->is_r500) {
71 BEGIN_CS(size);
72 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
73 OUT_CS(bc->blend_color_red_alpha);
74 OUT_CS(bc->blend_color_green_blue);
75 END_CS;
76 } else {
77 BEGIN_CS(size);
78 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
79 END_CS;
80 }
81 }
82
83 void r300_emit_clip_state(struct r300_context* r300,
84 unsigned size, void* state)
85 {
86 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
87 int i;
88 struct r300_screen* r300screen = r300_screen(r300->context.screen);
89 CS_LOCALS(r300);
90
91 if (r300screen->caps->has_tcl) {
92 BEGIN_CS(size);
93 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
94 (r300screen->caps->is_r500 ?
95 R500_PVS_UCP_START : R300_PVS_UCP_START));
96 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
97 for (i = 0; i < 6; i++) {
98 OUT_CS_32F(clip->ucp[i][0]);
99 OUT_CS_32F(clip->ucp[i][1]);
100 OUT_CS_32F(clip->ucp[i][2]);
101 OUT_CS_32F(clip->ucp[i][3]);
102 }
103 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
104 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
105 END_CS;
106 } else {
107 BEGIN_CS(size);
108 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
109 END_CS;
110 }
111
112 }
113
114 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
115 {
116 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
117 struct r300_screen* r300screen = r300_screen(r300->context.screen);
118 struct pipe_framebuffer_state* fb =
119 (struct pipe_framebuffer_state*)r300->fb_state.state;
120 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
121 CS_LOCALS(r300);
122
123 BEGIN_CS(size);
124 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
125 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
126
127 if (fb->zsbuf) {
128 OUT_CS(dsa->z_buffer_control);
129 OUT_CS(dsa->z_stencil_control);
130 } else {
131 OUT_CS(0);
132 OUT_CS(0);
133 }
134
135 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
136
137 if (r300screen->caps->is_r500) {
138 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
139 }
140 END_CS;
141 }
142
143 static const float * get_shader_constant(
144 struct r300_context * r300,
145 struct rc_constant * constant,
146 struct r300_constant_buffer * externals)
147 {
148 struct r300_viewport_state* viewport = r300->viewport_state.state;
149 struct r300_textures_state* texstate = r300->textures_state.state;
150 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
151 struct pipe_texture *tex;
152
153 switch(constant->Type) {
154 case RC_CONSTANT_EXTERNAL:
155 return externals->constants[constant->u.External];
156
157 case RC_CONSTANT_IMMEDIATE:
158 return constant->u.Immediate;
159
160 case RC_CONSTANT_STATE:
161 switch (constant->u.State[0]) {
162 /* Factor for converting rectangle coords to
163 * normalized coords. Should only show up on non-r500. */
164 case RC_STATE_R300_TEXRECT_FACTOR:
165 tex = texstate->fragment_sampler_views[constant->u.State[1]]->texture;
166 vec[0] = 1.0 / tex->width0;
167 vec[1] = 1.0 / tex->height0;
168 break;
169
170 /* Texture compare-fail value. Shouldn't ever show up, but if
171 * it does, we'll be ready. */
172 case RC_STATE_SHADOW_AMBIENT:
173 vec[3] = 0;
174 break;
175
176 case RC_STATE_R300_VIEWPORT_SCALE:
177 vec[0] = viewport->xscale;
178 vec[1] = viewport->yscale;
179 vec[2] = viewport->zscale;
180 break;
181
182 case RC_STATE_R300_VIEWPORT_OFFSET:
183 vec[0] = viewport->xoffset;
184 vec[1] = viewport->yoffset;
185 vec[2] = viewport->zoffset;
186 break;
187
188 default:
189 debug_printf("r300: Implementation error: "
190 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
191 }
192 break;
193
194 default:
195 debug_printf("r300: Implementation error: "
196 "Unhandled constant type %d\n", constant->Type);
197 }
198
199 /* This should either be (0, 0, 0, 1), which should be a relatively safe
200 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
201 * state factors. */
202 return vec;
203 }
204
205 /* Convert a normal single-precision float into the 7.16 format
206 * used by the R300 fragment shader.
207 */
208 static uint32_t pack_float24(float f)
209 {
210 union {
211 float fl;
212 uint32_t u;
213 } u;
214 float mantissa;
215 int exponent;
216 uint32_t float24 = 0;
217
218 if (f == 0.0)
219 return 0;
220
221 u.fl = f;
222
223 mantissa = frexpf(f, &exponent);
224
225 /* Handle -ve */
226 if (mantissa < 0) {
227 float24 |= (1 << 23);
228 mantissa = mantissa * -1.0;
229 }
230 /* Handle exponent, bias of 63 */
231 exponent += 62;
232 float24 |= (exponent << 16);
233 /* Kill 7 LSB of mantissa */
234 float24 |= (u.u & 0x7FFFFF) >> 7;
235
236 return float24;
237 }
238
239 void r300_emit_fragment_program_code(struct r300_context* r300,
240 struct rX00_fragment_program_code* generic_code)
241 {
242 struct r300_fragment_program_code * code = &generic_code->code.r300;
243 int i;
244 CS_LOCALS(r300);
245
246 BEGIN_CS(15 +
247 code->alu.length * 4 +
248 (code->tex.length ? (1 + code->tex.length) : 0));
249
250 OUT_CS_REG(R300_US_CONFIG, code->config);
251 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
252 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
253
254 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
255 for(i = 0; i < 4; ++i)
256 OUT_CS(code->code_addr[i]);
257
258 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
259 for (i = 0; i < code->alu.length; i++)
260 OUT_CS(code->alu.inst[i].rgb_inst);
261
262 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
263 for (i = 0; i < code->alu.length; i++)
264 OUT_CS(code->alu.inst[i].rgb_addr);
265
266 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
267 for (i = 0; i < code->alu.length; i++)
268 OUT_CS(code->alu.inst[i].alpha_inst);
269
270 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
271 for (i = 0; i < code->alu.length; i++)
272 OUT_CS(code->alu.inst[i].alpha_addr);
273
274 if (code->tex.length) {
275 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
276 for(i = 0; i < code->tex.length; ++i)
277 OUT_CS(code->tex.inst[i]);
278 }
279
280 END_CS;
281 }
282
283 void r300_emit_fs_constant_buffer(struct r300_context* r300,
284 struct rc_constant_list* constants)
285 {
286 int i;
287 CS_LOCALS(r300);
288
289 if (constants->Count == 0)
290 return;
291
292 BEGIN_CS(constants->Count * 4 + 1);
293 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
294 for(i = 0; i < constants->Count; ++i) {
295 const float * data = get_shader_constant(r300,
296 &constants->Constants[i],
297 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
298 OUT_CS(pack_float24(data[0]));
299 OUT_CS(pack_float24(data[1]));
300 OUT_CS(pack_float24(data[2]));
301 OUT_CS(pack_float24(data[3]));
302 }
303 END_CS;
304 }
305
306 static void r300_emit_fragment_depth_config(struct r300_context* r300,
307 struct r300_fragment_shader* fs)
308 {
309 CS_LOCALS(r300);
310
311 BEGIN_CS(4);
312 if (r300_fragment_shader_writes_depth(fs)) {
313 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
314 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
315 } else {
316 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
317 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
318 }
319 END_CS;
320 }
321
322 void r500_emit_fragment_program_code(struct r300_context* r300,
323 struct rX00_fragment_program_code* generic_code)
324 {
325 struct r500_fragment_program_code * code = &generic_code->code.r500;
326 int i;
327 CS_LOCALS(r300);
328
329 BEGIN_CS(13 +
330 ((code->inst_end + 1) * 6));
331 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
332 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
333 OUT_CS_REG(R500_US_CODE_RANGE,
334 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
335 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
336 OUT_CS_REG(R500_US_CODE_ADDR,
337 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
338
339 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
340 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
341 for (i = 0; i <= code->inst_end; i++) {
342 OUT_CS(code->inst[i].inst0);
343 OUT_CS(code->inst[i].inst1);
344 OUT_CS(code->inst[i].inst2);
345 OUT_CS(code->inst[i].inst3);
346 OUT_CS(code->inst[i].inst4);
347 OUT_CS(code->inst[i].inst5);
348 }
349
350 END_CS;
351 }
352
353 void r500_emit_fs_constant_buffer(struct r300_context* r300,
354 struct rc_constant_list* constants)
355 {
356 int i;
357 CS_LOCALS(r300);
358
359 if (constants->Count == 0)
360 return;
361
362 BEGIN_CS(constants->Count * 4 + 3);
363 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
364 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
365 for (i = 0; i < constants->Count; i++) {
366 const float * data = get_shader_constant(r300,
367 &constants->Constants[i],
368 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
369 OUT_CS_32F(data[0]);
370 OUT_CS_32F(data[1]);
371 OUT_CS_32F(data[2]);
372 OUT_CS_32F(data[3]);
373 }
374 END_CS;
375 }
376
377 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
378 {
379 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
380 struct r300_screen* r300screen = r300_screen(r300->context.screen);
381 struct r300_texture* tex;
382 struct pipe_surface* surf;
383 int i;
384 CS_LOCALS(r300);
385
386 BEGIN_CS(size);
387
388 /* Flush and free renderbuffer caches. */
389 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
390 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
391 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
392 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
393 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
394 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
395
396 /* Set the number of colorbuffers. */
397 if (fb->nr_cbufs > 1) {
398 if (r300screen->caps->is_r500) {
399 OUT_CS_REG(R300_RB3D_CCTL,
400 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
401 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
402 } else {
403 OUT_CS_REG(R300_RB3D_CCTL,
404 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
405 }
406 } else {
407 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
408 }
409
410 /* Set up colorbuffers. */
411 for (i = 0; i < fb->nr_cbufs; i++) {
412 surf = fb->cbufs[i];
413 tex = (struct r300_texture*)surf->texture;
414 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
415
416 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
417 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
418
419 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
420 OUT_CS_TEX_RELOC(tex, tex->fb_state.colorpitch[surf->level],
421 0, RADEON_GEM_DOMAIN_VRAM, 0);
422
423 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
424 }
425 for (; i < 4; i++) {
426 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
427 }
428
429 /* Set up a zbuffer. */
430 if (fb->zsbuf) {
431 surf = fb->zsbuf;
432 tex = (struct r300_texture*)surf->texture;
433 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
434
435 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
436 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
437
438 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
439
440 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
441 OUT_CS_TEX_RELOC(tex, tex->fb_state.depthpitch[surf->level],
442 0, RADEON_GEM_DOMAIN_VRAM, 0);
443 }
444
445 OUT_CS_REG(R300_GA_POINT_MINMAX,
446 (MAX2(fb->width, fb->height) * 6) << R300_GA_POINT_MINMAX_MAX_SHIFT);
447 END_CS;
448 }
449
450 void r300_emit_query_start(struct r300_context *r300)
451 {
452 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
453 struct r300_query *query = r300->query_current;
454 CS_LOCALS(r300);
455
456 if (!query)
457 return;
458
459 BEGIN_CS(4);
460 if (caps->family == CHIP_FAMILY_RV530) {
461 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
462 } else {
463 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
464 }
465 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
466 END_CS;
467 query->begin_emitted = TRUE;
468 }
469
470
471 static void r300_emit_query_finish(struct r300_context *r300,
472 struct r300_query *query)
473 {
474 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
475 CS_LOCALS(r300);
476
477 assert(caps->num_frag_pipes);
478
479 BEGIN_CS(6 * caps->num_frag_pipes + 2);
480 /* I'm not so sure I like this switch, but it's hard to be elegant
481 * when there's so many special cases...
482 *
483 * So here's the basic idea. For each pipe, enable writes to it only,
484 * then put out the relocation for ZPASS_ADDR, taking into account a
485 * 4-byte offset for each pipe. RV380 and older are special; they have
486 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
487 * so there's a chipset cap for that. */
488 switch (caps->num_frag_pipes) {
489 case 4:
490 /* pipe 3 only */
491 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
492 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
493 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
494 0, RADEON_GEM_DOMAIN_GTT, 0);
495 case 3:
496 /* pipe 2 only */
497 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
498 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
499 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
500 0, RADEON_GEM_DOMAIN_GTT, 0);
501 case 2:
502 /* pipe 1 only */
503 /* As mentioned above, accomodate RV380 and older. */
504 OUT_CS_REG(R300_SU_REG_DEST,
505 1 << (caps->high_second_pipe ? 3 : 1));
506 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
507 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
508 0, RADEON_GEM_DOMAIN_GTT, 0);
509 case 1:
510 /* pipe 0 only */
511 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
512 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
513 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
514 0, RADEON_GEM_DOMAIN_GTT, 0);
515 break;
516 default:
517 debug_printf("r300: Implementation error: Chipset reports %d"
518 " pixel pipes!\n", caps->num_frag_pipes);
519 assert(0);
520 }
521
522 /* And, finally, reset it to normal... */
523 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
524 END_CS;
525 }
526
527 static void rv530_emit_query_single(struct r300_context *r300,
528 struct r300_query *query)
529 {
530 CS_LOCALS(r300);
531
532 BEGIN_CS(8);
533 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
534 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
535 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
536 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
537 END_CS;
538 }
539
540 static void rv530_emit_query_double(struct r300_context *r300,
541 struct r300_query *query)
542 {
543 CS_LOCALS(r300);
544
545 BEGIN_CS(14);
546 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
547 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
548 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
549 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
550 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
551 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
552 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
553 END_CS;
554 }
555
556 void r300_emit_query_end(struct r300_context* r300)
557 {
558 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
559 struct r300_query *query = r300->query_current;
560
561 if (!query)
562 return;
563
564 if (query->begin_emitted == FALSE)
565 return;
566
567 if (caps->family == CHIP_FAMILY_RV530) {
568 if (caps->num_z_pipes == 2)
569 rv530_emit_query_double(r300, query);
570 else
571 rv530_emit_query_single(r300, query);
572 } else
573 r300_emit_query_finish(r300, query);
574 }
575
576 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
577 {
578 struct r300_rs_state* rs = (struct r300_rs_state*)state;
579 float scale, offset;
580 CS_LOCALS(r300);
581
582 BEGIN_CS(size);
583 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
584
585 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
586
587 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
588 OUT_CS_REG(R300_GA_LINE_CNTL, rs->line_control);
589
590 if (rs->polygon_offset_enable) {
591 scale = rs->depth_scale * 12;
592 offset = rs->depth_offset;
593
594 switch (r300->zbuffer_bpp) {
595 case 16:
596 offset *= 4;
597 break;
598 case 24:
599 offset *= 2;
600 break;
601 }
602
603 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
604 OUT_CS_32F(scale);
605 OUT_CS_32F(offset);
606 OUT_CS_32F(scale);
607 OUT_CS_32F(offset);
608 }
609
610 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
611 OUT_CS(rs->polygon_offset_enable);
612 OUT_CS(rs->cull_mode);
613 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
614 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
615 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
616 END_CS;
617 }
618
619 void r300_emit_rs_block_state(struct r300_context* r300,
620 unsigned size, void* state)
621 {
622 struct r300_rs_block* rs = (struct r300_rs_block*)state;
623 unsigned i;
624 struct r300_screen* r300screen = r300_screen(r300->context.screen);
625 /* It's the same for both INST and IP tables */
626 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
627 CS_LOCALS(r300);
628
629 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
630
631 BEGIN_CS(size);
632 if (r300screen->caps->is_r500) {
633 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
634 } else {
635 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
636 }
637 for (i = 0; i < count; i++) {
638 OUT_CS(rs->ip[i]);
639 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
640 }
641
642 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
643 OUT_CS(rs->count);
644 OUT_CS(rs->inst_count);
645
646 if (r300screen->caps->is_r500) {
647 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
648 } else {
649 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
650 }
651 for (i = 0; i < count; i++) {
652 OUT_CS(rs->inst[i]);
653 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
654 }
655
656 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
657 rs->count, rs->inst_count);
658
659 END_CS;
660 }
661
662 void r300_emit_scissor_state(struct r300_context* r300,
663 unsigned size, void* state)
664 {
665 unsigned minx, miny, maxx, maxy;
666 uint32_t top_left, bottom_right;
667 struct r300_screen* r300screen = r300_screen(r300->context.screen);
668 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
669 struct pipe_framebuffer_state* fb =
670 (struct pipe_framebuffer_state*)r300->fb_state.state;
671 CS_LOCALS(r300);
672
673 minx = miny = 0;
674 maxx = fb->width;
675 maxy = fb->height;
676
677 if (r300->scissor_enabled) {
678 minx = MAX2(minx, scissor->minx);
679 miny = MAX2(miny, scissor->miny);
680 maxx = MIN2(maxx, scissor->maxx);
681 maxy = MIN2(maxy, scissor->maxy);
682 }
683
684 /* Special case for zero-area scissor.
685 *
686 * We can't allow the variables maxx and maxy to be zero because they are
687 * subtracted from later in the code, which would cause emitting ~0 and
688 * making the kernel checker angry.
689 *
690 * Let's consider we change maxx and maxy to 1, which is effectively
691 * a one-pixel area. We must then change minx and miny to a number which is
692 * greater than 1 to get the zero area back. */
693 if (!maxx || !maxy) {
694 minx = 2;
695 miny = 2;
696 maxx = 1;
697 maxy = 1;
698 }
699
700 if (r300screen->caps->is_r500) {
701 top_left =
702 (minx << R300_SCISSORS_X_SHIFT) |
703 (miny << R300_SCISSORS_Y_SHIFT);
704 bottom_right =
705 ((maxx - 1) << R300_SCISSORS_X_SHIFT) |
706 ((maxy - 1) << R300_SCISSORS_Y_SHIFT);
707 } else {
708 /* Offset of 1440 in non-R500 chipsets. */
709 top_left =
710 ((minx + 1440) << R300_SCISSORS_X_SHIFT) |
711 ((miny + 1440) << R300_SCISSORS_Y_SHIFT);
712 bottom_right =
713 (((maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
714 (((maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
715 }
716
717 BEGIN_CS(size);
718 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
719 OUT_CS(top_left);
720 OUT_CS(bottom_right);
721 END_CS;
722 }
723
724 void r300_emit_textures_state(struct r300_context *r300,
725 unsigned size, void *state)
726 {
727 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
728 struct r300_texture_sampler_state *texstate;
729 unsigned i;
730 CS_LOCALS(r300);
731
732 BEGIN_CS(size);
733 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
734
735 for (i = 0; i < allstate->count; i++) {
736 if ((1 << i) & allstate->tx_enable) {
737 texstate = &allstate->regs[i];
738
739 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter[0]);
740 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter[1]);
741 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
742 texstate->border_color);
743
744 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format[0]);
745 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format[1]);
746 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format[2]);
747
748 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
749 OUT_CS_TEX_RELOC((struct r300_texture *)allstate->fragment_sampler_views[i]->texture,
750 texstate->tile_config,
751 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
752 }
753 }
754 END_CS;
755 }
756
757 void r300_emit_aos(struct r300_context* r300, unsigned offset)
758 {
759 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
760 struct pipe_vertex_element *velem = r300->velems->velem;
761 int i;
762 unsigned size1, size2, aos_count = r300->velems->count;
763 unsigned packet_size = (aos_count * 3 + 1) / 2;
764 CS_LOCALS(r300);
765
766 BEGIN_CS(2 + packet_size + aos_count * 2);
767 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
768 OUT_CS(aos_count);
769
770 for (i = 0; i < aos_count - 1; i += 2) {
771 vb1 = &vbuf[velem[i].vertex_buffer_index];
772 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
773 size1 = util_format_get_blocksize(velem[i].src_format);
774 size2 = util_format_get_blocksize(velem[i+1].src_format);
775
776 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
777 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
778 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
779 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
780 }
781
782 if (aos_count & 1) {
783 vb1 = &vbuf[velem[i].vertex_buffer_index];
784 size1 = util_format_get_blocksize(velem[i].src_format);
785
786 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
787 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
788 }
789
790 for (i = 0; i < aos_count; i++) {
791 OUT_CS_BUF_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
792 RADEON_GEM_DOMAIN_GTT, 0, 0);
793 }
794 END_CS;
795 }
796
797 void r300_emit_vertex_buffer(struct r300_context* r300)
798 {
799 CS_LOCALS(r300);
800
801 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
802 "vertex size %d\n", r300->vbo,
803 r300->vertex_info.size);
804 /* Set the pointer to our vertex buffer. The emitted values are this:
805 * PACKET3 [3D_LOAD_VBPNTR]
806 * COUNT [1]
807 * FORMAT [size | stride << 8]
808 * OFFSET [offset into BO]
809 * VBPNTR [relocated BO]
810 */
811 BEGIN_CS(7);
812 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
813 OUT_CS(1);
814 OUT_CS(r300->vertex_info.size |
815 (r300->vertex_info.size << 8));
816 OUT_CS(r300->vbo_offset);
817 OUT_CS_BUF_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
818 END_CS;
819 }
820
821 void r300_emit_vertex_stream_state(struct r300_context* r300,
822 unsigned size, void* state)
823 {
824 struct r300_vertex_stream_state *streams =
825 (struct r300_vertex_stream_state*)state;
826 unsigned i;
827 CS_LOCALS(r300);
828
829 DBG(r300, DBG_DRAW, "r300: PSC emit:\n");
830
831 BEGIN_CS(size);
832 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
833 for (i = 0; i < streams->count; i++) {
834 OUT_CS(streams->vap_prog_stream_cntl[i]);
835 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
836 streams->vap_prog_stream_cntl[i]);
837 }
838 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
839 for (i = 0; i < streams->count; i++) {
840 OUT_CS(streams->vap_prog_stream_cntl_ext[i]);
841 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
842 streams->vap_prog_stream_cntl_ext[i]);
843 }
844 END_CS;
845 }
846
847 void r300_emit_vap_output_state(struct r300_context* r300,
848 unsigned size, void* state)
849 {
850 struct r300_vap_output_state *vap_out_state =
851 (struct r300_vap_output_state*)state;
852 CS_LOCALS(r300);
853
854 DBG(r300, DBG_DRAW, "r300: VAP emit:\n");
855
856 BEGIN_CS(size);
857 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
858 OUT_CS(vap_out_state->vap_vtx_state_cntl);
859 OUT_CS(vap_out_state->vap_vsm_vtx_assm);
860 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
861 OUT_CS(vap_out_state->vap_out_vtx_fmt[0]);
862 OUT_CS(vap_out_state->vap_out_vtx_fmt[1]);
863 END_CS;
864 }
865
866 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
867 {
868 CS_LOCALS(r300);
869
870 BEGIN_CS(size);
871 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
872 END_CS;
873 }
874
875 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
876 {
877 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
878 struct r300_vertex_program_code* code = &vs->code;
879 struct r300_screen* r300screen = r300_screen(r300->context.screen);
880 unsigned instruction_count = code->length / 4;
881 unsigned i;
882
883 unsigned vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
884 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
885 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
886 unsigned temp_count = MAX2(code->num_temporaries, 1);
887
888 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
889 vtx_mem_size / output_count, 10);
890 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
891
892 CS_LOCALS(r300);
893
894 BEGIN_CS(size);
895 /* R300_VAP_PVS_CODE_CNTL_0
896 * R300_VAP_PVS_CONST_CNTL
897 * R300_VAP_PVS_CODE_CNTL_1
898 * See the r5xx docs for instructions on how to use these. */
899 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
900 OUT_CS(R300_PVS_FIRST_INST(0) |
901 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
902 R300_PVS_LAST_INST(instruction_count - 1));
903 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
904 OUT_CS(instruction_count - 1);
905
906 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
907 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
908 for (i = 0; i < code->length; i++) {
909 OUT_CS(code->body.d[i]);
910 }
911
912 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
913 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
914 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
915 R300_PVS_VF_MAX_VTX_NUM(12) |
916 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
917 END_CS;
918 }
919
920 void r300_emit_vs_constant_buffer(struct r300_context* r300,
921 struct rc_constant_list* constants)
922 {
923 struct r300_screen* r300screen = r300_screen(r300->context.screen);
924 unsigned i;
925 CS_LOCALS(r300);
926
927 BEGIN_CS(constants->Count * 4 + 3);
928 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
929 (r300screen->caps->is_r500 ?
930 R500_PVS_CONST_START : R300_PVS_CONST_START));
931 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
932 for (i = 0; i < constants->Count; i++) {
933 const float *data = get_shader_constant(r300,
934 &constants->Constants[i],
935 &r300->shader_constants[PIPE_SHADER_VERTEX]);
936 OUT_CS_32F(data[0]);
937 OUT_CS_32F(data[1]);
938 OUT_CS_32F(data[2]);
939 OUT_CS_32F(data[3]);
940 }
941 END_CS;
942 }
943
944 void r300_emit_viewport_state(struct r300_context* r300,
945 unsigned size, void* state)
946 {
947 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
948 CS_LOCALS(r300);
949
950 BEGIN_CS(size);
951 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
952 OUT_CS_32F(viewport->xscale);
953 OUT_CS_32F(viewport->xoffset);
954 OUT_CS_32F(viewport->yscale);
955 OUT_CS_32F(viewport->yoffset);
956 OUT_CS_32F(viewport->zscale);
957 OUT_CS_32F(viewport->zoffset);
958 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
959 END_CS;
960 }
961
962 void r300_emit_ztop_state(struct r300_context* r300,
963 unsigned size, void* state)
964 {
965 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
966 CS_LOCALS(r300);
967
968 BEGIN_CS(size);
969 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
970 END_CS;
971 }
972
973 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
974 {
975 CS_LOCALS(r300);
976
977 BEGIN_CS(size);
978 OUT_CS_REG(R300_TX_INVALTAGS, 0);
979 END_CS;
980 }
981
982 void r300_emit_buffer_validate(struct r300_context *r300,
983 boolean do_validate_vertex_buffers,
984 struct pipe_buffer *index_buffer)
985 {
986 struct pipe_framebuffer_state* fb =
987 (struct pipe_framebuffer_state*)r300->fb_state.state;
988 struct r300_textures_state *texstate =
989 (struct r300_textures_state*)r300->textures_state.state;
990 struct r300_texture* tex;
991 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
992 struct pipe_vertex_element *velem = r300->velems->velem;
993 struct pipe_buffer *pbuf;
994 unsigned i;
995 boolean invalid = FALSE;
996
997 /* upload buffers first */
998 if (r300->any_user_vbs) {
999 r300_upload_user_buffers(r300);
1000 r300->any_user_vbs = false;
1001 }
1002
1003 /* Clean out BOs. */
1004 r300->rws->reset_bos(r300->rws);
1005
1006 validate:
1007 /* Color buffers... */
1008 for (i = 0; i < fb->nr_cbufs; i++) {
1009 tex = (struct r300_texture*)fb->cbufs[i]->texture;
1010 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1011 if (!r300_add_texture(r300->rws, tex,
1012 0, RADEON_GEM_DOMAIN_VRAM)) {
1013 r300->context.flush(&r300->context, 0, NULL);
1014 goto validate;
1015 }
1016 }
1017 /* ...depth buffer... */
1018 if (fb->zsbuf) {
1019 tex = (struct r300_texture*)fb->zsbuf->texture;
1020 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1021 if (!r300_add_texture(r300->rws, tex,
1022 0, RADEON_GEM_DOMAIN_VRAM)) {
1023 r300->context.flush(&r300->context, 0, NULL);
1024 goto validate;
1025 }
1026 }
1027 /* ...textures... */
1028 for (i = 0; i < texstate->count; i++) {
1029 if (!(texstate->tx_enable & (1 << i))) {
1030 continue;
1031 }
1032
1033 tex = (struct r300_texture*)texstate->fragment_sampler_views[i]->texture;
1034 if (!r300_add_texture(r300->rws, tex,
1035 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1036 r300->context.flush(&r300->context, 0, NULL);
1037 goto validate;
1038 }
1039 }
1040 /* ...occlusion query buffer... */
1041 if (r300->dirty_state & R300_NEW_QUERY) {
1042 if (!r300_add_buffer(r300->rws, r300->oqbo,
1043 0, RADEON_GEM_DOMAIN_GTT)) {
1044 r300->context.flush(&r300->context, 0, NULL);
1045 goto validate;
1046 }
1047 }
1048 /* ...vertex buffer for SWTCL path... */
1049 if (r300->vbo) {
1050 if (!r300_add_buffer(r300->rws, r300->vbo,
1051 RADEON_GEM_DOMAIN_GTT, 0)) {
1052 r300->context.flush(&r300->context, 0, NULL);
1053 goto validate;
1054 }
1055 }
1056 /* ...vertex buffers for HWTCL path... */
1057 if (do_validate_vertex_buffers) {
1058 for (i = 0; i < r300->velems->count; i++) {
1059 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1060
1061 if (!r300_add_buffer(r300->rws, pbuf,
1062 RADEON_GEM_DOMAIN_GTT, 0)) {
1063 r300->context.flush(&r300->context, 0, NULL);
1064 goto validate;
1065 }
1066 }
1067 }
1068 /* ...and index buffer for HWTCL path. */
1069 if (index_buffer) {
1070 if (!r300_add_buffer(r300->rws, index_buffer,
1071 RADEON_GEM_DOMAIN_GTT, 0)) {
1072 r300->context.flush(&r300->context, 0, NULL);
1073 goto validate;
1074 }
1075 }
1076 if (!r300->rws->validate(r300->rws)) {
1077 r300->context.flush(&r300->context, 0, NULL);
1078 if (invalid) {
1079 /* Well, hell. */
1080 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1081 exit(1);
1082 }
1083 invalid = TRUE;
1084 goto validate;
1085 }
1086 }
1087
1088 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1089 {
1090 struct r300_atom* atom;
1091 unsigned dwords = 0;
1092
1093 foreach(atom, &r300->atom_list) {
1094 if (atom->dirty || atom->always_dirty) {
1095 dwords += atom->size;
1096 }
1097 }
1098
1099 /* XXX This is the compensation for the non-atomized states. */
1100 dwords += 1024;
1101
1102 return dwords;
1103 }
1104
1105 /* Emit all dirty state. */
1106 void r300_emit_dirty_state(struct r300_context* r300)
1107 {
1108 struct r300_screen* r300screen = r300_screen(r300->context.screen);
1109 struct r300_atom* atom;
1110
1111 if (r300->dirty_state & R300_NEW_QUERY) {
1112 r300_emit_query_start(r300);
1113 r300->dirty_state &= ~R300_NEW_QUERY;
1114 }
1115
1116 foreach(atom, &r300->atom_list) {
1117 if (atom->dirty || atom->always_dirty) {
1118 atom->emit(r300, atom->size, atom->state);
1119 atom->dirty = FALSE;
1120 }
1121 }
1122
1123 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1124 r300_emit_fragment_depth_config(r300, r300->fs);
1125 if (r300screen->caps->is_r500) {
1126 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1127 } else {
1128 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1129 }
1130 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1131 }
1132
1133 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1134 if (r300screen->caps->is_r500) {
1135 r500_emit_fs_constant_buffer(r300,
1136 &r300->fs->shader->code.constants);
1137 } else {
1138 r300_emit_fs_constant_buffer(r300,
1139 &r300->fs->shader->code.constants);
1140 }
1141 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1142 }
1143
1144 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1145 struct r300_vertex_shader* vs = r300->vs_state.state;
1146 if (vs->code.constants.Count) {
1147 r300_emit_vs_constant_buffer(r300, &vs->code.constants);
1148 }
1149 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1150 }
1151
1152 /* XXX
1153 assert(r300->dirty_state == 0);
1154 */
1155
1156 /* Emit the VBO for SWTCL. */
1157 if (!r300screen->caps->has_tcl) {
1158 r300_emit_vertex_buffer(r300);
1159 }
1160
1161 r300->dirty_hw++;
1162 }