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Merge commit 'origin/graw-tests'
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300,
39 unsigned size, void* state)
40 {
41 struct r300_blend_state* blend = (struct r300_blend_state*)state;
42 struct pipe_framebuffer_state* fb =
43 (struct pipe_framebuffer_state*)r300->fb_state.state;
44 CS_LOCALS(r300);
45
46 BEGIN_CS(size);
47 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
48 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
49 if (fb->nr_cbufs) {
50 OUT_CS(blend->blend_control);
51 OUT_CS(blend->alpha_blend_control);
52 OUT_CS(blend->color_channel_mask);
53 } else {
54 OUT_CS(0);
55 OUT_CS(0);
56 OUT_CS(0);
57 /* XXX also disable fastfill here once it's supported */
58 }
59 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
60 END_CS;
61 }
62
63 void r300_emit_blend_color_state(struct r300_context* r300,
64 unsigned size, void* state)
65 {
66 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
67 CS_LOCALS(r300);
68
69 if (r300->screen->caps.is_r500) {
70 BEGIN_CS(size);
71 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
72 OUT_CS(bc->blend_color_red_alpha);
73 OUT_CS(bc->blend_color_green_blue);
74 END_CS;
75 } else {
76 BEGIN_CS(size);
77 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
78 END_CS;
79 }
80 }
81
82 void r300_emit_clip_state(struct r300_context* r300,
83 unsigned size, void* state)
84 {
85 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
86 CS_LOCALS(r300);
87
88 if (r300->screen->caps.has_tcl) {
89 BEGIN_CS(size);
90 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
91 (r300->screen->caps.is_r500 ?
92 R500_PVS_UCP_START : R300_PVS_UCP_START));
93 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
94 OUT_CS_TABLE(clip->ucp, 6 * 4);
95 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
96 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
97 END_CS;
98 } else {
99 BEGIN_CS(size);
100 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
101 END_CS;
102 }
103 }
104
105 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
106 {
107 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
108 struct pipe_framebuffer_state* fb =
109 (struct pipe_framebuffer_state*)r300->fb_state.state;
110 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
111 CS_LOCALS(r300);
112
113 BEGIN_CS(size);
114 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
115 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
116
117 if (fb->zsbuf) {
118 OUT_CS(dsa->z_buffer_control);
119 OUT_CS(dsa->z_stencil_control);
120 } else {
121 OUT_CS(0);
122 OUT_CS(0);
123 }
124
125 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
126
127 if (r300->screen->caps.is_r500) {
128 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
129 }
130 END_CS;
131 }
132
133 static const float * get_rc_constant_state(
134 struct r300_context * r300,
135 struct rc_constant * constant)
136 {
137 struct r300_viewport_state* viewport = r300->viewport_state.state;
138 struct r300_textures_state* texstate = r300->textures_state.state;
139 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
140 struct pipe_resource *tex;
141
142 assert(constant->Type == RC_CONSTANT_STATE);
143
144 switch (constant->u.State[0]) {
145 /* Factor for converting rectangle coords to
146 * normalized coords. Should only show up on non-r500. */
147 case RC_STATE_R300_TEXRECT_FACTOR:
148 tex = texstate->sampler_views[constant->u.State[1]]->base.texture;
149 vec[0] = 1.0 / tex->width0;
150 vec[1] = 1.0 / tex->height0;
151 break;
152
153 case RC_STATE_R300_VIEWPORT_SCALE:
154 vec[0] = viewport->xscale;
155 vec[1] = viewport->yscale;
156 vec[2] = viewport->zscale;
157 break;
158
159 case RC_STATE_R300_VIEWPORT_OFFSET:
160 vec[0] = viewport->xoffset;
161 vec[1] = viewport->yoffset;
162 vec[2] = viewport->zoffset;
163 break;
164
165 default:
166 fprintf(stderr, "r300: Implementation error: "
167 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
168 }
169
170 /* This should either be (0, 0, 0, 1), which should be a relatively safe
171 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
172 * state factors. */
173 return vec;
174 }
175
176 /* Convert a normal single-precision float into the 7.16 format
177 * used by the R300 fragment shader.
178 */
179 static uint32_t pack_float24(float f)
180 {
181 union {
182 float fl;
183 uint32_t u;
184 } u;
185 float mantissa;
186 int exponent;
187 uint32_t float24 = 0;
188
189 if (f == 0.0)
190 return 0;
191
192 u.fl = f;
193
194 mantissa = frexpf(f, &exponent);
195
196 /* Handle -ve */
197 if (mantissa < 0) {
198 float24 |= (1 << 23);
199 mantissa = mantissa * -1.0;
200 }
201 /* Handle exponent, bias of 63 */
202 exponent += 62;
203 float24 |= (exponent << 16);
204 /* Kill 7 LSB of mantissa */
205 float24 |= (u.u & 0x7FFFFF) >> 7;
206
207 return float24;
208 }
209
210 unsigned r300_get_fs_atom_size(struct r300_context *r300)
211 {
212 struct r300_fragment_shader *fs = r300_fs(r300);
213 unsigned imm_count = fs->shader->immediates_count;
214 struct r300_fragment_program_code *code = &fs->shader->code.code.r300;
215
216 return 19 +
217 code->alu.length * 4 +
218 (code->tex.length ? (1 + code->tex.length) : 0) +
219 (imm_count ? imm_count * 5 : 0);
220 }
221
222 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
223 {
224 struct r300_fragment_shader *fs = r300_fs(r300);
225 struct rX00_fragment_program_code* generic_code = &fs->shader->code;
226 struct r300_fragment_program_code * code = &generic_code->code.r300;
227 unsigned i;
228 unsigned imm_count = fs->shader->immediates_count;
229 unsigned imm_first = fs->shader->externals_count;
230 unsigned imm_end = generic_code->constants.Count;
231 struct rc_constant *constants = generic_code->constants.Constants;
232 CS_LOCALS(r300);
233
234 BEGIN_CS(size);
235 OUT_CS_REG(R300_US_CONFIG, code->config);
236 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
237 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
238
239 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
240 OUT_CS_TABLE(code->code_addr, 4);
241
242 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
243 for (i = 0; i < code->alu.length; i++)
244 OUT_CS(code->alu.inst[i].rgb_inst);
245
246 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
247 for (i = 0; i < code->alu.length; i++)
248 OUT_CS(code->alu.inst[i].rgb_addr);
249
250 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
251 for (i = 0; i < code->alu.length; i++)
252 OUT_CS(code->alu.inst[i].alpha_inst);
253
254 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
255 for (i = 0; i < code->alu.length; i++)
256 OUT_CS(code->alu.inst[i].alpha_addr);
257
258 if (code->tex.length) {
259 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
260 OUT_CS_TABLE(code->tex.inst, code->tex.length);
261 }
262
263 /* Emit immediates. */
264 if (imm_count) {
265 for(i = imm_first; i < imm_end; ++i) {
266 if (constants[i].Type == RC_CONSTANT_IMMEDIATE) {
267 const float *data = constants[i].u.Immediate;
268
269 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
270 OUT_CS(pack_float24(data[0]));
271 OUT_CS(pack_float24(data[1]));
272 OUT_CS(pack_float24(data[2]));
273 OUT_CS(pack_float24(data[3]));
274 }
275 }
276 }
277
278 OUT_CS_REG(R300_FG_DEPTH_SRC, fs->shader->fg_depth_src);
279 OUT_CS_REG(R300_US_W_FMT, fs->shader->us_out_w);
280 END_CS;
281 }
282
283 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
284 {
285 struct r300_fragment_shader *fs = r300_fs(r300);
286 struct rc_constant_list *constants = &fs->shader->code.constants;
287 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
288 unsigned i, count = fs->shader->externals_count;
289 CS_LOCALS(r300);
290
291 if (count == 0)
292 return;
293
294 BEGIN_CS(size);
295 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
296 for(i = 0; i < count; ++i) {
297 const float *data;
298 assert(constants->Constants[i].Type == RC_CONSTANT_EXTERNAL);
299 data = buf->constants[i];
300 OUT_CS(pack_float24(data[0]));
301 OUT_CS(pack_float24(data[1]));
302 OUT_CS(pack_float24(data[2]));
303 OUT_CS(pack_float24(data[3]));
304 }
305 END_CS;
306 }
307
308 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
309 {
310 struct r300_fragment_shader *fs = r300_fs(r300);
311 struct rc_constant_list *constants = &fs->shader->code.constants;
312 unsigned i;
313 unsigned count = fs->shader->rc_state_count;
314 unsigned first = fs->shader->externals_count;
315 unsigned end = constants->Count;
316 CS_LOCALS(r300);
317
318 if (count == 0)
319 return;
320
321 BEGIN_CS(size);
322 for(i = first; i < end; ++i) {
323 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
324 const float *data =
325 get_rc_constant_state(r300, &constants->Constants[i]);
326
327 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
328 OUT_CS(pack_float24(data[0]));
329 OUT_CS(pack_float24(data[1]));
330 OUT_CS(pack_float24(data[2]));
331 OUT_CS(pack_float24(data[3]));
332 }
333 }
334 END_CS;
335 }
336
337 unsigned r500_get_fs_atom_size(struct r300_context *r300)
338 {
339 struct r300_fragment_shader *fs = r300_fs(r300);
340 unsigned imm_count = fs->shader->immediates_count;
341 struct r500_fragment_program_code *code = &fs->shader->code.code.r500;
342
343 return 17 +
344 ((code->inst_end + 1) * 6) +
345 (imm_count ? imm_count * 7 : 0);
346 }
347
348 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
349 {
350 struct r300_fragment_shader *fs = r300_fs(r300);
351 struct rX00_fragment_program_code* generic_code = &fs->shader->code;
352 struct r500_fragment_program_code * code = &generic_code->code.r500;
353 unsigned i;
354 unsigned imm_count = fs->shader->immediates_count;
355 unsigned imm_first = fs->shader->externals_count;
356 unsigned imm_end = generic_code->constants.Count;
357 struct rc_constant *constants = generic_code->constants.Constants;
358 CS_LOCALS(r300);
359
360 BEGIN_CS(size);
361 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
362 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
363 OUT_CS_REG(R500_US_CODE_RANGE,
364 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
365 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
366 OUT_CS_REG(R500_US_CODE_ADDR,
367 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
368
369 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
370 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
371 for (i = 0; i <= code->inst_end; i++) {
372 OUT_CS(code->inst[i].inst0);
373 OUT_CS(code->inst[i].inst1);
374 OUT_CS(code->inst[i].inst2);
375 OUT_CS(code->inst[i].inst3);
376 OUT_CS(code->inst[i].inst4);
377 OUT_CS(code->inst[i].inst5);
378 }
379
380 /* Emit immediates. */
381 if (imm_count) {
382 for(i = imm_first; i < imm_end; ++i) {
383 if (constants[i].Type == RC_CONSTANT_IMMEDIATE) {
384 const float *data = constants[i].u.Immediate;
385
386 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
387 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
388 (i & R500_GA_US_VECTOR_INDEX_MASK));
389 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
390 OUT_CS_TABLE(data, 4);
391 }
392 }
393 }
394
395 OUT_CS_REG(R300_FG_DEPTH_SRC, fs->shader->fg_depth_src);
396 OUT_CS_REG(R300_US_W_FMT, fs->shader->us_out_w);
397 END_CS;
398 }
399
400 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
401 {
402 struct r300_fragment_shader *fs = r300_fs(r300);
403 struct rc_constant_list *constants = &fs->shader->code.constants;
404 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
405 unsigned i, count = fs->shader->externals_count;
406 CS_LOCALS(r300);
407
408 if (count == 0)
409 return;
410
411 BEGIN_CS(size);
412 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
413 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
414 for(i = 0; i < count; ++i) {
415 assert(constants->Constants[i].Type == RC_CONSTANT_EXTERNAL);
416 }
417 OUT_CS_TABLE(buf->constants, count * 4);
418 END_CS;
419 }
420
421 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
422 {
423 struct r300_fragment_shader *fs = r300_fs(r300);
424 struct rc_constant_list *constants = &fs->shader->code.constants;
425 unsigned i;
426 unsigned count = fs->shader->rc_state_count;
427 unsigned first = fs->shader->externals_count;
428 unsigned end = constants->Count;
429 CS_LOCALS(r300);
430
431 if (count == 0)
432 return;
433
434 BEGIN_CS(size);
435 for(i = first; i < end; ++i) {
436 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
437 const float *data =
438 get_rc_constant_state(r300, &constants->Constants[i]);
439
440 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
441 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
442 (i & R500_GA_US_VECTOR_INDEX_MASK));
443 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
444 OUT_CS_TABLE(data, 4);
445 }
446 }
447 END_CS;
448 }
449
450 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
451 {
452 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
453 struct r300_texture* tex;
454 struct pipe_surface* surf;
455 int i;
456 CS_LOCALS(r300);
457
458 BEGIN_CS(size);
459
460 /* Flush and free renderbuffer caches. */
461 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
462 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
463 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
464 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
465 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
466 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
467
468 /* Set the number of colorbuffers. */
469 if (fb->nr_cbufs > 1) {
470 if (r300->screen->caps.is_r500) {
471 OUT_CS_REG(R300_RB3D_CCTL,
472 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
473 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
474 } else {
475 OUT_CS_REG(R300_RB3D_CCTL,
476 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
477 }
478 } else {
479 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
480 }
481
482 /* Set up colorbuffers. */
483 for (i = 0; i < fb->nr_cbufs; i++) {
484 surf = fb->cbufs[i];
485 tex = r300_texture(surf->texture);
486 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
487
488 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
489 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
490
491 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
492 OUT_CS_TEX_RELOC(tex, tex->fb_state.colorpitch[surf->level],
493 0, RADEON_GEM_DOMAIN_VRAM, 0);
494
495 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
496 }
497 for (; i < 4; i++) {
498 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
499 }
500
501 /* Set up a zbuffer. */
502 if (fb->zsbuf) {
503 surf = fb->zsbuf;
504 tex = r300_texture(surf->texture);
505 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
506
507 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
508 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
509
510 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
511
512 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
513 OUT_CS_TEX_RELOC(tex, tex->fb_state.depthpitch[surf->level],
514 0, RADEON_GEM_DOMAIN_VRAM, 0);
515 }
516
517 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
518 if (r300->screen->caps.is_r500) {
519 OUT_CS(0);
520 OUT_CS(((fb->width - 1) << R300_SCISSORS_X_SHIFT) |
521 ((fb->height - 1) << R300_SCISSORS_Y_SHIFT));
522 } else {
523 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
524 (1440 << R300_SCISSORS_Y_SHIFT));
525 OUT_CS(((fb->width + 1440-1) << R300_SCISSORS_X_SHIFT) |
526 ((fb->height + 1440-1) << R300_SCISSORS_Y_SHIFT));
527 }
528 END_CS;
529 }
530
531 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
532 {
533 struct r300_query *query = r300->query_current;
534 CS_LOCALS(r300);
535
536 if (!query)
537 return;
538
539 BEGIN_CS(size);
540 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
541 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
542 } else {
543 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
544 }
545 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
546 END_CS;
547 query->begin_emitted = TRUE;
548 }
549
550
551 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
552 struct r300_query *query)
553 {
554 struct r300_capabilities* caps = &r300->screen->caps;
555 CS_LOCALS(r300);
556
557 assert(caps->num_frag_pipes);
558
559 BEGIN_CS(6 * caps->num_frag_pipes + 2);
560 /* I'm not so sure I like this switch, but it's hard to be elegant
561 * when there's so many special cases...
562 *
563 * So here's the basic idea. For each pipe, enable writes to it only,
564 * then put out the relocation for ZPASS_ADDR, taking into account a
565 * 4-byte offset for each pipe. RV380 and older are special; they have
566 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
567 * so there's a chipset cap for that. */
568 switch (caps->num_frag_pipes) {
569 case 4:
570 /* pipe 3 only */
571 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
572 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
573 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
574 0, RADEON_GEM_DOMAIN_GTT, 0);
575 case 3:
576 /* pipe 2 only */
577 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
578 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
579 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
580 0, RADEON_GEM_DOMAIN_GTT, 0);
581 case 2:
582 /* pipe 1 only */
583 /* As mentioned above, accomodate RV380 and older. */
584 OUT_CS_REG(R300_SU_REG_DEST,
585 1 << (caps->high_second_pipe ? 3 : 1));
586 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
587 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
588 0, RADEON_GEM_DOMAIN_GTT, 0);
589 case 1:
590 /* pipe 0 only */
591 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
592 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
593 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
594 0, RADEON_GEM_DOMAIN_GTT, 0);
595 break;
596 default:
597 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
598 " pixel pipes!\n", caps->num_frag_pipes);
599 abort();
600 }
601
602 /* And, finally, reset it to normal... */
603 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
604 END_CS;
605 }
606
607 static void rv530_emit_query_end_single_z(struct r300_context *r300,
608 struct r300_query *query)
609 {
610 CS_LOCALS(r300);
611
612 BEGIN_CS(8);
613 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
614 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
615 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
616 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
617 END_CS;
618 }
619
620 static void rv530_emit_query_end_double_z(struct r300_context *r300,
621 struct r300_query *query)
622 {
623 CS_LOCALS(r300);
624
625 BEGIN_CS(14);
626 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
627 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
628 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
629 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
630 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
631 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
632 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
633 END_CS;
634 }
635
636 void r300_emit_query_end(struct r300_context* r300)
637 {
638 struct r300_capabilities *caps = &r300->screen->caps;
639 struct r300_query *query = r300->query_current;
640
641 if (!query)
642 return;
643
644 if (query->begin_emitted == FALSE)
645 return;
646
647 if (caps->family == CHIP_FAMILY_RV530) {
648 if (caps->num_z_pipes == 2)
649 rv530_emit_query_end_double_z(r300, query);
650 else
651 rv530_emit_query_end_single_z(r300, query);
652 } else
653 r300_emit_query_end_frag_pipes(r300, query);
654
655 query->begin_emitted = FALSE;
656 }
657
658 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
659 {
660 struct r300_rs_state* rs = (struct r300_rs_state*)state;
661 float scale, offset;
662 CS_LOCALS(r300);
663
664 BEGIN_CS(size);
665 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
666
667 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
668
669 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
670 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
671 OUT_CS(rs->point_minmax);
672 OUT_CS(rs->line_control);
673
674 if (rs->polygon_offset_enable) {
675 scale = rs->depth_scale * 12;
676 offset = rs->depth_offset;
677
678 switch (r300->zbuffer_bpp) {
679 case 16:
680 offset *= 4;
681 break;
682 case 24:
683 offset *= 2;
684 break;
685 }
686
687 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
688 OUT_CS_32F(scale);
689 OUT_CS_32F(offset);
690 OUT_CS_32F(scale);
691 OUT_CS_32F(offset);
692 }
693
694 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
695 OUT_CS(rs->polygon_offset_enable);
696 OUT_CS(rs->cull_mode);
697 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
698 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
699 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
700 OUT_CS_REG(R300_SC_CLIP_RULE, rs->clip_rule);
701 OUT_CS_REG(R300_GB_ENABLE, rs->stuffing_enable);
702 OUT_CS_REG_SEQ(R300_GA_POINT_S0, 4);
703 OUT_CS_32F(rs->point_texcoord_left);
704 OUT_CS_32F(rs->point_texcoord_bottom);
705 OUT_CS_32F(rs->point_texcoord_right);
706 OUT_CS_32F(rs->point_texcoord_top);
707 END_CS;
708 }
709
710 void r300_emit_rs_block_state(struct r300_context* r300,
711 unsigned size, void* state)
712 {
713 struct r300_rs_block* rs = (struct r300_rs_block*)state;
714 unsigned i;
715 /* It's the same for both INST and IP tables */
716 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
717 CS_LOCALS(r300);
718
719 if (SCREEN_DBG_ON(r300->screen, DBG_DRAW)) {
720 r500_dump_rs_block(rs);
721 }
722
723 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
724
725 BEGIN_CS(size);
726 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
727 OUT_CS(rs->vap_vtx_state_cntl);
728 OUT_CS(rs->vap_vsm_vtx_assm);
729 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
730 OUT_CS(rs->vap_out_vtx_fmt[0]);
731 OUT_CS(rs->vap_out_vtx_fmt[1]);
732
733 if (r300->screen->caps.is_r500) {
734 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
735 } else {
736 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
737 }
738 OUT_CS_TABLE(rs->ip, count);
739 for (i = 0; i < count; i++) {
740 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
741 }
742
743 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
744 OUT_CS(rs->count);
745 OUT_CS(rs->inst_count);
746
747 if (r300->screen->caps.is_r500) {
748 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
749 } else {
750 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
751 }
752 OUT_CS_TABLE(rs->inst, count);
753 for (i = 0; i < count; i++) {
754 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
755 }
756
757 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
758 rs->count, rs->inst_count);
759
760 END_CS;
761 }
762
763 void r300_emit_scissor_state(struct r300_context* r300,
764 unsigned size, void* state)
765 {
766 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
767 CS_LOCALS(r300);
768
769 BEGIN_CS(size);
770 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
771 if (r300->screen->caps.is_r500) {
772 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
773 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
774 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
775 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
776 } else {
777 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
778 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
779 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
780 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
781 }
782 END_CS;
783 }
784
785 void r300_emit_textures_state(struct r300_context *r300,
786 unsigned size, void *state)
787 {
788 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
789 struct r300_texture_sampler_state *texstate;
790 unsigned i;
791 CS_LOCALS(r300);
792
793 BEGIN_CS(size);
794 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
795
796 for (i = 0; i < allstate->count; i++) {
797 if ((1 << i) & allstate->tx_enable) {
798 texstate = &allstate->regs[i];
799
800 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
801 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
802 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
803 texstate->border_color);
804
805 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
806 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
807 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
808
809 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
810 OUT_CS_TEX_RELOC(r300_texture(allstate->sampler_views[i]->base.texture),
811 texstate->format.tile_config,
812 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
813 }
814 }
815 END_CS;
816 }
817
818 void r300_emit_aos(struct r300_context* r300, unsigned offset, boolean indexed)
819 {
820 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
821 struct pipe_vertex_element *velem = r300->velems->velem;
822 int i;
823 unsigned size1, size2, aos_count = r300->velems->count;
824 unsigned packet_size = (aos_count * 3 + 1) / 2;
825 CS_LOCALS(r300);
826
827 for (i = 0; i < aos_count; i++) {
828 if ((vbuf[velem[i].vertex_buffer_index].buffer_offset + velem[i].src_offset) % 4 != 0) {
829 /* XXX We must align the buffer. */
830 assert(0);
831 fprintf(stderr, "r300: Unaligned vertex buffer offsets aren't supported, aborting..\n");
832 abort();
833 }
834 }
835
836 BEGIN_CS(2 + packet_size + aos_count * 2);
837 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
838 OUT_CS(aos_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
839
840 for (i = 0; i < aos_count - 1; i += 2) {
841 vb1 = &vbuf[velem[i].vertex_buffer_index];
842 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
843 size1 = util_format_get_blocksize(velem[i].src_format);
844 size2 = util_format_get_blocksize(velem[i+1].src_format);
845
846 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
847 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
848 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
849 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
850 }
851
852 if (aos_count & 1) {
853 vb1 = &vbuf[velem[i].vertex_buffer_index];
854 size1 = util_format_get_blocksize(velem[i].src_format);
855
856 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
857 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
858 }
859
860 for (i = 0; i < aos_count; i++) {
861 OUT_CS_BUF_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
862 RADEON_GEM_DOMAIN_GTT, 0, 0);
863 }
864 END_CS;
865 }
866
867 void r300_emit_vertex_buffer(struct r300_context* r300)
868 {
869 CS_LOCALS(r300);
870
871 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
872 "vertex size %d\n", r300->vbo,
873 r300->vertex_info.size);
874 /* Set the pointer to our vertex buffer. The emitted values are this:
875 * PACKET3 [3D_LOAD_VBPNTR]
876 * COUNT [1]
877 * FORMAT [size | stride << 8]
878 * OFFSET [offset into BO]
879 * VBPNTR [relocated BO]
880 */
881 BEGIN_CS(7);
882 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
883 OUT_CS(1);
884 OUT_CS(r300->vertex_info.size |
885 (r300->vertex_info.size << 8));
886 OUT_CS(r300->vbo_offset);
887 OUT_CS_BUF_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
888 END_CS;
889 }
890
891 void r300_emit_vertex_stream_state(struct r300_context* r300,
892 unsigned size, void* state)
893 {
894 struct r300_vertex_stream_state *streams =
895 (struct r300_vertex_stream_state*)state;
896 unsigned i;
897 CS_LOCALS(r300);
898
899 DBG(r300, DBG_DRAW, "r300: PSC emit:\n");
900
901 BEGIN_CS(size);
902 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
903 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
904 for (i = 0; i < streams->count; i++) {
905 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
906 streams->vap_prog_stream_cntl[i]);
907 }
908 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
909 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
910 for (i = 0; i < streams->count; i++) {
911 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
912 streams->vap_prog_stream_cntl_ext[i]);
913 }
914 END_CS;
915 }
916
917 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
918 {
919 CS_LOCALS(r300);
920
921 BEGIN_CS(size);
922 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
923 END_CS;
924 }
925
926 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
927 {
928 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
929 struct r300_vertex_program_code* code = &vs->code;
930 struct r300_screen* r300screen = r300->screen;
931 unsigned instruction_count = code->length / 4;
932 unsigned i;
933
934 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
935 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
936 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
937 unsigned temp_count = MAX2(code->num_temporaries, 1);
938
939 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
940 vtx_mem_size / output_count, 10);
941 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
942
943 unsigned imm_first = vs->externals_count;
944 unsigned imm_end = vs->code.constants.Count;
945 unsigned imm_count = vs->immediates_count;
946
947 CS_LOCALS(r300);
948
949 BEGIN_CS(size);
950 /* R300_VAP_PVS_CODE_CNTL_0
951 * R300_VAP_PVS_CONST_CNTL
952 * R300_VAP_PVS_CODE_CNTL_1
953 * See the r5xx docs for instructions on how to use these. */
954 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
955 OUT_CS(R300_PVS_FIRST_INST(0) |
956 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
957 R300_PVS_LAST_INST(instruction_count - 1));
958 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
959 OUT_CS(instruction_count - 1);
960
961 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
962 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
963 OUT_CS_TABLE(code->body.d, code->length);
964
965 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
966 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
967 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
968 R300_PVS_VF_MAX_VTX_NUM(12) |
969 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
970
971 /* Emit immediates. */
972 if (imm_count) {
973 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
974 (r300->screen->caps.is_r500 ?
975 R500_PVS_CONST_START : R300_PVS_CONST_START) +
976 imm_first);
977 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
978 for (i = imm_first; i < imm_end; i++) {
979 const float *data = vs->code.constants.Constants[i].u.Immediate;
980 OUT_CS_TABLE(data, 4);
981 }
982 }
983 END_CS;
984 }
985
986 void r300_emit_vs_constants(struct r300_context* r300,
987 unsigned size, void *state)
988 {
989 unsigned count =
990 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
991 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
992 CS_LOCALS(r300);
993
994 if (!count)
995 return;
996
997 BEGIN_CS(size);
998 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
999 (r300->screen->caps.is_r500 ?
1000 R500_PVS_CONST_START : R300_PVS_CONST_START));
1001 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1002 OUT_CS_TABLE(buf->constants, count * 4);
1003 END_CS;
1004 }
1005
1006 void r300_emit_viewport_state(struct r300_context* r300,
1007 unsigned size, void* state)
1008 {
1009 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1010 CS_LOCALS(r300);
1011
1012 BEGIN_CS(size);
1013 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1014 OUT_CS_32F(viewport->xscale);
1015 OUT_CS_32F(viewport->xoffset);
1016 OUT_CS_32F(viewport->yscale);
1017 OUT_CS_32F(viewport->yoffset);
1018 OUT_CS_32F(viewport->zscale);
1019 OUT_CS_32F(viewport->zoffset);
1020 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1021 END_CS;
1022 }
1023
1024 void r300_emit_ztop_state(struct r300_context* r300,
1025 unsigned size, void* state)
1026 {
1027 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1028 CS_LOCALS(r300);
1029
1030 BEGIN_CS(size);
1031 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1032 END_CS;
1033 }
1034
1035 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1036 {
1037 CS_LOCALS(r300);
1038
1039 BEGIN_CS(size);
1040 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1041 END_CS;
1042 }
1043
1044 void r300_emit_buffer_validate(struct r300_context *r300,
1045 boolean do_validate_vertex_buffers,
1046 struct pipe_resource *index_buffer)
1047 {
1048 struct pipe_framebuffer_state* fb =
1049 (struct pipe_framebuffer_state*)r300->fb_state.state;
1050 struct r300_textures_state *texstate =
1051 (struct r300_textures_state*)r300->textures_state.state;
1052 struct r300_texture* tex;
1053 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1054 struct pipe_vertex_element *velem = r300->velems->velem;
1055 struct pipe_resource *pbuf;
1056 unsigned i;
1057 boolean invalid = FALSE;
1058
1059 /* upload buffers first */
1060 if (r300->any_user_vbs) {
1061 r300_upload_user_buffers(r300);
1062 r300->any_user_vbs = false;
1063 }
1064
1065 /* Clean out BOs. */
1066 r300->rws->reset_bos(r300->rws);
1067
1068 validate:
1069 /* Color buffers... */
1070 for (i = 0; i < fb->nr_cbufs; i++) {
1071 tex = r300_texture(fb->cbufs[i]->texture);
1072 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1073 if (!r300_add_texture(r300->rws, tex,
1074 0, RADEON_GEM_DOMAIN_VRAM)) {
1075 r300->context.flush(&r300->context, 0, NULL);
1076 goto validate;
1077 }
1078 }
1079 /* ...depth buffer... */
1080 if (fb->zsbuf) {
1081 tex = r300_texture(fb->zsbuf->texture);
1082 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1083 if (!r300_add_texture(r300->rws, tex,
1084 0, RADEON_GEM_DOMAIN_VRAM)) {
1085 r300->context.flush(&r300->context, 0, NULL);
1086 goto validate;
1087 }
1088 }
1089 /* ...textures... */
1090 for (i = 0; i < texstate->count; i++) {
1091 if (!(texstate->tx_enable & (1 << i))) {
1092 continue;
1093 }
1094
1095 tex = r300_texture(texstate->sampler_views[i]->base.texture);
1096 if (!r300_add_texture(r300->rws, tex,
1097 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1098 r300->context.flush(&r300->context, 0, NULL);
1099 goto validate;
1100 }
1101 }
1102 /* ...occlusion query buffer... */
1103 if (r300->query_start.dirty ||
1104 (r300->query_current && r300->query_current->begin_emitted)) {
1105 if (!r300_add_buffer(r300->rws, r300->oqbo,
1106 0, RADEON_GEM_DOMAIN_GTT)) {
1107 r300->context.flush(&r300->context, 0, NULL);
1108 goto validate;
1109 }
1110 }
1111 /* ...vertex buffer for SWTCL path... */
1112 if (r300->vbo) {
1113 if (!r300_add_buffer(r300->rws, r300->vbo,
1114 RADEON_GEM_DOMAIN_GTT, 0)) {
1115 r300->context.flush(&r300->context, 0, NULL);
1116 goto validate;
1117 }
1118 }
1119 /* ...vertex buffers for HWTCL path... */
1120 if (do_validate_vertex_buffers) {
1121 for (i = 0; i < r300->velems->count; i++) {
1122 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1123
1124 if (!r300_add_buffer(r300->rws, pbuf,
1125 RADEON_GEM_DOMAIN_GTT, 0)) {
1126 r300->context.flush(&r300->context, 0, NULL);
1127 goto validate;
1128 }
1129 }
1130 }
1131 /* ...and index buffer for HWTCL path. */
1132 if (index_buffer) {
1133 if (!r300_add_buffer(r300->rws, index_buffer,
1134 RADEON_GEM_DOMAIN_GTT, 0)) {
1135 r300->context.flush(&r300->context, 0, NULL);
1136 goto validate;
1137 }
1138 }
1139 if (!r300->rws->validate(r300->rws)) {
1140 r300->context.flush(&r300->context, 0, NULL);
1141 if (invalid) {
1142 /* Well, hell. */
1143 fprintf(stderr, "r300: Stuck in validation loop, gonna quit now.\n");
1144 abort();
1145 }
1146 invalid = TRUE;
1147 goto validate;
1148 }
1149 }
1150
1151 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1152 {
1153 struct r300_atom* atom;
1154 unsigned dwords = 0;
1155
1156 foreach(atom, &r300->atom_list) {
1157 if (atom->dirty) {
1158 dwords += atom->size;
1159 }
1160 }
1161
1162 /* let's reserve some more, just in case */
1163 dwords += 32;
1164
1165 return dwords;
1166 }
1167
1168 /* Emit all dirty state. */
1169 void r300_emit_dirty_state(struct r300_context* r300)
1170 {
1171 struct r300_screen* r300screen = r300->screen;
1172 struct r300_atom* atom;
1173
1174 foreach(atom, &r300->atom_list) {
1175 if (atom->dirty) {
1176 atom->emit(r300, atom->size, atom->state);
1177 if (SCREEN_DBG_ON(r300->screen, DBG_STATS)) {
1178 atom->counter++;
1179 }
1180 atom->dirty = FALSE;
1181 }
1182 }
1183
1184 /* Emit the VBO for SWTCL. */
1185 if (!r300screen->caps.has_tcl) {
1186 r300_emit_vertex_buffer(r300);
1187 }
1188
1189 r300->dirty_hw++;
1190 }