2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23 /* r300_emit: Functions for emitting state. */
25 #include "util/u_math.h"
27 #include "r300_context.h"
29 #include "r300_emit.h"
31 #include "r300_screen.h"
32 #include "r300_state_derived.h"
33 #include "r300_state_inlines.h"
34 #include "r300_texture.h"
37 void r300_emit_blend_state(struct r300_context
* r300
,
38 struct r300_blend_state
* blend
)
42 OUT_CS_REG_SEQ(R300_RB3D_CBLEND
, 2);
43 OUT_CS(blend
->blend_control
);
44 OUT_CS(blend
->alpha_blend_control
);
45 OUT_CS_REG(R300_RB3D_ROPCNTL
, blend
->rop
);
46 OUT_CS_REG(R300_RB3D_DITHER_CTL
, blend
->dither
);
50 void r300_emit_blend_color_state(struct r300_context
* r300
,
51 struct r300_blend_color_state
* bc
)
53 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
56 if (r300screen
->caps
->is_r500
) {
58 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR
, 2);
59 OUT_CS(bc
->blend_color_red_alpha
);
60 OUT_CS(bc
->blend_color_green_blue
);
64 OUT_CS_REG(R300_RB3D_BLEND_COLOR
, bc
->blend_color
);
69 void r300_emit_clip_state(struct r300_context
* r300
,
70 struct pipe_clip_state
* clip
)
73 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
76 if (r300screen
->caps
->has_tcl
) {
77 BEGIN_CS(5 + (6 * 4));
78 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
79 (r300screen
->caps
->is_r500
?
80 R500_PVS_UCP_START
: R300_PVS_UCP_START
));
81 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, 6 * 4);
82 for (i
= 0; i
< 6; i
++) {
83 OUT_CS_32F(clip
->ucp
[i
][0]);
84 OUT_CS_32F(clip
->ucp
[i
][1]);
85 OUT_CS_32F(clip
->ucp
[i
][2]);
86 OUT_CS_32F(clip
->ucp
[i
][3]);
88 OUT_CS_REG(R300_VAP_CLIP_CNTL
, ((1 << clip
->nr
) - 1) |
89 R300_PS_UCP_MODE_CLIP_AS_TRIFAN
);
93 OUT_CS_REG(R300_VAP_CLIP_CNTL
, R300_CLIP_DISABLE
);
99 void r300_emit_dsa_state(struct r300_context
* r300
,
100 struct r300_dsa_state
* dsa
)
102 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
105 BEGIN_CS(r300screen
->caps
->is_r500
? 10 : 8);
106 OUT_CS_REG(R300_FG_ALPHA_FUNC
, dsa
->alpha_function
);
108 /* not needed since we use the 8bit alpha ref */
109 /*if (r300screen->caps->is_r500) {
110 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
113 OUT_CS_REG_SEQ(R300_ZB_CNTL
, 3);
114 OUT_CS(dsa
->z_buffer_control
);
115 OUT_CS(dsa
->z_stencil_control
);
116 OUT_CS(dsa
->stencil_ref_mask
);
117 OUT_CS_REG(R300_ZB_ZTOP
, r300
->ztop_state
.z_buffer_top
);
119 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
120 if (r300screen
->caps
->is_r500
) {
121 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF
, dsa
->stencil_ref_bf
);
126 static const float * get_shader_constant(
127 struct r300_context
* r300
,
128 struct rc_constant
* constant
,
129 struct r300_constant_buffer
* externals
)
131 static const float zero
[4] = { 0.0, 0.0, 0.0, 0.0 };
132 switch(constant
->Type
) {
133 case RC_CONSTANT_EXTERNAL
:
134 return externals
->constants
[constant
->u
.External
];
136 case RC_CONSTANT_IMMEDIATE
:
137 return constant
->u
.Immediate
;
140 debug_printf("r300: Implementation error: Unhandled constant type %i\n",
146 /* Convert a normal single-precision float into the 7.16 format
147 * used by the R300 fragment shader.
149 static uint32_t pack_float24(float f
)
157 uint32_t float24
= 0;
164 mantissa
= frexpf(f
, &exponent
);
168 float24
|= (1 << 23);
169 mantissa
= mantissa
* -1.0;
171 /* Handle exponent, bias of 63 */
173 float24
|= (exponent
<< 16);
174 /* Kill 7 LSB of mantissa */
175 float24
|= (u
.u
& 0x7FFFFF) >> 7;
180 void r300_emit_fragment_program_code(struct r300_context
* r300
,
181 struct rX00_fragment_program_code
* generic_code
)
183 struct r300_fragment_program_code
* code
= &generic_code
->code
.r300
;
188 code
->alu
.length
* 4 +
189 (code
->tex
.length
? (1 + code
->tex
.length
) : 0));
191 OUT_CS_REG(R300_US_CONFIG
, code
->config
);
192 OUT_CS_REG(R300_US_PIXSIZE
, code
->pixsize
);
193 OUT_CS_REG(R300_US_CODE_OFFSET
, code
->code_offset
);
195 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0
, 4);
196 for(i
= 0; i
< 4; ++i
)
197 OUT_CS(code
->code_addr
[i
]);
199 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0
, code
->alu
.length
);
200 for (i
= 0; i
< code
->alu
.length
; i
++)
201 OUT_CS(code
->alu
.inst
[i
].rgb_inst
);
203 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0
, code
->alu
.length
);
204 for (i
= 0; i
< code
->alu
.length
; i
++)
205 OUT_CS(code
->alu
.inst
[i
].rgb_addr
);
207 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0
, code
->alu
.length
);
208 for (i
= 0; i
< code
->alu
.length
; i
++)
209 OUT_CS(code
->alu
.inst
[i
].alpha_inst
);
211 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0
, code
->alu
.length
);
212 for (i
= 0; i
< code
->alu
.length
; i
++)
213 OUT_CS(code
->alu
.inst
[i
].alpha_addr
);
215 if (code
->tex
.length
) {
216 OUT_CS_REG_SEQ(R300_US_TEX_INST_0
, code
->tex
.length
);
217 for(i
= 0; i
< code
->tex
.length
; ++i
)
218 OUT_CS(code
->tex
.inst
[i
]);
224 void r300_emit_fs_constant_buffer(struct r300_context
* r300
,
225 struct rc_constant_list
* constants
)
230 if (constants
->Count
== 0)
233 BEGIN_CS(constants
->Count
* 4 + 1);
234 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, constants
->Count
* 4);
235 for(i
= 0; i
< constants
->Count
; ++i
) {
236 const float * data
= get_shader_constant(r300
,
237 &constants
->Constants
[i
],
238 &r300
->shader_constants
[PIPE_SHADER_FRAGMENT
]);
239 OUT_CS(pack_float24(data
[0]));
240 OUT_CS(pack_float24(data
[1]));
241 OUT_CS(pack_float24(data
[2]));
242 OUT_CS(pack_float24(data
[3]));
247 void r500_emit_fragment_program_code(struct r300_context
* r300
,
248 struct rX00_fragment_program_code
* generic_code
)
250 struct r500_fragment_program_code
* code
= &generic_code
->code
.r500
;
255 ((code
->inst_end
+ 1) * 6));
256 OUT_CS_REG(R500_US_CONFIG
, 0);
257 OUT_CS_REG(R500_US_PIXSIZE
, code
->max_temp_idx
);
258 OUT_CS_REG(R500_US_CODE_RANGE
,
259 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code
->inst_end
));
260 OUT_CS_REG(R500_US_CODE_OFFSET
, 0);
261 OUT_CS_REG(R500_US_CODE_ADDR
,
262 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code
->inst_end
));
264 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_INSTR
);
265 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, (code
->inst_end
+ 1) * 6);
266 for (i
= 0; i
<= code
->inst_end
; i
++) {
267 OUT_CS(code
->inst
[i
].inst0
);
268 OUT_CS(code
->inst
[i
].inst1
);
269 OUT_CS(code
->inst
[i
].inst2
);
270 OUT_CS(code
->inst
[i
].inst3
);
271 OUT_CS(code
->inst
[i
].inst4
);
272 OUT_CS(code
->inst
[i
].inst5
);
278 void r500_emit_fs_constant_buffer(struct r300_context
* r300
,
279 struct rc_constant_list
* constants
)
284 if (constants
->Count
== 0)
287 BEGIN_CS(constants
->Count
* 4 + 2);
288 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
289 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, constants
->Count
* 4);
290 for (i
= 0; i
< constants
->Count
; i
++) {
291 const float * data
= get_shader_constant(r300
,
292 &constants
->Constants
[i
],
293 &r300
->shader_constants
[PIPE_SHADER_FRAGMENT
]);
302 void r300_emit_fb_state(struct r300_context
* r300
,
303 struct pipe_framebuffer_state
* fb
)
305 struct r300_texture
* tex
;
306 struct pipe_surface
* surf
;
310 BEGIN_CS((10 * fb
->nr_cbufs
) + (fb
->zsbuf
? 10 : 0) + 4);
311 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
313 tex
= (struct r300_texture
*)surf
->texture
;
314 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
316 /* XXX I still need to figure out how to set the mipmap level here */
317 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
+ (4 * i
), 1);
318 OUT_CS_RELOC(tex
->buffer
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
320 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0
+ (4 * i
), 1);
321 OUT_CS_RELOC(tex
->buffer
, tex
->pitch
[surf
->level
] |
322 r300_translate_colorformat(tex
->tex
.format
), 0,
323 RADEON_GEM_DOMAIN_VRAM
, 0);
325 OUT_CS_REG(R300_US_OUT_FMT_0
+ (4 * i
),
326 r300_translate_out_fmt(surf
->format
));
331 tex
= (struct r300_texture
*)surf
->texture
;
332 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
334 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
335 OUT_CS_RELOC(tex
->buffer
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
337 OUT_CS_REG(R300_ZB_FORMAT
, r300_translate_zsformat(tex
->tex
.format
));
339 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
340 OUT_CS_RELOC(tex
->buffer
, tex
->pitch
[surf
->level
], 0,
341 RADEON_GEM_DOMAIN_VRAM
, 0);
344 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT
,
345 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS
|
346 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
347 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
,
348 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
349 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);
353 static void r300_emit_query_start(struct r300_context
*r300
)
355 struct r300_capabilities
*caps
= r300_screen(r300
->context
.screen
)->caps
;
356 struct r300_query
*query
= r300
->query_current
;
362 /* XXX This will almost certainly not return good results
363 * for overlapping queries. */
365 if (caps
->family
== CHIP_FAMILY_RV530
) {
366 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
368 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
370 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
372 query
->begin_emitted
= TRUE
;
376 static void r300_emit_query_finish(struct r300_context
*r300
,
377 struct r300_query
*query
)
379 struct r300_capabilities
* caps
= r300_screen(r300
->context
.screen
)->caps
;
382 assert(caps
->num_frag_pipes
);
384 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
385 /* I'm not so sure I like this switch, but it's hard to be elegant
386 * when there's so many special cases...
388 * So here's the basic idea. For each pipe, enable writes to it only,
389 * then put out the relocation for ZPASS_ADDR, taking into account a
390 * 4-byte offset for each pipe. RV380 and older are special; they have
391 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
392 * so there's a chipset cap for that. */
393 switch (caps
->num_frag_pipes
) {
396 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
397 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
398 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 3),
399 0, RADEON_GEM_DOMAIN_GTT
, 0);
402 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
403 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
404 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 2),
405 0, RADEON_GEM_DOMAIN_GTT
, 0);
408 /* As mentioned above, accomodate RV380 and older. */
409 OUT_CS_REG(R300_SU_REG_DEST
,
410 1 << (caps
->high_second_pipe
? 3 : 1));
411 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
412 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 1),
413 0, RADEON_GEM_DOMAIN_GTT
, 0);
416 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
417 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
418 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 0),
419 0, RADEON_GEM_DOMAIN_GTT
, 0);
422 debug_printf("r300: Implementation error: Chipset reports %d"
423 " pixel pipes!\n", caps
->num_frag_pipes
);
427 /* And, finally, reset it to normal... */
428 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
432 static void rv530_emit_query_single(struct r300_context
*r300
,
433 struct r300_query
*query
)
438 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
439 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
440 OUT_CS_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
441 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
445 static void rv530_emit_query_double(struct r300_context
*r300
,
446 struct r300_query
*query
)
451 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
452 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
453 OUT_CS_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
454 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
455 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
456 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
457 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
461 void r300_emit_query_end(struct r300_context
* r300
)
463 struct r300_capabilities
*caps
= r300_screen(r300
->context
.screen
)->caps
;
464 struct r300_query
*query
= r300
->query_current
;
469 if (query
->begin_emitted
== FALSE
)
472 if (caps
->family
== CHIP_FAMILY_RV530
) {
473 if (caps
->num_z_pipes
== 2)
474 rv530_emit_query_double(r300
, query
);
476 rv530_emit_query_single(r300
, query
);
478 r300_emit_query_finish(r300
, query
);
481 void r300_emit_rs_state(struct r300_context
* r300
, struct r300_rs_state
* rs
)
486 OUT_CS_REG(R300_VAP_CNTL_STATUS
, rs
->vap_control_status
);
487 OUT_CS_REG(R300_GA_POINT_SIZE
, rs
->point_size
);
488 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX
, 2);
489 OUT_CS(rs
->point_minmax
);
490 OUT_CS(rs
->line_control
);
491 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE
, 6);
492 OUT_CS(rs
->depth_scale_front
);
493 OUT_CS(rs
->depth_offset_front
);
494 OUT_CS(rs
->depth_scale_back
);
495 OUT_CS(rs
->depth_offset_back
);
496 OUT_CS(rs
->polygon_offset_enable
);
497 OUT_CS(rs
->cull_mode
);
498 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG
, rs
->line_stipple_config
);
499 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE
, rs
->line_stipple_value
);
500 OUT_CS_REG(R300_GA_COLOR_CONTROL
, rs
->color_control
);
504 void r300_emit_rs_block_state(struct r300_context
* r300
,
505 struct r300_rs_block
* rs
)
508 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
512 if (r300screen
->caps
->is_r500
) {
513 OUT_CS_REG_SEQ(R500_RS_IP_0
, 8);
515 OUT_CS_REG_SEQ(R300_RS_IP_0
, 8);
517 for (i
= 0; i
< 8; i
++) {
519 /* debug_printf("ip %d: 0x%08x\n", i, rs->ip[i]); */
522 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
524 OUT_CS(rs
->inst_count
);
526 if (r300screen
->caps
->is_r500
) {
527 OUT_CS_REG_SEQ(R500_RS_INST_0
, 8);
529 OUT_CS_REG_SEQ(R300_RS_INST_0
, 8);
531 for (i
= 0; i
< 8; i
++) {
533 /* debug_printf("inst %d: 0x%08x\n", i, rs->inst[i]); */
536 /* debug_printf("count: 0x%08x inst_count: 0x%08x\n", rs->count,
537 * rs->inst_count); */
542 void r300_emit_scissor_state(struct r300_context
* r300
,
543 struct r300_scissor_state
* scissor
)
548 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
549 OUT_CS(scissor
->scissor_top_left
);
550 OUT_CS(scissor
->scissor_bottom_right
);
554 void r300_emit_texture(struct r300_context
* r300
,
555 struct r300_sampler_state
* sampler
,
556 struct r300_texture
* tex
,
559 uint32_t filter0
= sampler
->filter0
;
562 /* to emulate 1D textures through 2D ones correctly */
563 if (tex
->tex
.target
== PIPE_TEXTURE_1D
) {
564 filter0
&= ~R300_TX_WRAP_T_MASK
;
565 filter0
|= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE
);
569 OUT_CS_REG(R300_TX_FILTER0_0
+ (offset
* 4), filter0
|
571 OUT_CS_REG(R300_TX_FILTER1_0
+ (offset
* 4), sampler
->filter1
);
572 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (offset
* 4), sampler
->border_color
);
574 OUT_CS_REG(R300_TX_FORMAT0_0
+ (offset
* 4), tex
->state
.format0
);
575 OUT_CS_REG(R300_TX_FORMAT1_0
+ (offset
* 4), tex
->state
.format1
);
576 OUT_CS_REG(R300_TX_FORMAT2_0
+ (offset
* 4), tex
->state
.format2
);
577 OUT_CS_REG_SEQ(R300_TX_OFFSET_0
+ (offset
* 4), 1);
578 OUT_CS_RELOC(tex
->buffer
, 0,
579 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0, 0);
583 void r300_emit_vertex_buffer(struct r300_context
* r300
)
587 DBG(r300
, DBG_DRAW
, "r300: Preparing vertex buffer %p for render, "
588 "vertex size %d\n", r300
->vbo
,
589 r300
->vertex_info
->vinfo
.size
);
590 /* Set the pointer to our vertex buffer. The emitted values are this:
591 * PACKET3 [3D_LOAD_VBPNTR]
593 * FORMAT [size | stride << 8]
594 * OFFSET [offset into BO]
595 * VBPNTR [relocated BO]
598 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
600 OUT_CS(r300
->vertex_info
->vinfo
.size
|
601 (r300
->vertex_info
->vinfo
.size
<< 8));
602 OUT_CS(r300
->vbo_offset
);
603 OUT_CS_RELOC(r300
->vbo
, 0, RADEON_GEM_DOMAIN_GTT
, 0, 0);
607 void r300_emit_vertex_format_state(struct r300_context
* r300
)
613 OUT_CS_REG(R300_VAP_VTX_SIZE
, r300
->vertex_info
->vinfo
.size
);
615 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
616 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[0]);
617 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[1]);
618 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
619 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[2]);
620 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[3]);
621 /* for (i = 0; i < 4; i++) {
622 * debug_printf("hwfmt%d: 0x%08x\n", i,
623 * r300->vertex_info->vinfo.hwfmt[i]);
626 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, 8);
627 for (i
= 0; i
< 8; i
++) {
628 OUT_CS(r300
->vertex_info
->vap_prog_stream_cntl
[i
]);
629 /* debug_printf("prog_stream_cntl%d: 0x%08x\n", i,
630 * r300->vertex_info->vap_prog_stream_cntl[i]); */
632 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, 8);
633 for (i
= 0; i
< 8; i
++) {
634 OUT_CS(r300
->vertex_info
->vap_prog_stream_cntl_ext
[i
]);
635 /* debug_printf("prog_stream_cntl_ext%d: 0x%08x\n", i,
636 * r300->vertex_info->vap_prog_stream_cntl_ext[i]); */
641 void r300_emit_vertex_program_code(struct r300_context
* r300
,
642 struct r300_vertex_program_code
* code
)
645 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
646 unsigned instruction_count
= code
->length
/ 4;
649 if (!r300screen
->caps
->has_tcl
) {
650 debug_printf("r300: Implementation error: emit_vertex_shader called,"
651 " but has_tcl is FALSE!\n");
655 BEGIN_CS(9 + code
->length
);
656 /* R300_VAP_PVS_CODE_CNTL_0
657 * R300_VAP_PVS_CONST_CNTL
658 * R300_VAP_PVS_CODE_CNTL_1
659 * See the r5xx docs for instructions on how to use these.
660 * XXX these could be optimized to select better values... */
661 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0
, 3);
662 OUT_CS(R300_PVS_FIRST_INST(0) |
663 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
664 R300_PVS_LAST_INST(instruction_count
- 1));
665 OUT_CS(R300_PVS_MAX_CONST_ADDR(code
->constants
.Count
- 1));
666 OUT_CS(instruction_count
- 1);
668 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
669 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
670 for (i
= 0; i
< code
->length
; i
++)
671 OUT_CS(code
->body
.d
[i
]);
673 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(10) |
674 R300_PVS_NUM_CNTLRS(5) |
675 R300_PVS_NUM_FPUS(r300screen
->caps
->num_vert_fpus
) |
676 R300_PVS_VF_MAX_VTX_NUM(12));
680 void r300_emit_vertex_shader(struct r300_context
* r300
,
681 struct r300_vertex_shader
* vs
)
683 r300_emit_vertex_program_code(r300
, &vs
->code
);
686 void r300_emit_vs_constant_buffer(struct r300_context
* r300
,
687 struct rc_constant_list
* constants
)
690 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
693 if (!r300screen
->caps
->has_tcl
) {
694 debug_printf("r300: Implementation error: emit_vertex_shader called,"
695 " but has_tcl is FALSE!\n");
699 if (constants
->Count
== 0)
702 BEGIN_CS(constants
->Count
* 4 + 3);
703 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
704 (r300screen
->caps
->is_r500
?
705 R500_PVS_CONST_START
: R300_PVS_CONST_START
));
706 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, constants
->Count
* 4);
707 for (i
= 0; i
< constants
->Count
; i
++) {
708 const float * data
= get_shader_constant(r300
,
709 &constants
->Constants
[i
],
710 &r300
->shader_constants
[PIPE_SHADER_VERTEX
]);
719 void r300_emit_viewport_state(struct r300_context
* r300
,
720 struct r300_viewport_state
* viewport
)
725 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
726 OUT_CS_32F(viewport
->xscale
);
727 OUT_CS_32F(viewport
->xoffset
);
728 OUT_CS_32F(viewport
->yscale
);
729 OUT_CS_32F(viewport
->yoffset
);
730 OUT_CS_32F(viewport
->zscale
);
731 OUT_CS_32F(viewport
->zoffset
);
733 if (r300
->rs_state
->enable_vte
) {
734 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
736 OUT_CS_REG(R300_VAP_VTE_CNTL
, 0);
741 void r300_flush_textures(struct r300_context
* r300
)
746 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
747 OUT_CS_REG(R300_TX_ENABLE
, (1 << r300
->texture_count
) - 1);
751 static void r300_flush_pvs(struct r300_context
* r300
)
756 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
760 /* Emit all dirty state. */
761 void r300_emit_dirty_state(struct r300_context
* r300
)
763 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
764 struct r300_texture
* tex
;
765 int i
, dirty_tex
= 0;
766 boolean invalid
= FALSE
;
768 if (!(r300
->dirty_state
)) {
772 r300_update_derived_state(r300
);
775 r300
->winsys
->reset_bos(r300
->winsys
);
779 /* Color buffers... */
780 for (i
= 0; i
< r300
->framebuffer_state
.nr_cbufs
; i
++) {
781 tex
= (struct r300_texture
*)r300
->framebuffer_state
.cbufs
[i
]->texture
;
782 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
783 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
784 0, RADEON_GEM_DOMAIN_VRAM
)) {
785 r300
->context
.flush(&r300
->context
, 0, NULL
);
789 /* ...depth buffer... */
790 if (r300
->framebuffer_state
.zsbuf
) {
791 tex
= (struct r300_texture
*)r300
->framebuffer_state
.zsbuf
->texture
;
792 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
793 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
794 0, RADEON_GEM_DOMAIN_VRAM
)) {
795 r300
->context
.flush(&r300
->context
, 0, NULL
);
800 for (i
= 0; i
< r300
->texture_count
; i
++) {
801 tex
= r300
->textures
[i
];
804 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
805 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0)) {
806 r300
->context
.flush(&r300
->context
, 0, NULL
);
810 /* ...occlusion query buffer... */
811 if (!r300
->winsys
->add_buffer(r300
->winsys
, r300
->oqbo
,
812 0, RADEON_GEM_DOMAIN_GTT
)) {
813 r300
->context
.flush(&r300
->context
, 0, NULL
);
816 /* ...and vertex buffer. */
818 if (!r300
->winsys
->add_buffer(r300
->winsys
, r300
->vbo
,
819 RADEON_GEM_DOMAIN_GTT
, 0)) {
820 r300
->context
.flush(&r300
->context
, 0, NULL
);
824 debug_printf("No VBO while emitting dirty state!\n");
826 if (!r300
->winsys
->validate(r300
->winsys
)) {
827 r300
->context
.flush(&r300
->context
, 0, NULL
);
830 debug_printf("r300: Stuck in validation loop, gonna quit now.");
837 if (r300
->dirty_state
& R300_NEW_QUERY
) {
838 r300_emit_query_start(r300
);
839 r300
->dirty_state
&= ~R300_NEW_QUERY
;
842 if (r300
->dirty_state
& R300_NEW_BLEND
) {
843 r300_emit_blend_state(r300
, r300
->blend_state
);
844 r300
->dirty_state
&= ~R300_NEW_BLEND
;
847 if (r300
->dirty_state
& R300_NEW_BLEND_COLOR
) {
848 r300_emit_blend_color_state(r300
, r300
->blend_color_state
);
849 r300
->dirty_state
&= ~R300_NEW_BLEND_COLOR
;
852 if (r300
->dirty_state
& R300_NEW_CLIP
) {
853 r300_emit_clip_state(r300
, &r300
->clip_state
);
854 r300
->dirty_state
&= ~R300_NEW_CLIP
;
857 if (r300
->dirty_state
& R300_NEW_DSA
) {
858 r300_emit_dsa_state(r300
, r300
->dsa_state
);
859 r300
->dirty_state
&= ~R300_NEW_DSA
;
862 if (r300
->dirty_state
& R300_NEW_FRAGMENT_SHADER
) {
863 if (r300screen
->caps
->is_r500
) {
864 r500_emit_fragment_program_code(r300
, &r300
->fs
->code
);
866 r300_emit_fragment_program_code(r300
, &r300
->fs
->code
);
868 r300
->dirty_state
&= ~R300_NEW_FRAGMENT_SHADER
;
871 if (r300
->dirty_state
& R300_NEW_FRAGMENT_SHADER_CONSTANTS
) {
872 if (r300screen
->caps
->is_r500
) {
873 r500_emit_fs_constant_buffer(r300
, &r300
->fs
->code
.constants
);
875 r300_emit_fs_constant_buffer(r300
, &r300
->fs
->code
.constants
);
877 r300
->dirty_state
&= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS
;
880 if (r300
->dirty_state
& R300_NEW_FRAMEBUFFERS
) {
881 r300_emit_fb_state(r300
, &r300
->framebuffer_state
);
882 r300
->dirty_state
&= ~R300_NEW_FRAMEBUFFERS
;
885 if (r300
->dirty_state
& R300_NEW_RASTERIZER
) {
886 r300_emit_rs_state(r300
, r300
->rs_state
);
887 r300
->dirty_state
&= ~R300_NEW_RASTERIZER
;
890 if (r300
->dirty_state
& R300_NEW_RS_BLOCK
) {
891 r300_emit_rs_block_state(r300
, r300
->rs_block
);
892 r300
->dirty_state
&= ~R300_NEW_RS_BLOCK
;
895 if (r300
->dirty_state
& R300_NEW_SCISSOR
) {
896 r300_emit_scissor_state(r300
, r300
->scissor_state
);
897 r300
->dirty_state
&= ~R300_NEW_SCISSOR
;
900 /* Samplers and textures are tracked separately but emitted together. */
901 if (r300
->dirty_state
&
902 (R300_ANY_NEW_SAMPLERS
| R300_ANY_NEW_TEXTURES
)) {
903 for (i
= 0; i
< MIN2(r300
->sampler_count
, r300
->texture_count
); i
++) {
904 if (r300
->dirty_state
&
905 ((R300_NEW_SAMPLER
<< i
) | (R300_NEW_TEXTURE
<< i
))) {
906 if (r300
->textures
[i
])
907 r300_emit_texture(r300
,
908 r300
->sampler_states
[i
],
912 ~((R300_NEW_SAMPLER
<< i
) | (R300_NEW_TEXTURE
<< i
));
916 r300
->dirty_state
&= ~(R300_ANY_NEW_SAMPLERS
| R300_ANY_NEW_TEXTURES
);
919 if (r300
->dirty_state
& R300_NEW_VIEWPORT
) {
920 r300_emit_viewport_state(r300
, r300
->viewport_state
);
921 r300
->dirty_state
&= ~R300_NEW_VIEWPORT
;
925 r300_flush_textures(r300
);
928 if (r300
->dirty_state
& R300_NEW_VERTEX_FORMAT
) {
929 r300_emit_vertex_format_state(r300
);
930 r300
->dirty_state
&= ~R300_NEW_VERTEX_FORMAT
;
933 if (r300
->dirty_state
& (R300_NEW_VERTEX_SHADER
| R300_NEW_VERTEX_SHADER_CONSTANTS
)) {
934 r300_flush_pvs(r300
);
937 if (r300
->dirty_state
& R300_NEW_VERTEX_SHADER
) {
938 r300_emit_vertex_shader(r300
, r300
->vs
);
939 r300
->dirty_state
&= ~R300_NEW_VERTEX_SHADER
;
942 if (r300
->dirty_state
& R300_NEW_VERTEX_SHADER_CONSTANTS
) {
943 r300_emit_vs_constant_buffer(r300
, &r300
->vs
->code
.constants
);
944 r300
->dirty_state
&= ~R300_NEW_VERTEX_SHADER_CONSTANTS
;
948 assert(r300->dirty_state == 0);
951 /* Finally, emit the VBO. */
952 r300_emit_vertex_buffer(r300
);