r300g: add support for color0 writes to all bound color buffers.
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29
30 #include "r300_context.h"
31 #include "r300_cb.h"
32 #include "r300_cs.h"
33 #include "r300_emit.h"
34 #include "r300_fs.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
37 #include "r300_vs.h"
38
39 void r300_emit_blend_state(struct r300_context* r300,
40 unsigned size, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 struct pipe_framebuffer_state* fb =
44 (struct pipe_framebuffer_state*)r300->fb_state.state;
45 CS_LOCALS(r300);
46
47 if (fb->nr_cbufs) {
48 WRITE_CS_TABLE(blend->cb, size);
49 } else {
50 WRITE_CS_TABLE(blend->cb_no_readwrite, size);
51 }
52 }
53
54 void r300_emit_blend_color_state(struct r300_context* r300,
55 unsigned size, void* state)
56 {
57 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
58 CS_LOCALS(r300);
59
60 WRITE_CS_TABLE(bc->cb, size);
61 }
62
63 void r300_emit_clip_state(struct r300_context* r300,
64 unsigned size, void* state)
65 {
66 struct r300_clip_state* clip = (struct r300_clip_state*)state;
67 CS_LOCALS(r300);
68
69 WRITE_CS_TABLE(clip->cb, size);
70 }
71
72 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
73 {
74 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
75 struct pipe_framebuffer_state* fb =
76 (struct pipe_framebuffer_state*)r300->fb_state.state;
77 CS_LOCALS(r300);
78
79 if (fb->zsbuf) {
80 WRITE_CS_TABLE(&dsa->cb_begin, size);
81 } else {
82 WRITE_CS_TABLE(dsa->cb_no_readwrite, size);
83 }
84 }
85
86 static void get_rc_constant_state(
87 float vec[4],
88 struct r300_context * r300,
89 struct rc_constant * constant)
90 {
91 struct r300_textures_state* texstate = r300->textures_state.state;
92 struct r300_texture *tex;
93
94 assert(constant->Type == RC_CONSTANT_STATE);
95
96 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
97 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
98 * state factors. */
99
100 switch (constant->u.State[0]) {
101 /* Factor for converting rectangle coords to
102 * normalized coords. Should only show up on non-r500. */
103 case RC_STATE_R300_TEXRECT_FACTOR:
104 tex = r300_texture(texstate->sampler_views[constant->u.State[1]]->base.texture);
105 vec[0] = 1.0 / tex->desc.width0;
106 vec[1] = 1.0 / tex->desc.height0;
107 vec[2] = 0;
108 vec[3] = 1;
109 break;
110
111 case RC_STATE_R300_TEXSCALE_FACTOR:
112 tex = r300_texture(texstate->sampler_views[constant->u.State[1]]->base.texture);
113 /* Add a small number to the texture size to work around rounding errors in hw. */
114 vec[0] = tex->desc.b.b.width0 / (tex->desc.width0 + 0.001f);
115 vec[1] = tex->desc.b.b.height0 / (tex->desc.height0 + 0.001f);
116 vec[2] = tex->desc.b.b.depth0 / (tex->desc.depth0 + 0.001f);
117 vec[3] = 1;
118 break;
119
120 case RC_STATE_R300_VIEWPORT_SCALE:
121 vec[0] = r300->viewport.scale[0];
122 vec[1] = r300->viewport.scale[1];
123 vec[2] = r300->viewport.scale[2];
124 vec[3] = 1;
125 break;
126
127 case RC_STATE_R300_VIEWPORT_OFFSET:
128 vec[0] = r300->viewport.translate[0];
129 vec[1] = r300->viewport.translate[1];
130 vec[2] = r300->viewport.translate[2];
131 vec[3] = 1;
132 break;
133
134 default:
135 fprintf(stderr, "r300: Implementation error: "
136 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
137 vec[0] = 0;
138 vec[1] = 0;
139 vec[2] = 0;
140 vec[3] = 1;
141 }
142 }
143
144 /* Convert a normal single-precision float into the 7.16 format
145 * used by the R300 fragment shader.
146 */
147 uint32_t pack_float24(float f)
148 {
149 union {
150 float fl;
151 uint32_t u;
152 } u;
153 float mantissa;
154 int exponent;
155 uint32_t float24 = 0;
156
157 if (f == 0.0)
158 return 0;
159
160 u.fl = f;
161
162 mantissa = frexpf(f, &exponent);
163
164 /* Handle -ve */
165 if (mantissa < 0) {
166 float24 |= (1 << 23);
167 mantissa = mantissa * -1.0;
168 }
169 /* Handle exponent, bias of 63 */
170 exponent += 62;
171 float24 |= (exponent << 16);
172 /* Kill 7 LSB of mantissa */
173 float24 |= (u.u & 0x7FFFFF) >> 7;
174
175 return float24;
176 }
177
178 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
179 {
180 struct r300_fragment_shader *fs = r300_fs(r300);
181 CS_LOCALS(r300);
182
183 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
184 }
185
186 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
187 {
188 struct r300_fragment_shader *fs = r300_fs(r300);
189 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
190 unsigned count = fs->shader->externals_count;
191 unsigned i, j;
192 CS_LOCALS(r300);
193
194 if (count == 0)
195 return;
196
197 BEGIN_CS(size);
198 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
199 if (buf->remap_table){
200 for (i = 0; i < count; i++) {
201 float *data = (float*)&buf->ptr[buf->remap_table[i]*4];
202 for (j = 0; j < 4; j++)
203 OUT_CS(pack_float24(data[j]));
204 }
205 } else {
206 for (i = 0; i < count; i++)
207 for (j = 0; j < 4; j++)
208 OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j]));
209 }
210
211 END_CS;
212 }
213
214 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
215 {
216 struct r300_fragment_shader *fs = r300_fs(r300);
217 struct rc_constant_list *constants = &fs->shader->code.constants;
218 unsigned i;
219 unsigned count = fs->shader->rc_state_count;
220 unsigned first = fs->shader->externals_count;
221 unsigned end = constants->Count;
222 unsigned j;
223 CS_LOCALS(r300);
224
225 if (count == 0)
226 return;
227
228 BEGIN_CS(size);
229 for(i = first; i < end; ++i) {
230 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
231 float data[4];
232
233 get_rc_constant_state(data, r300, &constants->Constants[i]);
234
235 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
236 for (j = 0; j < 4; j++)
237 OUT_CS(pack_float24(data[j]));
238 }
239 }
240 END_CS;
241 }
242
243 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
244 {
245 struct r300_fragment_shader *fs = r300_fs(r300);
246 CS_LOCALS(r300);
247
248 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
249 }
250
251 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
252 {
253 struct r300_fragment_shader *fs = r300_fs(r300);
254 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
255 unsigned count = fs->shader->externals_count;
256 CS_LOCALS(r300);
257
258 if (count == 0)
259 return;
260
261 BEGIN_CS(size);
262 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
263 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
264 if (buf->remap_table){
265 for (unsigned i = 0; i < count; i++) {
266 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
267 OUT_CS_TABLE(data, 4);
268 }
269 } else {
270 OUT_CS_TABLE(buf->ptr, count * 4);
271 }
272 END_CS;
273 }
274
275 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
276 {
277 struct r300_fragment_shader *fs = r300_fs(r300);
278 struct rc_constant_list *constants = &fs->shader->code.constants;
279 unsigned i;
280 unsigned count = fs->shader->rc_state_count;
281 unsigned first = fs->shader->externals_count;
282 unsigned end = constants->Count;
283 CS_LOCALS(r300);
284
285 if (count == 0)
286 return;
287
288 BEGIN_CS(size);
289 for(i = first; i < end; ++i) {
290 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
291 float data[4];
292
293 get_rc_constant_state(data, r300, &constants->Constants[i]);
294
295 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
296 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
297 (i & R500_GA_US_VECTOR_INDEX_MASK));
298 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
299 OUT_CS_TABLE(data, 4);
300 }
301 }
302 END_CS;
303 }
304
305 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
306 {
307 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
308 struct pipe_framebuffer_state* fb =
309 (struct pipe_framebuffer_state*)r300->fb_state.state;
310 uint32_t height = fb->height;
311 uint32_t width = fb->width;
312 CS_LOCALS(r300);
313
314 if (r300->cbzb_clear) {
315 struct r300_surface *surf = r300_surface(fb->cbufs[0]);
316
317 height = surf->cbzb_height;
318 width = surf->cbzb_width;
319 }
320
321 DBG(r300, DBG_SCISSOR,
322 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
323 width, height, r300->cbzb_clear ? "YES" : "NO");
324
325 BEGIN_CS(size);
326
327 /* Set up scissors.
328 * By writing to the SC registers, SC & US assert idle. */
329 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
330 if (r300->screen->caps.is_r500) {
331 OUT_CS(0);
332 OUT_CS(((width - 1) << R300_SCISSORS_X_SHIFT) |
333 ((height - 1) << R300_SCISSORS_Y_SHIFT));
334 } else {
335 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
336 (1440 << R300_SCISSORS_Y_SHIFT));
337 OUT_CS(((width + 1440-1) << R300_SCISSORS_X_SHIFT) |
338 ((height + 1440-1) << R300_SCISSORS_Y_SHIFT));
339 }
340
341 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
342 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
343 END_CS;
344 }
345
346 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
347 {
348 struct r300_aa_state *aa = (struct r300_aa_state*)state;
349 CS_LOCALS(r300);
350
351 BEGIN_CS(size);
352 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
353
354 if (aa->dest) {
355 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET, 1);
356 OUT_CS_RELOC(aa->dest->cs_buffer, aa->dest->offset, 0, aa->dest->domain);
357
358 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_PITCH, 1);
359 OUT_CS_RELOC(aa->dest->cs_buffer, aa->dest->pitch, 0, aa->dest->domain);
360 }
361
362 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, aa->aaresolve_ctl);
363 END_CS;
364 }
365
366 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
367 {
368 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
369 struct r300_surface* surf;
370 unsigned i;
371 boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
372 uint32_t rb3d_cctl = 0;
373
374 CS_LOCALS(r300);
375
376 BEGIN_CS(size);
377
378 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
379 * what we usually want. */
380 if (r300->screen->caps.is_r500) {
381 rb3d_cctl = R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE;
382 }
383 if (r300_fragment_shader_writes_all(r300_fs(r300))) {
384 rb3d_cctl |= R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs);
385 }
386
387 OUT_CS_REG(R300_RB3D_CCTL, rb3d_cctl);
388
389 /* Set up colorbuffers. */
390 for (i = 0; i < fb->nr_cbufs; i++) {
391 surf = r300_surface(fb->cbufs[i]);
392
393 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
394 OUT_CS_RELOC(surf->cs_buffer, surf->offset, 0, surf->domain);
395
396 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
397 OUT_CS_RELOC(surf->cs_buffer, surf->pitch, 0, surf->domain);
398 }
399
400 /* Set up the ZB part of the CBZB clear. */
401 if (r300->cbzb_clear) {
402 surf = r300_surface(fb->cbufs[0]);
403
404 OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format);
405
406 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
407 OUT_CS_RELOC(surf->cs_buffer, surf->cbzb_midpoint_offset, 0, surf->domain);
408
409 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
410 OUT_CS_RELOC(surf->cs_buffer, surf->cbzb_pitch, 0, surf->domain);
411
412 DBG(r300, DBG_CBZB,
413 "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format,
414 surf->cbzb_pitch);
415 }
416 /* Set up a zbuffer. */
417 else if (fb->zsbuf) {
418 surf = r300_surface(fb->zsbuf);
419
420 OUT_CS_REG(R300_ZB_FORMAT, surf->format);
421
422 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
423 OUT_CS_RELOC(surf->cs_buffer, surf->offset, 0, surf->domain);
424
425 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
426 OUT_CS_RELOC(surf->cs_buffer, surf->pitch, 0, surf->domain);
427
428 if (can_hyperz) {
429 uint32_t surf_pitch;
430 struct r300_texture *tex;
431 int level = surf->base.u.tex.level;
432 tex = r300_texture(surf->base.texture);
433
434 surf_pitch = surf->pitch & R300_DEPTHPITCH_MASK;
435 /* HiZ RAM. */
436 if (r300->screen->caps.hiz_ram) {
437 if (tex->hiz_mem[level]) {
438 OUT_CS_REG(R300_ZB_HIZ_OFFSET, tex->hiz_mem[level]->ofs << 2);
439 OUT_CS_REG(R300_ZB_HIZ_PITCH, surf_pitch);
440 } else {
441 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
442 OUT_CS_REG(R300_ZB_HIZ_PITCH, 0);
443 }
444 }
445 /* Z Mask RAM. (compressed zbuffer) */
446 if (tex->zmask_mem[level]) {
447 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, tex->zmask_mem[level]->ofs << 2);
448 OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf_pitch);
449 } else {
450 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
451 OUT_CS_REG(R300_ZB_ZMASK_PITCH, 0);
452 }
453 }
454 }
455
456 END_CS;
457 }
458
459 void r300_emit_hyperz_state(struct r300_context *r300,
460 unsigned size, void *state)
461 {
462 struct r300_hyperz_state *z = state;
463 CS_LOCALS(r300);
464 if (z->flush)
465 WRITE_CS_TABLE(&z->cb_flush_begin, size);
466 else
467 WRITE_CS_TABLE(&z->cb_begin, size - 2);
468 }
469
470 void r300_emit_hyperz_end(struct r300_context *r300)
471 {
472 struct r300_hyperz_state z =
473 *(struct r300_hyperz_state*)r300->hyperz_state.state;
474
475 z.flush = 1;
476 z.zb_bw_cntl = 0;
477 z.zb_depthclearvalue = 0;
478 z.sc_hyperz = R300_SC_HYPERZ_ADJ_2;
479 z.gb_z_peq_config = 0;
480
481 r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z);
482 }
483
484 void r300_emit_fb_state_pipelined(struct r300_context *r300,
485 unsigned size, void *state)
486 {
487 struct pipe_framebuffer_state* fb =
488 (struct pipe_framebuffer_state*)r300->fb_state.state;
489 unsigned i, num_cbufs = fb->nr_cbufs;
490 CS_LOCALS(r300);
491
492 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be
493 * marked as UNUSED in the US block. */
494 if (r300_fragment_shader_writes_all(r300_fs(r300))) {
495 num_cbufs = MIN2(num_cbufs, 1);
496 }
497
498 BEGIN_CS(size);
499
500 /* Colorbuffer format in the US block.
501 * (must be written after unpipelined regs) */
502 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
503 for (i = 0; i < num_cbufs; i++) {
504 OUT_CS(r300_surface(fb->cbufs[i])->format);
505 }
506 for (; i < 4; i++) {
507 OUT_CS(R300_US_OUT_FMT_UNUSED);
508 }
509
510 /* Multisampling. Depends on framebuffer sample count.
511 * These are pipelined regs and as such cannot be moved
512 * to the AA state. */
513 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
514 unsigned mspos0 = 0x66666666;
515 unsigned mspos1 = 0x6666666;
516
517 if (fb->nr_cbufs && fb->cbufs[0]->texture->nr_samples > 1) {
518 /* Subsample placement. These may not be optimal. */
519 switch (fb->cbufs[0]->texture->nr_samples) {
520 case 2:
521 mspos0 = 0x33996633;
522 mspos1 = 0x6666663;
523 break;
524 case 3:
525 mspos0 = 0x33936933;
526 mspos1 = 0x6666663;
527 break;
528 case 4:
529 mspos0 = 0x33939933;
530 mspos1 = 0x3966663;
531 break;
532 case 6:
533 mspos0 = 0x22a2aa22;
534 mspos1 = 0x2a65672;
535 break;
536 default:
537 debug_printf("r300: Bad number of multisamples!\n");
538 }
539 }
540
541 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
542 OUT_CS(mspos0);
543 OUT_CS(mspos1);
544 }
545 END_CS;
546 }
547
548 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
549 {
550 struct r300_query *query = r300->query_current;
551 CS_LOCALS(r300);
552
553 if (!query)
554 return;
555
556 BEGIN_CS(size);
557 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
558 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
559 } else {
560 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
561 }
562 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
563 END_CS;
564 query->begin_emitted = TRUE;
565 query->flushed = FALSE;
566 }
567
568 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
569 struct r300_query *query)
570 {
571 struct r300_capabilities* caps = &r300->screen->caps;
572 struct r300_winsys_cs_buffer *buf = r300->query_current->cs_buffer;
573 CS_LOCALS(r300);
574
575 assert(caps->num_frag_pipes);
576
577 BEGIN_CS(6 * caps->num_frag_pipes + 2);
578 /* I'm not so sure I like this switch, but it's hard to be elegant
579 * when there's so many special cases...
580 *
581 * So here's the basic idea. For each pipe, enable writes to it only,
582 * then put out the relocation for ZPASS_ADDR, taking into account a
583 * 4-byte offset for each pipe. RV380 and older are special; they have
584 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
585 * so there's a chipset cap for that. */
586 switch (caps->num_frag_pipes) {
587 case 4:
588 /* pipe 3 only */
589 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
590 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
591 OUT_CS_RELOC(buf, (query->num_results + 3) * 4,
592 0, query->domain);
593 case 3:
594 /* pipe 2 only */
595 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
596 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
597 OUT_CS_RELOC(buf, (query->num_results + 2) * 4,
598 0, query->domain);
599 case 2:
600 /* pipe 1 only */
601 /* As mentioned above, accomodate RV380 and older. */
602 OUT_CS_REG(R300_SU_REG_DEST,
603 1 << (caps->high_second_pipe ? 3 : 1));
604 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
605 OUT_CS_RELOC(buf, (query->num_results + 1) * 4,
606 0, query->domain);
607 case 1:
608 /* pipe 0 only */
609 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
610 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
611 OUT_CS_RELOC(buf, (query->num_results + 0) * 4,
612 0, query->domain);
613 break;
614 default:
615 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
616 " pixel pipes!\n", caps->num_frag_pipes);
617 abort();
618 }
619
620 /* And, finally, reset it to normal... */
621 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
622 END_CS;
623 }
624
625 static void rv530_emit_query_end_single_z(struct r300_context *r300,
626 struct r300_query *query)
627 {
628 struct r300_winsys_cs_buffer *buf = r300->query_current->cs_buffer;
629 CS_LOCALS(r300);
630
631 BEGIN_CS(8);
632 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
633 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
634 OUT_CS_RELOC(buf, query->num_results * 4, 0, query->domain);
635 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
636 END_CS;
637 }
638
639 static void rv530_emit_query_end_double_z(struct r300_context *r300,
640 struct r300_query *query)
641 {
642 struct r300_winsys_cs_buffer *buf = r300->query_current->cs_buffer;
643 CS_LOCALS(r300);
644
645 BEGIN_CS(14);
646 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
647 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
648 OUT_CS_RELOC(buf, (query->num_results + 0) * 4, 0, query->domain);
649 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
650 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
651 OUT_CS_RELOC(buf, (query->num_results + 1) * 4, 0, query->domain);
652 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
653 END_CS;
654 }
655
656 void r300_emit_query_end(struct r300_context* r300)
657 {
658 struct r300_capabilities *caps = &r300->screen->caps;
659 struct r300_query *query = r300->query_current;
660
661 if (!query)
662 return;
663
664 if (query->begin_emitted == FALSE)
665 return;
666
667 if (caps->family == CHIP_FAMILY_RV530) {
668 if (caps->num_z_pipes == 2)
669 rv530_emit_query_end_double_z(r300, query);
670 else
671 rv530_emit_query_end_single_z(r300, query);
672 } else
673 r300_emit_query_end_frag_pipes(r300, query);
674
675 query->begin_emitted = FALSE;
676 query->num_results += query->num_pipes;
677
678 /* XXX grab all the results and reset the counter. */
679 if (query->num_results >= query->buffer_size / 4 - 4) {
680 query->num_results = (query->buffer_size / 4) / 2;
681 fprintf(stderr, "r300: Rewinding OQBO...\n");
682 }
683 }
684
685 void r300_emit_invariant_state(struct r300_context *r300,
686 unsigned size, void *state)
687 {
688 CS_LOCALS(r300);
689 WRITE_CS_TABLE(state, size);
690 }
691
692 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
693 {
694 struct r300_rs_state* rs = state;
695 CS_LOCALS(r300);
696
697 BEGIN_CS(size);
698 OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE);
699 if (rs->polygon_offset_enable) {
700 if (r300->zbuffer_bpp == 16) {
701 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5);
702 } else {
703 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5);
704 }
705 }
706 END_CS;
707 }
708
709 void r300_emit_rs_block_state(struct r300_context* r300,
710 unsigned size, void* state)
711 {
712 struct r300_rs_block* rs = (struct r300_rs_block*)state;
713 unsigned i;
714 /* It's the same for both INST and IP tables */
715 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
716 CS_LOCALS(r300);
717
718 if (DBG_ON(r300, DBG_RS_BLOCK)) {
719 r500_dump_rs_block(rs);
720
721 fprintf(stderr, "r300: RS emit:\n");
722
723 for (i = 0; i < count; i++)
724 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]);
725
726 for (i = 0; i < count; i++)
727 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]);
728
729 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n",
730 rs->count, rs->inst_count);
731 }
732
733 BEGIN_CS(size);
734 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
735 OUT_CS(rs->vap_vtx_state_cntl);
736 OUT_CS(rs->vap_vsm_vtx_assm);
737 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
738 OUT_CS(rs->vap_out_vtx_fmt[0]);
739 OUT_CS(rs->vap_out_vtx_fmt[1]);
740 OUT_CS_REG_SEQ(R300_GB_ENABLE, 1);
741 OUT_CS(rs->gb_enable);
742
743 if (r300->screen->caps.is_r500) {
744 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
745 } else {
746 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
747 }
748 OUT_CS_TABLE(rs->ip, count);
749
750 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
751 OUT_CS(rs->count);
752 OUT_CS(rs->inst_count);
753
754 if (r300->screen->caps.is_r500) {
755 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
756 } else {
757 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
758 }
759 OUT_CS_TABLE(rs->inst, count);
760 END_CS;
761 }
762
763 void r300_emit_scissor_state(struct r300_context* r300,
764 unsigned size, void* state)
765 {
766 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
767 CS_LOCALS(r300);
768
769 BEGIN_CS(size);
770 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
771 if (r300->screen->caps.is_r500) {
772 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
773 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
774 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
775 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
776 } else {
777 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
778 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
779 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
780 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
781 }
782 END_CS;
783 }
784
785 void r300_emit_textures_state(struct r300_context *r300,
786 unsigned size, void *state)
787 {
788 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
789 struct r300_texture_sampler_state *texstate;
790 struct r300_texture *tex;
791 unsigned i;
792 CS_LOCALS(r300);
793
794 BEGIN_CS(size);
795 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
796
797 for (i = 0; i < allstate->count; i++) {
798 if ((1 << i) & allstate->tx_enable) {
799 texstate = &allstate->regs[i];
800 tex = r300_texture(allstate->sampler_views[i]->base.texture);
801
802 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
803 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
804 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
805 texstate->border_color);
806
807 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
808 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
809 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
810
811 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
812 OUT_CS_TEX_RELOC(tex, texstate->format.tile_config, tex->domain,
813 0);
814 }
815 }
816 END_CS;
817 }
818
819 static void r300_update_aos_cb(struct r300_context *r300, unsigned packet_size)
820 {
821 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
822 struct pipe_vertex_element *velem = r300->velems->velem;
823 unsigned *hw_format_size = r300->velems->hw_format_size;
824 unsigned size1, size2, aos_count = r300->velems->count;
825 int i;
826 CB_LOCALS;
827
828 BEGIN_CB(r300->aos_cb, packet_size);
829 for (i = 0; i < aos_count - 1; i += 2) {
830 vb1 = &vbuf[velem[i].vertex_buffer_index];
831 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
832 size1 = hw_format_size[i];
833 size2 = hw_format_size[i+1];
834
835 OUT_CB(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
836 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
837 OUT_CB(vb1->buffer_offset + velem[i].src_offset);
838 OUT_CB(vb2->buffer_offset + velem[i+1].src_offset);
839 }
840
841 if (aos_count & 1) {
842 vb1 = &vbuf[velem[i].vertex_buffer_index];
843 size1 = hw_format_size[i];
844
845 OUT_CB(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
846 OUT_CB(vb1->buffer_offset + velem[i].src_offset);
847 }
848 END_CB;
849
850 r300->aos_dirty = FALSE;
851 }
852
853 void r300_emit_aos(struct r300_context* r300, int offset, boolean indexed)
854 {
855 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
856 struct pipe_vertex_element *velem = r300->velems->velem;
857 struct r300_buffer *buf;
858 int i;
859 unsigned aos_count = r300->velems->count;
860 unsigned packet_size = (aos_count * 3 + 1) / 2;
861 CS_LOCALS(r300);
862
863 BEGIN_CS(2 + packet_size + aos_count * 2);
864 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
865 OUT_CS(aos_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
866
867 if (!offset) {
868 if (r300->aos_dirty) {
869 r300_update_aos_cb(r300, packet_size);
870 }
871 OUT_CS_TABLE(r300->aos_cb, packet_size);
872 } else {
873 struct pipe_vertex_buffer *vb1, *vb2;
874 unsigned *hw_format_size = r300->velems->hw_format_size;
875 unsigned size1, size2;
876
877 for (i = 0; i < aos_count - 1; i += 2) {
878 vb1 = &vbuf[velem[i].vertex_buffer_index];
879 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
880 size1 = hw_format_size[i];
881 size2 = hw_format_size[i+1];
882
883 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
884 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
885 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
886 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
887 }
888
889 if (aos_count & 1) {
890 vb1 = &vbuf[velem[i].vertex_buffer_index];
891 size1 = hw_format_size[i];
892
893 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
894 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
895 }
896 }
897
898 for (i = 0; i < aos_count; i++) {
899 buf = r300_buffer(vbuf[velem[i].vertex_buffer_index].buffer);
900 OUT_CS_BUF_RELOC_NO_OFFSET(&buf->b.b, buf->domain, 0);
901 }
902 END_CS;
903 }
904
905 void r300_emit_aos_swtcl(struct r300_context *r300, boolean indexed)
906 {
907 CS_LOCALS(r300);
908
909 DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, "
910 "vertex size %d\n", r300->vbo,
911 r300->vertex_info.size);
912 /* Set the pointer to our vertex buffer. The emitted values are this:
913 * PACKET3 [3D_LOAD_VBPNTR]
914 * COUNT [1]
915 * FORMAT [size | stride << 8]
916 * OFFSET [offset into BO]
917 * VBPNTR [relocated BO]
918 */
919 BEGIN_CS(7);
920 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
921 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
922 OUT_CS(r300->vertex_info.size |
923 (r300->vertex_info.size << 8));
924 OUT_CS(r300->draw_vbo_offset);
925 OUT_CS_BUF_RELOC(r300->vbo, 0, r300_buffer(r300->vbo)->domain, 0);
926 END_CS;
927 }
928
929 void r300_emit_vertex_stream_state(struct r300_context* r300,
930 unsigned size, void* state)
931 {
932 struct r300_vertex_stream_state *streams =
933 (struct r300_vertex_stream_state*)state;
934 unsigned i;
935 CS_LOCALS(r300);
936
937 if (DBG_ON(r300, DBG_PSC)) {
938 fprintf(stderr, "r300: PSC emit:\n");
939
940 for (i = 0; i < streams->count; i++) {
941 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i,
942 streams->vap_prog_stream_cntl[i]);
943 }
944
945 for (i = 0; i < streams->count; i++) {
946 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
947 streams->vap_prog_stream_cntl_ext[i]);
948 }
949 }
950
951 BEGIN_CS(size);
952 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
953 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
954 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
955 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
956 END_CS;
957 }
958
959 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
960 {
961 CS_LOCALS(r300);
962
963 BEGIN_CS(size);
964 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
965 END_CS;
966 }
967
968 void r300_emit_vap_invariant_state(struct r300_context *r300,
969 unsigned size, void *state)
970 {
971 CS_LOCALS(r300);
972 WRITE_CS_TABLE(state, size);
973 }
974
975 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
976 {
977 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
978 struct r300_vertex_program_code* code = &vs->code;
979 struct r300_screen* r300screen = r300->screen;
980 unsigned instruction_count = code->length / 4;
981
982 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
983 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
984 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
985 unsigned temp_count = MAX2(code->num_temporaries, 1);
986
987 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
988 vtx_mem_size / output_count, 10);
989 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5);
990
991 CS_LOCALS(r300);
992
993 BEGIN_CS(size);
994
995 /* R300_VAP_PVS_CODE_CNTL_0
996 * R300_VAP_PVS_CONST_CNTL
997 * R300_VAP_PVS_CODE_CNTL_1
998 * See the r5xx docs for instructions on how to use these. */
999 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) |
1000 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
1001 R300_PVS_LAST_INST(instruction_count - 1));
1002 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, instruction_count - 1);
1003
1004 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
1005 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
1006 OUT_CS_TABLE(code->body.d, code->length);
1007
1008 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
1009 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
1010 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
1011 R300_PVS_VF_MAX_VTX_NUM(12) |
1012 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
1013
1014 /* Emit flow control instructions. */
1015 if (code->num_fc_ops) {
1016
1017 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops);
1018 if (r300screen->caps.is_r500) {
1019 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, code->num_fc_ops * 2);
1020 OUT_CS_TABLE(code->fc_op_addrs.r500, code->num_fc_ops * 2);
1021 } else {
1022 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, code->num_fc_ops);
1023 OUT_CS_TABLE(code->fc_op_addrs.r300, code->num_fc_ops);
1024 }
1025 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, code->num_fc_ops);
1026 OUT_CS_TABLE(code->fc_loop_index, code->num_fc_ops);
1027 }
1028
1029 END_CS;
1030 }
1031
1032 void r300_emit_vs_constants(struct r300_context* r300,
1033 unsigned size, void *state)
1034 {
1035 unsigned count =
1036 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
1037 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
1038 struct r300_vertex_shader *vs = (struct r300_vertex_shader*)r300->vs_state.state;
1039 unsigned i;
1040 int imm_first = vs->externals_count;
1041 int imm_end = vs->code.constants.Count;
1042 int imm_count = vs->immediates_count;
1043 CS_LOCALS(r300);
1044
1045 BEGIN_CS(size);
1046 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL,
1047 R300_PVS_CONST_BASE_OFFSET(buf->buffer_base) |
1048 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end - 1, 0)));
1049 if (vs->externals_count) {
1050 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1051 (r300->screen->caps.is_r500 ?
1052 R500_PVS_CONST_START : R300_PVS_CONST_START) + buf->buffer_base);
1053 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1054 if (buf->remap_table){
1055 for (i = 0; i < count; i++) {
1056 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
1057 OUT_CS_TABLE(data, 4);
1058 }
1059 } else {
1060 OUT_CS_TABLE(buf->ptr, count * 4);
1061 }
1062 }
1063
1064 /* Emit immediates. */
1065 if (imm_count) {
1066 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1067 (r300->screen->caps.is_r500 ?
1068 R500_PVS_CONST_START : R300_PVS_CONST_START) +
1069 buf->buffer_base + imm_first);
1070 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
1071 for (i = imm_first; i < imm_end; i++) {
1072 const float *data = vs->code.constants.Constants[i].u.Immediate;
1073 OUT_CS_TABLE(data, 4);
1074 }
1075 }
1076 END_CS;
1077 }
1078
1079 void r300_emit_viewport_state(struct r300_context* r300,
1080 unsigned size, void* state)
1081 {
1082 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1083 CS_LOCALS(r300);
1084
1085 BEGIN_CS(size);
1086 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1087 OUT_CS_TABLE(&viewport->xscale, 6);
1088 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1089 END_CS;
1090 }
1091
1092 static void r300_emit_hiz_line_clear(struct r300_context *r300, int start, uint16_t count, uint32_t val)
1093 {
1094 CS_LOCALS(r300);
1095 BEGIN_CS(4);
1096 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2);
1097 OUT_CS(start);
1098 OUT_CS(count);
1099 OUT_CS(val);
1100 END_CS;
1101 }
1102
1103 static void r300_emit_zmask_line_clear(struct r300_context *r300, int start, uint16_t count, uint32_t val)
1104 {
1105 CS_LOCALS(r300);
1106 BEGIN_CS(4);
1107 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2);
1108 OUT_CS(start);
1109 OUT_CS(count);
1110 OUT_CS(val);
1111 END_CS;
1112 }
1113
1114 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1115
1116 void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state)
1117 {
1118 struct pipe_framebuffer_state *fb =
1119 (struct pipe_framebuffer_state*)r300->fb_state.state;
1120 struct r300_hyperz_state *z =
1121 (struct r300_hyperz_state*)r300->hyperz_state.state;
1122 struct r300_screen* r300screen = r300->screen;
1123 uint32_t stride, offset = 0, height, offset_shift;
1124 struct r300_texture* tex;
1125 int i;
1126
1127 tex = r300_texture(fb->zsbuf->texture);
1128
1129 offset = tex->hiz_mem[fb->zsbuf->u.tex.level]->ofs;
1130 stride = tex->desc.stride_in_pixels[fb->zsbuf->u.tex.level];
1131
1132 /* convert from pixels to 4x4 blocks */
1133 stride = ALIGN_DIVUP(stride, 4);
1134
1135 stride = ALIGN_DIVUP(stride, r300screen->caps.num_frag_pipes);
1136 /* there are 4 blocks per dwords */
1137 stride = ALIGN_DIVUP(stride, 4);
1138
1139 height = ALIGN_DIVUP(fb->zsbuf->height, 4);
1140
1141 offset_shift = 2;
1142 offset_shift += (r300screen->caps.num_frag_pipes / 2);
1143
1144 for (i = 0; i < height; i++) {
1145 offset = i * stride;
1146 offset <<= offset_shift;
1147 r300_emit_hiz_line_clear(r300, offset, stride, 0xffffffff);
1148 }
1149 z->current_func = -1;
1150
1151 /* Mark the current zbuffer's hiz ram as in use. */
1152 tex->hiz_in_use[fb->zsbuf->u.tex.level] = TRUE;
1153 }
1154
1155 void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state)
1156 {
1157 struct pipe_framebuffer_state *fb =
1158 (struct pipe_framebuffer_state*)r300->fb_state.state;
1159 struct r300_screen* r300screen = r300->screen;
1160 uint32_t stride, offset = 0;
1161 struct r300_texture* tex;
1162 uint32_t i, height;
1163 int mult, offset_shift;
1164
1165 tex = r300_texture(fb->zsbuf->texture);
1166 stride = tex->desc.stride_in_pixels[fb->zsbuf->u.tex.level];
1167
1168 offset = tex->zmask_mem[fb->zsbuf->u.tex.level]->ofs;
1169
1170 if (r300->z_compression == RV350_Z_COMPRESS_88)
1171 mult = 8;
1172 else
1173 mult = 4;
1174
1175 height = ALIGN_DIVUP(fb->zsbuf->height, mult);
1176
1177 offset_shift = 4;
1178 offset_shift += (r300screen->caps.num_frag_pipes / 2);
1179 stride = ALIGN_DIVUP(stride, r300screen->caps.num_frag_pipes);
1180
1181 /* okay have width in pixels - divide by block width */
1182 stride = ALIGN_DIVUP(stride, mult);
1183 /* have width in blocks - divide by number of fragment pipes screen width */
1184 /* 16 blocks per dword */
1185 stride = ALIGN_DIVUP(stride, 16);
1186
1187 for (i = 0; i < height; i++) {
1188 offset = i * stride;
1189 offset <<= offset_shift;
1190 r300_emit_zmask_line_clear(r300, offset, stride, 0x0);//0xffffffff);
1191 }
1192
1193 /* Mark the current zbuffer's zmask as in use. */
1194 tex->zmask_in_use[fb->zsbuf->u.tex.level] = TRUE;
1195 }
1196
1197 void r300_emit_ztop_state(struct r300_context* r300,
1198 unsigned size, void* state)
1199 {
1200 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1201 CS_LOCALS(r300);
1202
1203 BEGIN_CS(size);
1204 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1205 END_CS;
1206 }
1207
1208 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1209 {
1210 CS_LOCALS(r300);
1211
1212 BEGIN_CS(size);
1213 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1214 END_CS;
1215 }
1216
1217 boolean r300_emit_buffer_validate(struct r300_context *r300,
1218 boolean do_validate_vertex_buffers,
1219 struct pipe_resource *index_buffer)
1220 {
1221 struct pipe_framebuffer_state* fb =
1222 (struct pipe_framebuffer_state*)r300->fb_state.state;
1223 struct r300_textures_state *texstate =
1224 (struct r300_textures_state*)r300->textures_state.state;
1225 struct r300_texture* tex;
1226 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1227 struct pipe_vertex_element *velem = r300->velems->velem;
1228 struct pipe_resource *pbuf;
1229 unsigned i;
1230
1231 /* Clean out BOs. */
1232 r300->rws->cs_reset_buffers(r300->cs);
1233
1234 /* Color buffers... */
1235 for (i = 0; i < fb->nr_cbufs; i++) {
1236 tex = r300_texture(fb->cbufs[i]->texture);
1237 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1238 r300->rws->cs_add_buffer(r300->cs, tex->cs_buffer, 0,
1239 r300_surface(fb->cbufs[i])->domain);
1240 }
1241 /* ...depth buffer... */
1242 if (fb->zsbuf) {
1243 tex = r300_texture(fb->zsbuf->texture);
1244 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1245 r300->rws->cs_add_buffer(r300->cs, tex->cs_buffer, 0,
1246 r300_surface(fb->zsbuf)->domain);
1247 }
1248 /* ...textures... */
1249 for (i = 0; i < texstate->count; i++) {
1250 if (!(texstate->tx_enable & (1 << i))) {
1251 continue;
1252 }
1253
1254 tex = r300_texture(texstate->sampler_views[i]->base.texture);
1255 r300->rws->cs_add_buffer(r300->cs, tex->cs_buffer, tex->domain, 0);
1256 }
1257 /* ...occlusion query buffer... */
1258 if (r300->query_current)
1259 r300->rws->cs_add_buffer(r300->cs, r300->query_current->cs_buffer,
1260 0, r300->query_current->domain);
1261 /* ...vertex buffer for SWTCL path... */
1262 if (r300->vbo)
1263 r300->rws->cs_add_buffer(r300->cs, r300_buffer(r300->vbo)->cs_buf,
1264 r300_buffer(r300->vbo)->domain, 0);
1265 /* ...vertex buffers for HWTCL path... */
1266 if (do_validate_vertex_buffers) {
1267 for (i = 0; i < r300->velems->count; i++) {
1268 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1269 if (!pbuf)
1270 continue;
1271
1272 r300->rws->cs_add_buffer(r300->cs, r300_buffer(pbuf)->cs_buf,
1273 r300_buffer(pbuf)->domain, 0);
1274 }
1275 }
1276 /* ...and index buffer for HWTCL path. */
1277 if (index_buffer)
1278 r300->rws->cs_add_buffer(r300->cs, r300_buffer(index_buffer)->cs_buf,
1279 r300_buffer(index_buffer)->domain, 0);
1280
1281 if (!r300->rws->cs_validate(r300->cs)) {
1282 return FALSE;
1283 }
1284
1285 return TRUE;
1286 }
1287
1288 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1289 {
1290 struct r300_atom* atom;
1291 unsigned dwords = 0;
1292
1293 foreach_dirty_atom(r300, atom) {
1294 if (atom->dirty) {
1295 dwords += atom->size;
1296 }
1297 }
1298
1299 /* let's reserve some more, just in case */
1300 dwords += 32;
1301
1302 return dwords;
1303 }
1304
1305 unsigned r300_get_num_cs_end_dwords(struct r300_context *r300)
1306 {
1307 unsigned dwords = 0;
1308
1309 /* Emitted in flush. */
1310 dwords += 26; /* emit_query_end */
1311 dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */
1312 if (r300->screen->caps.index_bias_supported)
1313 dwords += 2;
1314
1315 return dwords;
1316 }
1317
1318 /* Emit all dirty state. */
1319 void r300_emit_dirty_state(struct r300_context* r300)
1320 {
1321 struct r300_atom *atom;
1322
1323 foreach_dirty_atom(r300, atom) {
1324 if (atom->dirty) {
1325 atom->emit(r300, atom->size, atom->state);
1326 atom->dirty = FALSE;
1327 }
1328 }
1329
1330 r300->first_dirty = NULL;
1331 r300->last_dirty = NULL;
1332 r300->dirty_hw++;
1333 }