r300g: implement draw_instanced for HWTCL
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29
30 #include "r300_context.h"
31 #include "r300_cb.h"
32 #include "r300_cs.h"
33 #include "r300_emit.h"
34 #include "r300_fs.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
37 #include "r300_vs.h"
38
39 void r300_emit_blend_state(struct r300_context* r300,
40 unsigned size, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 struct pipe_framebuffer_state* fb =
44 (struct pipe_framebuffer_state*)r300->fb_state.state;
45 CS_LOCALS(r300);
46
47 if (fb->nr_cbufs) {
48 if (fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT)
49 WRITE_CS_TABLE(blend->cb_noclamp, size);
50 else
51 WRITE_CS_TABLE(blend->cb_clamp, size);
52 } else {
53 WRITE_CS_TABLE(blend->cb_no_readwrite, size);
54 }
55 }
56
57 void r300_emit_blend_color_state(struct r300_context* r300,
58 unsigned size, void* state)
59 {
60 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
61 CS_LOCALS(r300);
62
63 WRITE_CS_TABLE(bc->cb, size);
64 }
65
66 void r300_emit_clip_state(struct r300_context* r300,
67 unsigned size, void* state)
68 {
69 struct r300_clip_state* clip = (struct r300_clip_state*)state;
70 CS_LOCALS(r300);
71
72 WRITE_CS_TABLE(clip->cb, size);
73 }
74
75 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
76 {
77 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
78 struct pipe_framebuffer_state* fb =
79 (struct pipe_framebuffer_state*)r300->fb_state.state;
80 CS_LOCALS(r300);
81
82 if (fb->zsbuf) {
83 if (fb->nr_cbufs && fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT)
84 WRITE_CS_TABLE(&dsa->cb_begin_fp16, size);
85 else
86 WRITE_CS_TABLE(&dsa->cb_begin, size);
87 } else {
88 if (fb->nr_cbufs && fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT)
89 WRITE_CS_TABLE(dsa->cb_fp16_zb_no_readwrite, size);
90 else
91 WRITE_CS_TABLE(dsa->cb_zb_no_readwrite, size);
92 }
93 }
94
95 static void get_rc_constant_state(
96 float vec[4],
97 struct r300_context * r300,
98 struct rc_constant * constant)
99 {
100 struct r300_textures_state* texstate = r300->textures_state.state;
101 struct r300_resource *tex;
102
103 assert(constant->Type == RC_CONSTANT_STATE);
104
105 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
106 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
107 * state factors. */
108
109 switch (constant->u.State[0]) {
110 /* Factor for converting rectangle coords to
111 * normalized coords. Should only show up on non-r500. */
112 case RC_STATE_R300_TEXRECT_FACTOR:
113 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
114 vec[0] = 1.0 / tex->tex.width0;
115 vec[1] = 1.0 / tex->tex.height0;
116 vec[2] = 0;
117 vec[3] = 1;
118 break;
119
120 case RC_STATE_R300_TEXSCALE_FACTOR:
121 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
122 /* Add a small number to the texture size to work around rounding errors in hw. */
123 vec[0] = tex->b.b.b.width0 / (tex->tex.width0 + 0.001f);
124 vec[1] = tex->b.b.b.height0 / (tex->tex.height0 + 0.001f);
125 vec[2] = tex->b.b.b.depth0 / (tex->tex.depth0 + 0.001f);
126 vec[3] = 1;
127 break;
128
129 case RC_STATE_R300_VIEWPORT_SCALE:
130 vec[0] = r300->viewport.scale[0];
131 vec[1] = r300->viewport.scale[1];
132 vec[2] = r300->viewport.scale[2];
133 vec[3] = 1;
134 break;
135
136 case RC_STATE_R300_VIEWPORT_OFFSET:
137 vec[0] = r300->viewport.translate[0];
138 vec[1] = r300->viewport.translate[1];
139 vec[2] = r300->viewport.translate[2];
140 vec[3] = 1;
141 break;
142
143 default:
144 fprintf(stderr, "r300: Implementation error: "
145 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
146 vec[0] = 0;
147 vec[1] = 0;
148 vec[2] = 0;
149 vec[3] = 1;
150 }
151 }
152
153 /* Convert a normal single-precision float into the 7.16 format
154 * used by the R300 fragment shader.
155 */
156 uint32_t pack_float24(float f)
157 {
158 union {
159 float fl;
160 uint32_t u;
161 } u;
162 float mantissa;
163 int exponent;
164 uint32_t float24 = 0;
165
166 if (f == 0.0)
167 return 0;
168
169 u.fl = f;
170
171 mantissa = frexpf(f, &exponent);
172
173 /* Handle -ve */
174 if (mantissa < 0) {
175 float24 |= (1 << 23);
176 mantissa = mantissa * -1.0;
177 }
178 /* Handle exponent, bias of 63 */
179 exponent += 62;
180 float24 |= (exponent << 16);
181 /* Kill 7 LSB of mantissa */
182 float24 |= (u.u & 0x7FFFFF) >> 7;
183
184 return float24;
185 }
186
187 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
188 {
189 struct r300_fragment_shader *fs = r300_fs(r300);
190 CS_LOCALS(r300);
191
192 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
193 }
194
195 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
196 {
197 struct r300_fragment_shader *fs = r300_fs(r300);
198 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
199 unsigned count = fs->shader->externals_count;
200 unsigned i, j;
201 CS_LOCALS(r300);
202
203 if (count == 0)
204 return;
205
206 BEGIN_CS(size);
207 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
208 if (buf->remap_table){
209 for (i = 0; i < count; i++) {
210 float *data = (float*)&buf->ptr[buf->remap_table[i]*4];
211 for (j = 0; j < 4; j++)
212 OUT_CS(pack_float24(data[j]));
213 }
214 } else {
215 for (i = 0; i < count; i++)
216 for (j = 0; j < 4; j++)
217 OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j]));
218 }
219
220 END_CS;
221 }
222
223 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
224 {
225 struct r300_fragment_shader *fs = r300_fs(r300);
226 struct rc_constant_list *constants = &fs->shader->code.constants;
227 unsigned i;
228 unsigned count = fs->shader->rc_state_count;
229 unsigned first = fs->shader->externals_count;
230 unsigned end = constants->Count;
231 unsigned j;
232 CS_LOCALS(r300);
233
234 if (count == 0)
235 return;
236
237 BEGIN_CS(size);
238 for(i = first; i < end; ++i) {
239 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
240 float data[4];
241
242 get_rc_constant_state(data, r300, &constants->Constants[i]);
243
244 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
245 for (j = 0; j < 4; j++)
246 OUT_CS(pack_float24(data[j]));
247 }
248 }
249 END_CS;
250 }
251
252 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
253 {
254 struct r300_fragment_shader *fs = r300_fs(r300);
255 CS_LOCALS(r300);
256
257 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
258 }
259
260 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
261 {
262 struct r300_fragment_shader *fs = r300_fs(r300);
263 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
264 unsigned count = fs->shader->externals_count;
265 CS_LOCALS(r300);
266
267 if (count == 0)
268 return;
269
270 BEGIN_CS(size);
271 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
272 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
273 if (buf->remap_table){
274 for (unsigned i = 0; i < count; i++) {
275 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
276 OUT_CS_TABLE(data, 4);
277 }
278 } else {
279 OUT_CS_TABLE(buf->ptr, count * 4);
280 }
281 END_CS;
282 }
283
284 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
285 {
286 struct r300_fragment_shader *fs = r300_fs(r300);
287 struct rc_constant_list *constants = &fs->shader->code.constants;
288 unsigned i;
289 unsigned count = fs->shader->rc_state_count;
290 unsigned first = fs->shader->externals_count;
291 unsigned end = constants->Count;
292 CS_LOCALS(r300);
293
294 if (count == 0)
295 return;
296
297 BEGIN_CS(size);
298 for(i = first; i < end; ++i) {
299 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
300 float data[4];
301
302 get_rc_constant_state(data, r300, &constants->Constants[i]);
303
304 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
305 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
306 (i & R500_GA_US_VECTOR_INDEX_MASK));
307 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
308 OUT_CS_TABLE(data, 4);
309 }
310 }
311 END_CS;
312 }
313
314 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
315 {
316 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
317 struct pipe_framebuffer_state* fb =
318 (struct pipe_framebuffer_state*)r300->fb_state.state;
319 uint32_t height = fb->height;
320 uint32_t width = fb->width;
321 CS_LOCALS(r300);
322
323 if (r300->cbzb_clear) {
324 struct r300_surface *surf = r300_surface(fb->cbufs[0]);
325
326 height = surf->cbzb_height;
327 width = surf->cbzb_width;
328 }
329
330 DBG(r300, DBG_SCISSOR,
331 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
332 width, height, r300->cbzb_clear ? "YES" : "NO");
333
334 BEGIN_CS(size);
335
336 /* Set up scissors.
337 * By writing to the SC registers, SC & US assert idle. */
338 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
339 if (r300->screen->caps.is_r500) {
340 OUT_CS(0);
341 OUT_CS(((width - 1) << R300_SCISSORS_X_SHIFT) |
342 ((height - 1) << R300_SCISSORS_Y_SHIFT));
343 } else {
344 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
345 (1440 << R300_SCISSORS_Y_SHIFT));
346 OUT_CS(((width + 1440-1) << R300_SCISSORS_X_SHIFT) |
347 ((height + 1440-1) << R300_SCISSORS_Y_SHIFT));
348 }
349
350 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
351 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
352 END_CS;
353 }
354
355 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
356 {
357 struct r300_aa_state *aa = (struct r300_aa_state*)state;
358 CS_LOCALS(r300);
359
360 BEGIN_CS(size);
361 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
362
363 if (aa->dest) {
364 OUT_CS_REG(R300_RB3D_AARESOLVE_OFFSET, aa->dest->offset);
365 OUT_CS_RELOC(aa->dest);
366 OUT_CS_REG(R300_RB3D_AARESOLVE_PITCH, aa->dest->pitch);
367 }
368
369 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, aa->aaresolve_ctl);
370 END_CS;
371 }
372
373 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
374 {
375 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
376 struct r300_surface* surf;
377 unsigned i;
378 boolean can_hyperz = r300->rws->get_value(r300->rws, RADEON_VID_CAN_HYPERZ);
379 uint32_t rb3d_cctl = 0;
380
381 CS_LOCALS(r300);
382
383 BEGIN_CS(size);
384
385 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
386 * what we usually want. */
387 if (r300->screen->caps.is_r500) {
388 rb3d_cctl = R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE;
389 }
390 if (fb->nr_cbufs && r300->fb_multiwrite) {
391 rb3d_cctl |= R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs);
392 }
393
394 OUT_CS_REG(R300_RB3D_CCTL, rb3d_cctl);
395
396 /* Set up colorbuffers. */
397 for (i = 0; i < fb->nr_cbufs; i++) {
398 surf = r300_surface(fb->cbufs[i]);
399
400 OUT_CS_REG(R300_RB3D_COLOROFFSET0 + (4 * i), surf->offset);
401 OUT_CS_RELOC(surf);
402
403 OUT_CS_REG(R300_RB3D_COLORPITCH0 + (4 * i), surf->pitch);
404 OUT_CS_RELOC(surf);
405 }
406
407 /* Set up the ZB part of the CBZB clear. */
408 if (r300->cbzb_clear) {
409 surf = r300_surface(fb->cbufs[0]);
410
411 OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format);
412
413 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->cbzb_midpoint_offset);
414 OUT_CS_RELOC(surf);
415
416 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->cbzb_pitch);
417 OUT_CS_RELOC(surf);
418
419 DBG(r300, DBG_CBZB,
420 "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format,
421 surf->cbzb_pitch);
422 }
423 /* Set up a zbuffer. */
424 else if (fb->zsbuf) {
425 surf = r300_surface(fb->zsbuf);
426
427 OUT_CS_REG(R300_ZB_FORMAT, surf->format);
428
429 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->offset);
430 OUT_CS_RELOC(surf);
431
432 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->pitch);
433 OUT_CS_RELOC(surf);
434
435 if (can_hyperz) {
436 /* HiZ RAM. */
437 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
438 OUT_CS_REG(R300_ZB_HIZ_PITCH, surf->pitch_hiz);
439 /* Z Mask RAM. (compressed zbuffer) */
440 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
441 OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf->pitch_zmask);
442 }
443 }
444
445 END_CS;
446 }
447
448 void r300_emit_hyperz_state(struct r300_context *r300,
449 unsigned size, void *state)
450 {
451 struct r300_hyperz_state *z = state;
452 CS_LOCALS(r300);
453
454 if (z->flush)
455 WRITE_CS_TABLE(&z->cb_flush_begin, size);
456 else
457 WRITE_CS_TABLE(&z->cb_begin, size - 2);
458 }
459
460 void r300_emit_hyperz_end(struct r300_context *r300)
461 {
462 struct r300_hyperz_state z =
463 *(struct r300_hyperz_state*)r300->hyperz_state.state;
464
465 z.flush = 1;
466 z.zb_bw_cntl = 0;
467 z.zb_depthclearvalue = 0;
468 z.sc_hyperz = R300_SC_HYPERZ_ADJ_2;
469 z.gb_z_peq_config = 0;
470
471 r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z);
472 }
473
474 void r300_emit_fb_state_pipelined(struct r300_context *r300,
475 unsigned size, void *state)
476 {
477 struct pipe_framebuffer_state* fb =
478 (struct pipe_framebuffer_state*)r300->fb_state.state;
479 unsigned i, num_cbufs = fb->nr_cbufs;
480 unsigned mspos0, mspos1;
481 CS_LOCALS(r300);
482
483 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be
484 * marked as UNUSED in the US block. */
485 if (r300->fb_multiwrite) {
486 num_cbufs = MIN2(num_cbufs, 1);
487 }
488
489 BEGIN_CS(size);
490
491 /* Colorbuffer format in the US block.
492 * (must be written after unpipelined regs) */
493 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
494 for (i = 0; i < num_cbufs; i++) {
495 OUT_CS(r300_surface(fb->cbufs[i])->format);
496 }
497 for (; i < 1; i++) {
498 OUT_CS(R300_US_OUT_FMT_C4_8 |
499 R300_C0_SEL_B | R300_C1_SEL_G |
500 R300_C2_SEL_R | R300_C3_SEL_A);
501 }
502 for (; i < 4; i++) {
503 OUT_CS(R300_US_OUT_FMT_UNUSED);
504 }
505
506 /* Multisampling. Depends on framebuffer sample count.
507 * These are pipelined regs and as such cannot be moved
508 * to the AA state. */
509 mspos0 = 0x66666666;
510 mspos1 = 0x6666666;
511
512 if (fb->nr_cbufs && fb->cbufs[0]->texture->nr_samples > 1) {
513 /* Subsample placement. These may not be optimal. */
514 switch (fb->cbufs[0]->texture->nr_samples) {
515 case 2:
516 mspos0 = 0x33996633;
517 mspos1 = 0x6666663;
518 break;
519 case 3:
520 mspos0 = 0x33936933;
521 mspos1 = 0x6666663;
522 break;
523 case 4:
524 mspos0 = 0x33939933;
525 mspos1 = 0x3966663;
526 break;
527 case 6:
528 mspos0 = 0x22a2aa22;
529 mspos1 = 0x2a65672;
530 break;
531 default:
532 debug_printf("r300: Bad number of multisamples!\n");
533 }
534 }
535
536 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
537 OUT_CS(mspos0);
538 OUT_CS(mspos1);
539 END_CS;
540 }
541
542 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
543 {
544 struct r300_query *query = r300->query_current;
545 CS_LOCALS(r300);
546
547 if (!query)
548 return;
549
550 BEGIN_CS(size);
551 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
552 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
553 } else {
554 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
555 }
556 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
557 END_CS;
558 query->begin_emitted = TRUE;
559 }
560
561 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
562 struct r300_query *query)
563 {
564 struct r300_capabilities* caps = &r300->screen->caps;
565 CS_LOCALS(r300);
566
567 assert(caps->num_frag_pipes);
568
569 BEGIN_CS(6 * caps->num_frag_pipes + 2);
570 /* I'm not so sure I like this switch, but it's hard to be elegant
571 * when there's so many special cases...
572 *
573 * So here's the basic idea. For each pipe, enable writes to it only,
574 * then put out the relocation for ZPASS_ADDR, taking into account a
575 * 4-byte offset for each pipe. RV380 and older are special; they have
576 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
577 * so there's a chipset cap for that. */
578 switch (caps->num_frag_pipes) {
579 case 4:
580 /* pipe 3 only */
581 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
582 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 3) * 4);
583 OUT_CS_RELOC(r300->query_current);
584 case 3:
585 /* pipe 2 only */
586 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
587 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 2) * 4);
588 OUT_CS_RELOC(r300->query_current);
589 case 2:
590 /* pipe 1 only */
591 /* As mentioned above, accomodate RV380 and older. */
592 OUT_CS_REG(R300_SU_REG_DEST,
593 1 << (caps->high_second_pipe ? 3 : 1));
594 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4);
595 OUT_CS_RELOC(r300->query_current);
596 case 1:
597 /* pipe 0 only */
598 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
599 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4);
600 OUT_CS_RELOC(r300->query_current);
601 break;
602 default:
603 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
604 " pixel pipes!\n", caps->num_frag_pipes);
605 abort();
606 }
607
608 /* And, finally, reset it to normal... */
609 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
610 END_CS;
611 }
612
613 static void rv530_emit_query_end_single_z(struct r300_context *r300,
614 struct r300_query *query)
615 {
616 CS_LOCALS(r300);
617
618 BEGIN_CS(8);
619 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
620 OUT_CS_REG(R300_ZB_ZPASS_ADDR, query->num_results * 4);
621 OUT_CS_RELOC(r300->query_current);
622 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
623 END_CS;
624 }
625
626 static void rv530_emit_query_end_double_z(struct r300_context *r300,
627 struct r300_query *query)
628 {
629 CS_LOCALS(r300);
630
631 BEGIN_CS(14);
632 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
633 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4);
634 OUT_CS_RELOC(r300->query_current);
635 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
636 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4);
637 OUT_CS_RELOC(r300->query_current);
638 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
639 END_CS;
640 }
641
642 void r300_emit_query_end(struct r300_context* r300)
643 {
644 struct r300_capabilities *caps = &r300->screen->caps;
645 struct r300_query *query = r300->query_current;
646
647 if (!query)
648 return;
649
650 if (query->begin_emitted == FALSE)
651 return;
652
653 if (caps->family == CHIP_FAMILY_RV530) {
654 if (caps->num_z_pipes == 2)
655 rv530_emit_query_end_double_z(r300, query);
656 else
657 rv530_emit_query_end_single_z(r300, query);
658 } else
659 r300_emit_query_end_frag_pipes(r300, query);
660
661 query->begin_emitted = FALSE;
662 query->num_results += query->num_pipes;
663
664 /* XXX grab all the results and reset the counter. */
665 if (query->num_results >= query->buffer_size / 4 - 4) {
666 query->num_results = (query->buffer_size / 4) / 2;
667 fprintf(stderr, "r300: Rewinding OQBO...\n");
668 }
669 }
670
671 void r300_emit_invariant_state(struct r300_context *r300,
672 unsigned size, void *state)
673 {
674 CS_LOCALS(r300);
675 WRITE_CS_TABLE(state, size);
676 }
677
678 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
679 {
680 struct r300_rs_state* rs = state;
681 CS_LOCALS(r300);
682
683 BEGIN_CS(size);
684 OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE);
685 if (rs->polygon_offset_enable) {
686 if (r300->zbuffer_bpp == 16) {
687 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5);
688 } else {
689 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5);
690 }
691 }
692 END_CS;
693 }
694
695 void r300_emit_rs_block_state(struct r300_context* r300,
696 unsigned size, void* state)
697 {
698 struct r300_rs_block* rs = (struct r300_rs_block*)state;
699 unsigned i;
700 /* It's the same for both INST and IP tables */
701 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
702 CS_LOCALS(r300);
703
704 if (DBG_ON(r300, DBG_RS_BLOCK)) {
705 r500_dump_rs_block(rs);
706
707 fprintf(stderr, "r300: RS emit:\n");
708
709 for (i = 0; i < count; i++)
710 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]);
711
712 for (i = 0; i < count; i++)
713 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]);
714
715 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n",
716 rs->count, rs->inst_count);
717 }
718
719 BEGIN_CS(size);
720 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
721 OUT_CS(rs->vap_vtx_state_cntl);
722 OUT_CS(rs->vap_vsm_vtx_assm);
723 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
724 OUT_CS(rs->vap_out_vtx_fmt[0]);
725 OUT_CS(rs->vap_out_vtx_fmt[1]);
726 OUT_CS_REG_SEQ(R300_GB_ENABLE, 1);
727 OUT_CS(rs->gb_enable);
728
729 if (r300->screen->caps.is_r500) {
730 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
731 } else {
732 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
733 }
734 OUT_CS_TABLE(rs->ip, count);
735
736 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
737 OUT_CS(rs->count);
738 OUT_CS(rs->inst_count);
739
740 if (r300->screen->caps.is_r500) {
741 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
742 } else {
743 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
744 }
745 OUT_CS_TABLE(rs->inst, count);
746 END_CS;
747 }
748
749 void r300_emit_scissor_state(struct r300_context* r300,
750 unsigned size, void* state)
751 {
752 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
753 CS_LOCALS(r300);
754
755 BEGIN_CS(size);
756 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
757 if (r300->screen->caps.is_r500) {
758 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
759 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
760 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
761 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
762 } else {
763 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
764 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
765 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
766 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
767 }
768 END_CS;
769 }
770
771 void r300_emit_textures_state(struct r300_context *r300,
772 unsigned size, void *state)
773 {
774 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
775 struct r300_texture_sampler_state *texstate;
776 struct r300_resource *tex;
777 unsigned i;
778 boolean has_us_format = r300->screen->caps.has_us_format;
779 CS_LOCALS(r300);
780
781 BEGIN_CS(size);
782 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
783
784 for (i = 0; i < allstate->count; i++) {
785 if ((1 << i) & allstate->tx_enable) {
786 texstate = &allstate->regs[i];
787 tex = r300_resource(allstate->sampler_views[i]->base.texture);
788
789 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
790 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
791 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
792 texstate->border_color);
793
794 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
795 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
796 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
797
798 OUT_CS_REG(R300_TX_OFFSET_0 + (i * 4), texstate->format.tile_config);
799 OUT_CS_RELOC(tex);
800
801 if (has_us_format) {
802 OUT_CS_REG(R500_US_FORMAT0_0 + (i * 4),
803 texstate->format.us_format0);
804 }
805 }
806 }
807 END_CS;
808 }
809
810 void r300_emit_vertex_arrays(struct r300_context* r300, int offset,
811 boolean indexed, int instance_id)
812 {
813 struct pipe_vertex_buffer *vbuf = r300->vbuf_mgr->vertex_buffer;
814 struct pipe_resource **valid_vbuf = r300->vbuf_mgr->real_vertex_buffer;
815 struct pipe_vertex_element *velem = r300->velems->velem;
816 struct r300_resource *buf;
817 int i;
818 unsigned vertex_array_count = r300->velems->count;
819 unsigned real_vertex_array_count = vertex_array_count +
820 (vertex_array_count == 16 || instance_id == -1 ? 0 : 1);
821 unsigned packet_size = (real_vertex_array_count * 3 + 1) / 2;
822 struct pipe_vertex_buffer *vb1, *vb2;
823 unsigned *hw_format_size = r300->velems->format_size;
824 unsigned size1, size2, offset1, offset2, stride1, stride2;
825 CS_LOCALS(r300);
826
827 BEGIN_CS(2 + packet_size + real_vertex_array_count * 2);
828 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
829 OUT_CS(real_vertex_array_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
830
831 if (instance_id == -1) {
832 /* Non-instanced arrays. This ignores instance_divisor and instance_id. */
833 for (i = 0; i < vertex_array_count - 1; i += 2) {
834 vb1 = &vbuf[velem[i].vertex_buffer_index];
835 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
836 size1 = hw_format_size[i];
837 size2 = hw_format_size[i+1];
838
839 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
840 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
841 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
842 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
843 }
844
845 if (vertex_array_count & 1) {
846 vb1 = &vbuf[velem[i].vertex_buffer_index];
847 size1 = hw_format_size[i];
848
849 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
850 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
851 }
852
853 for (i = 0; i < vertex_array_count; i++) {
854 buf = r300_resource(valid_vbuf[velem[i].vertex_buffer_index]);
855 OUT_CS_RELOC(buf);
856 }
857 } else {
858 /* Instanced arrays. */
859 for (i = 0; i < vertex_array_count - 1; i += 2) {
860 vb1 = &vbuf[velem[i].vertex_buffer_index];
861 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
862 size1 = hw_format_size[i];
863 size2 = hw_format_size[i+1];
864
865 if (velem[i].instance_divisor) {
866 stride1 = 0;
867 offset1 = vb1->buffer_offset + velem[i].src_offset +
868 (instance_id / velem[i].instance_divisor) * vb1->stride;
869 } else {
870 stride1 = vb1->stride;
871 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride;
872 }
873 if (velem[i+1].instance_divisor) {
874 stride2 = 0;
875 offset2 = vb2->buffer_offset + velem[i+1].src_offset +
876 (instance_id / velem[i+1].instance_divisor) * vb2->stride;
877 } else {
878 stride2 = vb2->stride;
879 offset2 = vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride;
880 }
881
882 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1) |
883 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(stride2));
884 OUT_CS(offset1);
885 OUT_CS(offset2);
886 }
887
888 if (vertex_array_count & 1) {
889 vb1 = &vbuf[velem[i].vertex_buffer_index];
890 size1 = hw_format_size[i];
891
892 if (velem[i].instance_divisor) {
893 stride1 = 0;
894 offset1 = vb1->buffer_offset + velem[i].src_offset +
895 (instance_id / velem[i].instance_divisor) * vb1->stride;
896 } else {
897 stride1 = vb1->stride;
898 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride;
899 }
900
901 /* Insert vertex buffer containing InstanceID. */
902 if (vertex_array_count < 16) {
903 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1) |
904 R300_VBPNTR_SIZE1(4));
905 OUT_CS(offset1);
906 OUT_CS(4 * instance_id);
907 } else {
908 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1));
909 OUT_CS(offset1);
910 }
911 } else if (vertex_array_count < 16) {
912 /* Insert vertex buffer containing InstanceID. */
913 OUT_CS(R300_VBPNTR_SIZE0(4));
914 OUT_CS(4 * instance_id);
915 }
916
917 for (i = 0; i < vertex_array_count; i++) {
918 buf = r300_resource(valid_vbuf[velem[i].vertex_buffer_index]);
919 OUT_CS_RELOC(buf);
920 }
921 if (vertex_array_count < 16)
922 OUT_CS_RELOC(r300->vb_instanceid);
923 }
924 END_CS;
925 }
926
927 void r300_emit_vertex_arrays_swtcl(struct r300_context *r300, boolean indexed)
928 {
929 CS_LOCALS(r300);
930
931 DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, "
932 "vertex size %d\n", r300->vbo,
933 r300->vertex_info.size);
934 /* Set the pointer to our vertex buffer. The emitted values are this:
935 * PACKET3 [3D_LOAD_VBPNTR]
936 * COUNT [1]
937 * FORMAT [size | stride << 8]
938 * OFFSET [offset into BO]
939 * VBPNTR [relocated BO]
940 */
941 BEGIN_CS(7);
942 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
943 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
944 OUT_CS(r300->vertex_info.size |
945 (r300->vertex_info.size << 8));
946 OUT_CS(r300->draw_vbo_offset);
947 OUT_CS(0);
948 OUT_CS_RELOC(r300_resource(r300->vbo));
949 END_CS;
950 }
951
952 void r300_emit_vertex_stream_state(struct r300_context* r300,
953 unsigned size, void* state)
954 {
955 struct r300_vertex_element_state *velems =
956 (struct r300_vertex_element_state*)state;
957 struct r300_vertex_stream_state *streams;
958 unsigned i;
959 CS_LOCALS(r300);
960
961 if (r300->screen->caps.has_tcl && r300->instancing_enabled) {
962 streams = &velems->vertex_stream_instanced;
963 } else {
964 streams = &velems->vertex_stream;
965 }
966
967 if (DBG_ON(r300, DBG_PSC)) {
968 fprintf(stderr, "r300: PSC emit:\n");
969
970 for (i = 0; i < streams->count; i++) {
971 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i,
972 streams->vap_prog_stream_cntl[i]);
973 }
974
975 for (i = 0; i < streams->count; i++) {
976 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
977 streams->vap_prog_stream_cntl_ext[i]);
978 }
979 }
980
981 BEGIN_CS((1 + streams->count) * 2);
982 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
983 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
984 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
985 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
986 END_CS;
987 }
988
989 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
990 {
991 CS_LOCALS(r300);
992
993 BEGIN_CS(size);
994 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
995 END_CS;
996 }
997
998 void r300_emit_vap_invariant_state(struct r300_context *r300,
999 unsigned size, void *state)
1000 {
1001 CS_LOCALS(r300);
1002 WRITE_CS_TABLE(state, size);
1003 }
1004
1005 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
1006 {
1007 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
1008 struct r300_vertex_program_code* code = &vs->code;
1009 struct r300_screen* r300screen = r300->screen;
1010 unsigned instruction_count = code->length / 4;
1011
1012 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
1013 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
1014 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
1015 unsigned temp_count = MAX2(code->num_temporaries, 1);
1016
1017 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
1018 vtx_mem_size / output_count, 10);
1019 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5);
1020
1021 CS_LOCALS(r300);
1022
1023 BEGIN_CS(size);
1024
1025 /* R300_VAP_PVS_CODE_CNTL_0
1026 * R300_VAP_PVS_CONST_CNTL
1027 * R300_VAP_PVS_CODE_CNTL_1
1028 * See the r5xx docs for instructions on how to use these. */
1029 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) |
1030 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
1031 R300_PVS_LAST_INST(instruction_count - 1));
1032 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, instruction_count - 1);
1033
1034 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
1035 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
1036 OUT_CS_TABLE(code->body.d, code->length);
1037
1038 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
1039 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
1040 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
1041 R300_PVS_VF_MAX_VTX_NUM(12) |
1042 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
1043
1044 /* Emit flow control instructions. */
1045 if (code->num_fc_ops) {
1046
1047 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops);
1048 if (r300screen->caps.is_r500) {
1049 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, code->num_fc_ops * 2);
1050 OUT_CS_TABLE(code->fc_op_addrs.r500, code->num_fc_ops * 2);
1051 } else {
1052 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, code->num_fc_ops);
1053 OUT_CS_TABLE(code->fc_op_addrs.r300, code->num_fc_ops);
1054 }
1055 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, code->num_fc_ops);
1056 OUT_CS_TABLE(code->fc_loop_index, code->num_fc_ops);
1057 }
1058
1059 END_CS;
1060 }
1061
1062 void r300_emit_vs_constants(struct r300_context* r300,
1063 unsigned size, void *state)
1064 {
1065 unsigned count =
1066 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
1067 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
1068 struct r300_vertex_shader *vs = (struct r300_vertex_shader*)r300->vs_state.state;
1069 unsigned i;
1070 int imm_first = vs->externals_count;
1071 int imm_end = vs->code.constants.Count;
1072 int imm_count = vs->immediates_count;
1073 CS_LOCALS(r300);
1074
1075 BEGIN_CS(size);
1076 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL,
1077 R300_PVS_CONST_BASE_OFFSET(buf->buffer_base) |
1078 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end - 1, 0)));
1079 if (vs->externals_count) {
1080 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1081 (r300->screen->caps.is_r500 ?
1082 R500_PVS_CONST_START : R300_PVS_CONST_START) + buf->buffer_base);
1083 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1084 if (buf->remap_table){
1085 for (i = 0; i < count; i++) {
1086 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
1087 OUT_CS_TABLE(data, 4);
1088 }
1089 } else {
1090 OUT_CS_TABLE(buf->ptr, count * 4);
1091 }
1092 }
1093
1094 /* Emit immediates. */
1095 if (imm_count) {
1096 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1097 (r300->screen->caps.is_r500 ?
1098 R500_PVS_CONST_START : R300_PVS_CONST_START) +
1099 buf->buffer_base + imm_first);
1100 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
1101 for (i = imm_first; i < imm_end; i++) {
1102 const float *data = vs->code.constants.Constants[i].u.Immediate;
1103 OUT_CS_TABLE(data, 4);
1104 }
1105 }
1106 END_CS;
1107 }
1108
1109 void r300_emit_viewport_state(struct r300_context* r300,
1110 unsigned size, void* state)
1111 {
1112 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1113 CS_LOCALS(r300);
1114
1115 BEGIN_CS(size);
1116 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1117 OUT_CS_TABLE(&viewport->xscale, 6);
1118 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1119 END_CS;
1120 }
1121
1122 void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state)
1123 {
1124 struct pipe_framebuffer_state *fb =
1125 (struct pipe_framebuffer_state*)r300->fb_state.state;
1126 struct r300_resource* tex;
1127 CS_LOCALS(r300);
1128
1129 tex = r300_resource(fb->zsbuf->texture);
1130
1131 BEGIN_CS(size);
1132 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2);
1133 OUT_CS(0);
1134 OUT_CS(tex->tex.hiz_dwords[fb->zsbuf->u.tex.level]);
1135 OUT_CS(r300->hiz_clear_value);
1136 END_CS;
1137
1138 /* Mark the current zbuffer's hiz ram as in use. */
1139 r300->hiz_in_use = TRUE;
1140 r300->hiz_func = HIZ_FUNC_NONE;
1141 r300_mark_atom_dirty(r300, &r300->hyperz_state);
1142 }
1143
1144 void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state)
1145 {
1146 struct pipe_framebuffer_state *fb =
1147 (struct pipe_framebuffer_state*)r300->fb_state.state;
1148 struct r300_resource *tex;
1149 CS_LOCALS(r300);
1150
1151 tex = r300_resource(fb->zsbuf->texture);
1152
1153 BEGIN_CS(size);
1154 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2);
1155 OUT_CS(0);
1156 OUT_CS(tex->tex.zmask_dwords[fb->zsbuf->u.tex.level]);
1157 OUT_CS(0);
1158 END_CS;
1159
1160 /* Mark the current zbuffer's zmask as in use. */
1161 r300->zmask_in_use = TRUE;
1162 r300_mark_atom_dirty(r300, &r300->hyperz_state);
1163 }
1164
1165 void r300_emit_ztop_state(struct r300_context* r300,
1166 unsigned size, void* state)
1167 {
1168 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1169 CS_LOCALS(r300);
1170
1171 BEGIN_CS(size);
1172 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1173 END_CS;
1174 }
1175
1176 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1177 {
1178 CS_LOCALS(r300);
1179
1180 BEGIN_CS(size);
1181 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1182 END_CS;
1183 }
1184
1185 boolean r300_emit_buffer_validate(struct r300_context *r300,
1186 boolean do_validate_vertex_buffers,
1187 struct pipe_resource *index_buffer)
1188 {
1189 struct pipe_framebuffer_state *fb =
1190 (struct pipe_framebuffer_state*)r300->fb_state.state;
1191 struct r300_textures_state *texstate =
1192 (struct r300_textures_state*)r300->textures_state.state;
1193 struct r300_resource *tex;
1194 unsigned i;
1195 boolean flushed = FALSE;
1196
1197 validate:
1198 if (r300->fb_state.dirty) {
1199 /* Color buffers... */
1200 for (i = 0; i < fb->nr_cbufs; i++) {
1201 tex = r300_resource(fb->cbufs[i]->texture);
1202 assert(tex && tex->buf && "cbuf is marked, but NULL!");
1203 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf, 0,
1204 r300_surface(fb->cbufs[i])->domain);
1205 }
1206 /* ...depth buffer... */
1207 if (fb->zsbuf) {
1208 tex = r300_resource(fb->zsbuf->texture);
1209 assert(tex && tex->buf && "zsbuf is marked, but NULL!");
1210 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf, 0,
1211 r300_surface(fb->zsbuf)->domain);
1212 }
1213 }
1214 if (r300->textures_state.dirty) {
1215 /* ...textures... */
1216 for (i = 0; i < texstate->count; i++) {
1217 if (!(texstate->tx_enable & (1 << i))) {
1218 continue;
1219 }
1220
1221 tex = r300_resource(texstate->sampler_views[i]->base.texture);
1222 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf, tex->domain, 0);
1223 }
1224 }
1225 /* ...occlusion query buffer... */
1226 if (r300->query_current)
1227 r300->rws->cs_add_reloc(r300->cs, r300->query_current->cs_buf,
1228 0, r300->query_current->domain);
1229 /* ...vertex buffer for SWTCL path... */
1230 if (r300->vbo)
1231 r300->rws->cs_add_reloc(r300->cs, r300_resource(r300->vbo)->cs_buf,
1232 r300_resource(r300->vbo)->domain, 0);
1233 /* ...vertex buffers for HWTCL path... */
1234 if (do_validate_vertex_buffers && r300->vertex_arrays_dirty) {
1235 struct pipe_resource **buf = r300->vbuf_mgr->real_vertex_buffer;
1236 struct pipe_resource **last = r300->vbuf_mgr->real_vertex_buffer +
1237 r300->vbuf_mgr->nr_real_vertex_buffers;
1238 for (; buf != last; buf++) {
1239 if (!*buf)
1240 continue;
1241
1242 r300->rws->cs_add_reloc(r300->cs, r300_resource(*buf)->cs_buf,
1243 r300_resource(*buf)->domain, 0);
1244 }
1245 if (r300->instancing_enabled) {
1246 r300->rws->cs_add_reloc(r300->cs, r300->vb_instanceid->cs_buf,
1247 r300->vb_instanceid->domain, 0);
1248 }
1249 }
1250 /* ...and index buffer for HWTCL path. */
1251 if (index_buffer)
1252 r300->rws->cs_add_reloc(r300->cs, r300_resource(index_buffer)->cs_buf,
1253 r300_resource(index_buffer)->domain, 0);
1254
1255 /* Now do the validation. */
1256 if (!r300->rws->cs_validate(r300->cs)) {
1257 /* Ooops, an infinite loop, give up. */
1258 if (flushed)
1259 return FALSE;
1260
1261 r300_flush(&r300->context, RADEON_FLUSH_ASYNC, NULL);
1262 flushed = TRUE;
1263 goto validate;
1264 }
1265
1266 return TRUE;
1267 }
1268
1269 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1270 {
1271 struct r300_atom* atom;
1272 unsigned dwords = 0;
1273
1274 foreach_dirty_atom(r300, atom) {
1275 if (atom->dirty) {
1276 dwords += atom->size;
1277 }
1278 }
1279
1280 /* let's reserve some more, just in case */
1281 dwords += 32;
1282
1283 return dwords;
1284 }
1285
1286 unsigned r300_get_num_cs_end_dwords(struct r300_context *r300)
1287 {
1288 unsigned dwords = 0;
1289
1290 /* Emitted in flush. */
1291 dwords += 26; /* emit_query_end */
1292 dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */
1293 if (r300->screen->caps.is_r500)
1294 dwords += 2;
1295
1296 return dwords;
1297 }
1298
1299 /* Emit all dirty state. */
1300 void r300_emit_dirty_state(struct r300_context* r300)
1301 {
1302 struct r300_atom *atom;
1303
1304 foreach_dirty_atom(r300, atom) {
1305 if (atom->dirty) {
1306 atom->emit(r300, atom->size, atom->state);
1307 atom->dirty = FALSE;
1308 }
1309 }
1310
1311 r300->first_dirty = NULL;
1312 r300->last_dirty = NULL;
1313 r300->dirty_hw++;
1314 }