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Merge remote branch 'origin/opengl-es-v2'
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_state_derived.h"
36 #include "r300_state_inlines.h"
37 #include "r300_texture.h"
38 #include "r300_vs.h"
39
40 void r300_emit_blend_state(struct r300_context* r300, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 CS_LOCALS(r300);
44
45 BEGIN_CS(8);
46 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
47 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
48 if (r300->framebuffer_state.nr_cbufs) {
49 OUT_CS(blend->blend_control);
50 OUT_CS(blend->alpha_blend_control);
51 OUT_CS(blend->color_channel_mask);
52 } else {
53 OUT_CS(0);
54 OUT_CS(0);
55 OUT_CS(0);
56 /* XXX also disable fastfill here once it's supported */
57 }
58 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
59 END_CS;
60 }
61
62 void r300_emit_blend_color_state(struct r300_context* r300, void* state)
63 {
64 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
65 struct r300_screen* r300screen = r300_screen(r300->context.screen);
66 CS_LOCALS(r300);
67
68 if (r300screen->caps->is_r500) {
69 BEGIN_CS(3);
70 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
71 OUT_CS(bc->blend_color_red_alpha);
72 OUT_CS(bc->blend_color_green_blue);
73 END_CS;
74 } else {
75 BEGIN_CS(2);
76 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
77 END_CS;
78 }
79 }
80
81 void r300_emit_clip_state(struct r300_context* r300, void* state)
82 {
83 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
84 int i;
85 struct r300_screen* r300screen = r300_screen(r300->context.screen);
86 CS_LOCALS(r300);
87
88 if (r300screen->caps->has_tcl) {
89 BEGIN_CS(5 + (6 * 4));
90 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
91 (r300screen->caps->is_r500 ?
92 R500_PVS_UCP_START : R300_PVS_UCP_START));
93 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
94 for (i = 0; i < 6; i++) {
95 OUT_CS_32F(clip->ucp[i][0]);
96 OUT_CS_32F(clip->ucp[i][1]);
97 OUT_CS_32F(clip->ucp[i][2]);
98 OUT_CS_32F(clip->ucp[i][3]);
99 }
100 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
101 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
102 END_CS;
103 } else {
104 BEGIN_CS(2);
105 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
106 END_CS;
107 }
108
109 }
110
111 void r300_emit_dsa_state(struct r300_context* r300, void* state)
112 {
113 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
114 struct r300_screen* r300screen = r300_screen(r300->context.screen);
115 CS_LOCALS(r300);
116
117 BEGIN_CS(r300screen->caps->is_r500 ? 8 : 6);
118 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
119
120 /* not needed since we use the 8bit alpha ref */
121 /*if (r300screen->caps->is_r500) {
122 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
123 }*/
124
125 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
126
127 if (r300->framebuffer_state.zsbuf) {
128 OUT_CS(dsa->z_buffer_control);
129 OUT_CS(dsa->z_stencil_control);
130 } else {
131 OUT_CS(0);
132 OUT_CS(0);
133 }
134
135 OUT_CS(dsa->stencil_ref_mask);
136
137 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
138 if (r300screen->caps->is_r500) {
139 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
140 }
141 END_CS;
142 }
143
144 static const float * get_shader_constant(
145 struct r300_context * r300,
146 struct rc_constant * constant,
147 struct r300_constant_buffer * externals)
148 {
149 struct r300_viewport_state* viewport =
150 (struct r300_viewport_state*)r300->viewport_state.state;
151 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
152 struct pipe_texture *tex;
153
154 switch(constant->Type) {
155 case RC_CONSTANT_EXTERNAL:
156 return externals->constants[constant->u.External];
157
158 case RC_CONSTANT_IMMEDIATE:
159 return constant->u.Immediate;
160
161 case RC_CONSTANT_STATE:
162 switch (constant->u.State[0]) {
163 /* Factor for converting rectangle coords to
164 * normalized coords. Should only show up on non-r500. */
165 case RC_STATE_R300_TEXRECT_FACTOR:
166 tex = &r300->textures[constant->u.State[1]]->tex;
167 vec[0] = 1.0 / tex->width0;
168 vec[1] = 1.0 / tex->height0;
169 break;
170
171 /* Texture compare-fail value. */
172 /* XXX Since Gallium doesn't support GL_ARB_shadow_ambient,
173 * this is always (0,0,0,0), right? */
174 case RC_STATE_SHADOW_AMBIENT:
175 vec[3] = 0;
176 break;
177
178 case RC_STATE_R300_VIEWPORT_SCALE:
179 if (r300->tcl_bypass) {
180 vec[0] = 1;
181 vec[1] = 1;
182 vec[2] = 1;
183 } else {
184 vec[0] = viewport->xscale;
185 vec[1] = viewport->yscale;
186 vec[2] = viewport->zscale;
187 }
188 break;
189
190 case RC_STATE_R300_VIEWPORT_OFFSET:
191 if (!r300->tcl_bypass) {
192 vec[0] = viewport->xoffset;
193 vec[1] = viewport->yoffset;
194 vec[2] = viewport->zoffset;
195 }
196 break;
197
198 default:
199 debug_printf("r300: Implementation error: "
200 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
201 }
202 break;
203
204 default:
205 debug_printf("r300: Implementation error: "
206 "Unhandled constant type %d\n", constant->Type);
207 }
208
209 /* This should either be (0, 0, 0, 1), which should be a relatively safe
210 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
211 * state factors. */
212 return vec;
213 }
214
215 /* Convert a normal single-precision float into the 7.16 format
216 * used by the R300 fragment shader.
217 */
218 static uint32_t pack_float24(float f)
219 {
220 union {
221 float fl;
222 uint32_t u;
223 } u;
224 float mantissa;
225 int exponent;
226 uint32_t float24 = 0;
227
228 if (f == 0.0)
229 return 0;
230
231 u.fl = f;
232
233 mantissa = frexpf(f, &exponent);
234
235 /* Handle -ve */
236 if (mantissa < 0) {
237 float24 |= (1 << 23);
238 mantissa = mantissa * -1.0;
239 }
240 /* Handle exponent, bias of 63 */
241 exponent += 62;
242 float24 |= (exponent << 16);
243 /* Kill 7 LSB of mantissa */
244 float24 |= (u.u & 0x7FFFFF) >> 7;
245
246 return float24;
247 }
248
249 void r300_emit_fragment_program_code(struct r300_context* r300,
250 struct rX00_fragment_program_code* generic_code)
251 {
252 struct r300_fragment_program_code * code = &generic_code->code.r300;
253 int i;
254 CS_LOCALS(r300);
255
256 BEGIN_CS(15 +
257 code->alu.length * 4 +
258 (code->tex.length ? (1 + code->tex.length) : 0));
259
260 OUT_CS_REG(R300_US_CONFIG, code->config);
261 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
262 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
263
264 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
265 for(i = 0; i < 4; ++i)
266 OUT_CS(code->code_addr[i]);
267
268 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
269 for (i = 0; i < code->alu.length; i++)
270 OUT_CS(code->alu.inst[i].rgb_inst);
271
272 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
273 for (i = 0; i < code->alu.length; i++)
274 OUT_CS(code->alu.inst[i].rgb_addr);
275
276 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
277 for (i = 0; i < code->alu.length; i++)
278 OUT_CS(code->alu.inst[i].alpha_inst);
279
280 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
281 for (i = 0; i < code->alu.length; i++)
282 OUT_CS(code->alu.inst[i].alpha_addr);
283
284 if (code->tex.length) {
285 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
286 for(i = 0; i < code->tex.length; ++i)
287 OUT_CS(code->tex.inst[i]);
288 }
289
290 END_CS;
291 }
292
293 void r300_emit_fs_constant_buffer(struct r300_context* r300,
294 struct rc_constant_list* constants)
295 {
296 int i;
297 CS_LOCALS(r300);
298
299 if (constants->Count == 0)
300 return;
301
302 BEGIN_CS(constants->Count * 4 + 1);
303 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
304 for(i = 0; i < constants->Count; ++i) {
305 const float * data = get_shader_constant(r300,
306 &constants->Constants[i],
307 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
308 OUT_CS(pack_float24(data[0]));
309 OUT_CS(pack_float24(data[1]));
310 OUT_CS(pack_float24(data[2]));
311 OUT_CS(pack_float24(data[3]));
312 }
313 END_CS;
314 }
315
316 static void r300_emit_fragment_depth_config(struct r300_context* r300,
317 struct r300_fragment_shader* fs)
318 {
319 CS_LOCALS(r300);
320
321 BEGIN_CS(4);
322 if (r300_fragment_shader_writes_depth(fs)) {
323 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
324 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
325 } else {
326 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
327 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
328 }
329 END_CS;
330 }
331
332 void r500_emit_fragment_program_code(struct r300_context* r300,
333 struct rX00_fragment_program_code* generic_code)
334 {
335 struct r500_fragment_program_code * code = &generic_code->code.r500;
336 int i;
337 CS_LOCALS(r300);
338
339 BEGIN_CS(13 +
340 ((code->inst_end + 1) * 6));
341 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
342 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
343 OUT_CS_REG(R500_US_CODE_RANGE,
344 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
345 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
346 OUT_CS_REG(R500_US_CODE_ADDR,
347 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
348
349 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
350 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
351 for (i = 0; i <= code->inst_end; i++) {
352 OUT_CS(code->inst[i].inst0);
353 OUT_CS(code->inst[i].inst1);
354 OUT_CS(code->inst[i].inst2);
355 OUT_CS(code->inst[i].inst3);
356 OUT_CS(code->inst[i].inst4);
357 OUT_CS(code->inst[i].inst5);
358 }
359
360 END_CS;
361 }
362
363 void r500_emit_fs_constant_buffer(struct r300_context* r300,
364 struct rc_constant_list* constants)
365 {
366 int i;
367 CS_LOCALS(r300);
368
369 if (constants->Count == 0)
370 return;
371
372 BEGIN_CS(constants->Count * 4 + 3);
373 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
374 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
375 for (i = 0; i < constants->Count; i++) {
376 const float * data = get_shader_constant(r300,
377 &constants->Constants[i],
378 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
379 OUT_CS_32F(data[0]);
380 OUT_CS_32F(data[1]);
381 OUT_CS_32F(data[2]);
382 OUT_CS_32F(data[3]);
383 }
384 END_CS;
385 }
386
387 void r300_emit_fb_state(struct r300_context* r300,
388 struct pipe_framebuffer_state* fb)
389 {
390 struct r300_texture* tex;
391 struct pipe_surface* surf;
392 int i;
393 CS_LOCALS(r300);
394
395 /* Shouldn't fail unless there is a bug in the state tracker. */
396 assert(fb->nr_cbufs <= 4);
397
398 BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
399 (fb->zsbuf ? 10 : 0) + 6);
400
401 /* Flush and free renderbuffer caches. */
402 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
403 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
404 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
405 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
406 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
407 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
408
409 /* Set the number of colorbuffers. */
410 OUT_CS_REG(R300_RB3D_CCTL, R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
411
412 /* Set up colorbuffers. */
413 for (i = 0; i < fb->nr_cbufs; i++) {
414 surf = fb->cbufs[i];
415 tex = (struct r300_texture*)surf->texture;
416 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
417
418 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
419 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
420
421 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
422 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
423 r300_translate_colorformat(tex->tex.format) |
424 R300_COLOR_TILE(tex->macrotile) |
425 R300_COLOR_MICROTILE(tex->microtile),
426 0, RADEON_GEM_DOMAIN_VRAM, 0);
427
428 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
429 r300_translate_out_fmt(surf->format));
430 }
431
432 /* Disable unused colorbuffers. */
433 for (; i < 4; i++) {
434 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
435 }
436
437 /* Set up a zbuffer. */
438 if (fb->zsbuf) {
439 surf = fb->zsbuf;
440 tex = (struct r300_texture*)surf->texture;
441 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
442
443 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
444 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
445
446 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
447
448 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
449 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
450 R300_DEPTHMACROTILE(tex->macrotile) |
451 R300_DEPTHMICROTILE(tex->microtile),
452 0, RADEON_GEM_DOMAIN_VRAM, 0);
453 }
454
455 END_CS;
456 }
457
458 static void r300_emit_query_start(struct r300_context *r300)
459 {
460 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
461 struct r300_query *query = r300->query_current;
462 CS_LOCALS(r300);
463
464 if (!query)
465 return;
466
467 BEGIN_CS(4);
468 if (caps->family == CHIP_FAMILY_RV530) {
469 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
470 } else {
471 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
472 }
473 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
474 END_CS;
475 query->begin_emitted = TRUE;
476 }
477
478
479 static void r300_emit_query_finish(struct r300_context *r300,
480 struct r300_query *query)
481 {
482 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
483 CS_LOCALS(r300);
484
485 assert(caps->num_frag_pipes);
486
487 BEGIN_CS(6 * caps->num_frag_pipes + 2);
488 /* I'm not so sure I like this switch, but it's hard to be elegant
489 * when there's so many special cases...
490 *
491 * So here's the basic idea. For each pipe, enable writes to it only,
492 * then put out the relocation for ZPASS_ADDR, taking into account a
493 * 4-byte offset for each pipe. RV380 and older are special; they have
494 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
495 * so there's a chipset cap for that. */
496 switch (caps->num_frag_pipes) {
497 case 4:
498 /* pipe 3 only */
499 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
500 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
501 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
502 0, RADEON_GEM_DOMAIN_GTT, 0);
503 case 3:
504 /* pipe 2 only */
505 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
506 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
507 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
508 0, RADEON_GEM_DOMAIN_GTT, 0);
509 case 2:
510 /* pipe 1 only */
511 /* As mentioned above, accomodate RV380 and older. */
512 OUT_CS_REG(R300_SU_REG_DEST,
513 1 << (caps->high_second_pipe ? 3 : 1));
514 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
515 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
516 0, RADEON_GEM_DOMAIN_GTT, 0);
517 case 1:
518 /* pipe 0 only */
519 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
520 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
521 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
522 0, RADEON_GEM_DOMAIN_GTT, 0);
523 break;
524 default:
525 debug_printf("r300: Implementation error: Chipset reports %d"
526 " pixel pipes!\n", caps->num_frag_pipes);
527 assert(0);
528 }
529
530 /* And, finally, reset it to normal... */
531 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
532 END_CS;
533 }
534
535 static void rv530_emit_query_single(struct r300_context *r300,
536 struct r300_query *query)
537 {
538 CS_LOCALS(r300);
539
540 BEGIN_CS(8);
541 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
542 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
543 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
544 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
545 END_CS;
546 }
547
548 static void rv530_emit_query_double(struct r300_context *r300,
549 struct r300_query *query)
550 {
551 CS_LOCALS(r300);
552
553 BEGIN_CS(14);
554 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
555 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
556 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
557 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
558 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
559 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
560 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
561 END_CS;
562 }
563
564 void r300_emit_query_end(struct r300_context* r300)
565 {
566 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
567 struct r300_query *query = r300->query_current;
568
569 if (!query)
570 return;
571
572 if (query->begin_emitted == FALSE)
573 return;
574
575 if (caps->family == CHIP_FAMILY_RV530) {
576 if (caps->num_z_pipes == 2)
577 rv530_emit_query_double(r300, query);
578 else
579 rv530_emit_query_single(r300, query);
580 } else
581 r300_emit_query_finish(r300, query);
582 }
583
584 void r300_emit_rs_state(struct r300_context* r300, void* state)
585 {
586 struct r300_rs_state* rs = (struct r300_rs_state*)state;
587 float scale, offset;
588 CS_LOCALS(r300);
589
590 BEGIN_CS(18 + (rs->polygon_offset_enable ? 5 : 0));
591 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
592 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
593 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
594 OUT_CS(rs->point_minmax);
595 OUT_CS(rs->line_control);
596
597 if (rs->polygon_offset_enable) {
598 scale = rs->depth_scale * 12;
599 offset = rs->depth_offset;
600
601 switch (r300->zbuffer_bpp) {
602 case 16:
603 offset *= 4;
604 break;
605 case 24:
606 offset *= 2;
607 break;
608 }
609
610 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
611 OUT_CS_32F(scale);
612 OUT_CS_32F(offset);
613 OUT_CS_32F(scale);
614 OUT_CS_32F(offset);
615 }
616
617 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
618 OUT_CS(rs->polygon_offset_enable);
619 OUT_CS(rs->cull_mode);
620 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
621 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
622 OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
623 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
624 END_CS;
625 }
626
627 void r300_emit_rs_block_state(struct r300_context* r300,
628 struct r300_rs_block* rs)
629 {
630 int i;
631 struct r300_screen* r300screen = r300_screen(r300->context.screen);
632 CS_LOCALS(r300);
633
634 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
635
636 BEGIN_CS(21);
637 if (r300screen->caps->is_r500) {
638 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
639 } else {
640 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
641 }
642 for (i = 0; i < 8; i++) {
643 OUT_CS(rs->ip[i]);
644 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
645 }
646
647 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
648 OUT_CS(rs->count);
649 OUT_CS(rs->inst_count);
650
651 if (r300screen->caps->is_r500) {
652 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
653 } else {
654 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
655 }
656 for (i = 0; i < 8; i++) {
657 OUT_CS(rs->inst[i]);
658 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
659 }
660
661 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
662 rs->count, rs->inst_count);
663
664 END_CS;
665 }
666
667 void r300_emit_scissor_state(struct r300_context* r300, void* state)
668 {
669 unsigned minx, miny, maxx, maxy;
670 uint32_t top_left, bottom_right;
671 struct r300_screen* r300screen = r300_screen(r300->context.screen);
672 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
673 CS_LOCALS(r300);
674
675 minx = miny = 0;
676 maxx = r300->framebuffer_state.width;
677 maxy = r300->framebuffer_state.height;
678
679 if (((struct r300_rs_state*)r300->rs_state.state)->rs.scissor) {
680 minx = MAX2(minx, scissor->minx);
681 miny = MAX2(miny, scissor->miny);
682 maxx = MIN2(maxx, scissor->maxx);
683 maxy = MIN2(maxy, scissor->maxy);
684 }
685
686 if (r300screen->caps->is_r500) {
687 top_left =
688 (minx << R300_SCISSORS_X_SHIFT) |
689 (miny << R300_SCISSORS_Y_SHIFT);
690 bottom_right =
691 ((maxx - 1) << R300_SCISSORS_X_SHIFT) |
692 ((maxy - 1) << R300_SCISSORS_Y_SHIFT);
693 } else {
694 /* Offset of 1440 in non-R500 chipsets. */
695 top_left =
696 ((minx + 1440) << R300_SCISSORS_X_SHIFT) |
697 ((miny + 1440) << R300_SCISSORS_Y_SHIFT);
698 bottom_right =
699 (((maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
700 (((maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
701 }
702
703 BEGIN_CS(3);
704 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
705 OUT_CS(top_left);
706 OUT_CS(bottom_right);
707 END_CS;
708 }
709
710 void r300_emit_texture(struct r300_context* r300,
711 struct r300_sampler_state* sampler,
712 struct r300_texture* tex,
713 unsigned offset)
714 {
715 uint32_t filter0 = sampler->filter0;
716 uint32_t format0 = tex->state.format0;
717 unsigned min_level, max_level;
718 CS_LOCALS(r300);
719
720 /* to emulate 1D textures through 2D ones correctly */
721 if (tex->tex.target == PIPE_TEXTURE_1D) {
722 filter0 &= ~R300_TX_WRAP_T_MASK;
723 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
724 }
725
726 if (tex->is_npot) {
727 /* NPOT textures don't support mip filter, unfortunately.
728 * This prevents incorrect rendering. */
729 filter0 &= ~R300_TX_MIN_FILTER_MIP_MASK;
730 } else {
731 /* determine min/max levels */
732 /* the MAX_MIP level is the largest (finest) one */
733 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
734 min_level = MIN2(sampler->min_lod, max_level);
735 format0 |= R300_TX_NUM_LEVELS(max_level);
736 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
737 }
738
739 BEGIN_CS(16);
740 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
741 (offset << 28));
742 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
743 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
744
745 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
746 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
747 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
748 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
749 OUT_CS_RELOC(tex->buffer,
750 R300_TXO_MACRO_TILE(tex->macrotile) |
751 R300_TXO_MICRO_TILE(tex->microtile),
752 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
753 END_CS;
754 }
755
756 static boolean r300_validate_aos(struct r300_context *r300)
757 {
758 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
759 struct pipe_vertex_element *velem = r300->vertex_element;
760 int i;
761
762 /* Check if formats and strides are aligned to the size of DWORD. */
763 for (i = 0; i < r300->vertex_element_count; i++) {
764 if (vbuf[velem[i].vertex_buffer_index].stride % 4 != 0 ||
765 util_format_get_blocksize(velem[i].src_format) % 4 != 0) {
766 return FALSE;
767 }
768 }
769 return TRUE;
770 }
771
772 void r300_emit_aos(struct r300_context* r300, unsigned offset)
773 {
774 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
775 struct pipe_vertex_element *velem = r300->vertex_element;
776 int i;
777 unsigned size1, size2, aos_count = r300->vertex_element_count;
778 unsigned packet_size = (aos_count * 3 + 1) / 2;
779 CS_LOCALS(r300);
780
781 /* XXX Move this checking to a more approriate place. */
782 if (!r300_validate_aos(r300)) {
783 /* XXX We should fallback using Draw. */
784 assert(0);
785 }
786
787 BEGIN_CS(2 + packet_size + aos_count * 2);
788 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
789 OUT_CS(aos_count);
790
791 for (i = 0; i < aos_count - 1; i += 2) {
792 vb1 = &vbuf[velem[i].vertex_buffer_index];
793 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
794 size1 = util_format_get_blocksize(velem[i].src_format);
795 size2 = util_format_get_blocksize(velem[i+1].src_format);
796
797 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
798 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
799 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
800 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
801 }
802
803 if (aos_count & 1) {
804 vb1 = &vbuf[velem[i].vertex_buffer_index];
805 size1 = util_format_get_blocksize(velem[i].src_format);
806
807 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
808 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
809 }
810
811 for (i = 0; i < aos_count; i++) {
812 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
813 RADEON_GEM_DOMAIN_GTT, 0, 0);
814 }
815 END_CS;
816 }
817
818 void r300_emit_vertex_format_state(struct r300_context* r300)
819 {
820 int i;
821 CS_LOCALS(r300);
822
823 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
824
825 BEGIN_CS(26);
826 OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info->vinfo.size);
827
828 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
829 OUT_CS(r300->vertex_info->vinfo.hwfmt[0]);
830 OUT_CS(r300->vertex_info->vinfo.hwfmt[1]);
831 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
832 OUT_CS(r300->vertex_info->vinfo.hwfmt[2]);
833 OUT_CS(r300->vertex_info->vinfo.hwfmt[3]);
834 for (i = 0; i < 4; i++) {
835 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
836 r300->vertex_info->vinfo.hwfmt[i]);
837 }
838
839 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
840 for (i = 0; i < 8; i++) {
841 OUT_CS(r300->vertex_info->vap_prog_stream_cntl[i]);
842 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
843 r300->vertex_info->vap_prog_stream_cntl[i]);
844 }
845 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
846 for (i = 0; i < 8; i++) {
847 OUT_CS(r300->vertex_info->vap_prog_stream_cntl_ext[i]);
848 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
849 r300->vertex_info->vap_prog_stream_cntl_ext[i]);
850 }
851 END_CS;
852 }
853
854
855 void r300_emit_vertex_program_code(struct r300_context* r300,
856 struct r300_vertex_program_code* code)
857 {
858 int i;
859 struct r300_screen* r300screen = r300_screen(r300->context.screen);
860 unsigned instruction_count = code->length / 4;
861
862 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
863 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
864 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
865 int temp_count = MAX2(code->num_temporaries, 1);
866 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
867 vtx_mem_size / output_count, 10);
868 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
869
870 CS_LOCALS(r300);
871
872 if (!r300screen->caps->has_tcl) {
873 debug_printf("r300: Implementation error: emit_vertex_shader called,"
874 " but has_tcl is FALSE!\n");
875 return;
876 }
877
878 BEGIN_CS(9 + code->length);
879 /* R300_VAP_PVS_CODE_CNTL_0
880 * R300_VAP_PVS_CONST_CNTL
881 * R300_VAP_PVS_CODE_CNTL_1
882 * See the r5xx docs for instructions on how to use these. */
883 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
884 OUT_CS(R300_PVS_FIRST_INST(0) |
885 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
886 R300_PVS_LAST_INST(instruction_count - 1));
887 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
888 OUT_CS(instruction_count - 1);
889
890 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
891 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
892 for (i = 0; i < code->length; i++)
893 OUT_CS(code->body.d[i]);
894
895 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
896 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
897 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
898 R300_PVS_VF_MAX_VTX_NUM(12) |
899 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
900 END_CS;
901 }
902
903 void r300_emit_vertex_shader(struct r300_context* r300,
904 struct r300_vertex_shader* vs)
905 {
906 r300_emit_vertex_program_code(r300, &vs->code);
907 }
908
909 void r300_emit_vs_constant_buffer(struct r300_context* r300,
910 struct rc_constant_list* constants)
911 {
912 int i;
913 struct r300_screen* r300screen = r300_screen(r300->context.screen);
914 CS_LOCALS(r300);
915
916 if (!r300screen->caps->has_tcl) {
917 debug_printf("r300: Implementation error: emit_vertex_shader called,"
918 " but has_tcl is FALSE!\n");
919 return;
920 }
921
922 if (constants->Count == 0)
923 return;
924
925 BEGIN_CS(constants->Count * 4 + 3);
926 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
927 (r300screen->caps->is_r500 ?
928 R500_PVS_CONST_START : R300_PVS_CONST_START));
929 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
930 for (i = 0; i < constants->Count; i++) {
931 const float * data = get_shader_constant(r300,
932 &constants->Constants[i],
933 &r300->shader_constants[PIPE_SHADER_VERTEX]);
934 OUT_CS_32F(data[0]);
935 OUT_CS_32F(data[1]);
936 OUT_CS_32F(data[2]);
937 OUT_CS_32F(data[3]);
938 }
939 END_CS;
940 }
941
942 void r300_emit_viewport_state(struct r300_context* r300, void* state)
943 {
944 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
945 CS_LOCALS(r300);
946
947 if (r300->tcl_bypass) {
948 BEGIN_CS(2);
949 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
950 END_CS;
951 } else {
952 BEGIN_CS(9);
953 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
954 OUT_CS_32F(viewport->xscale);
955 OUT_CS_32F(viewport->xoffset);
956 OUT_CS_32F(viewport->yscale);
957 OUT_CS_32F(viewport->yoffset);
958 OUT_CS_32F(viewport->zscale);
959 OUT_CS_32F(viewport->zoffset);
960 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
961 END_CS;
962 }
963 }
964
965 void r300_emit_texture_count(struct r300_context* r300)
966 {
967 uint32_t tx_enable = 0;
968 int i;
969 CS_LOCALS(r300);
970
971 /* Notice that texture_count and sampler_count are just sizes
972 * of the respective arrays. We still have to check for the individual
973 * elements. */
974 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
975 if (r300->textures[i]) {
976 tx_enable |= 1 << i;
977 }
978 }
979
980 BEGIN_CS(2);
981 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
982 END_CS;
983
984 }
985
986 void r300_emit_ztop_state(struct r300_context* r300, void* state)
987 {
988 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
989 CS_LOCALS(r300);
990
991 BEGIN_CS(2);
992 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
993 END_CS;
994 }
995
996 void r300_flush_textures(struct r300_context* r300)
997 {
998 CS_LOCALS(r300);
999
1000 BEGIN_CS(2);
1001 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1002 END_CS;
1003 }
1004
1005 static void r300_flush_pvs(struct r300_context* r300)
1006 {
1007 CS_LOCALS(r300);
1008
1009 BEGIN_CS(2);
1010 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
1011 END_CS;
1012 }
1013
1014 /* Emit all dirty state. */
1015 void r300_emit_dirty_state(struct r300_context* r300)
1016 {
1017 struct r300_screen* r300screen = r300_screen(r300->context.screen);
1018 struct r300_texture* tex;
1019 struct r300_atom* atom;
1020 unsigned i, dwords = 1024;
1021 int dirty_tex = 0;
1022 boolean invalid = FALSE;
1023
1024 /* Check the required number of dwords against the space remaining in the
1025 * current CS object. If we need more, then flush. */
1026
1027 foreach(atom, &r300->atom_list) {
1028 if (atom->dirty || atom->always_dirty) {
1029 dwords += atom->size;
1030 }
1031 }
1032
1033 /* Make sure we have at least 2*1024 spare dwords. */
1034 /* XXX It would be nice to know the number of dwords we really need to
1035 * XXX emit. */
1036 if (!r300->winsys->check_cs(r300->winsys, dwords)) {
1037 r300->context.flush(&r300->context, 0, NULL);
1038 }
1039
1040 /* Clean out BOs. */
1041 r300->winsys->reset_bos(r300->winsys);
1042
1043 validate:
1044 /* Color buffers... */
1045 for (i = 0; i < r300->framebuffer_state.nr_cbufs; i++) {
1046 tex = (struct r300_texture*)r300->framebuffer_state.cbufs[i]->texture;
1047 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1048 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1049 0, RADEON_GEM_DOMAIN_VRAM)) {
1050 r300->context.flush(&r300->context, 0, NULL);
1051 goto validate;
1052 }
1053 }
1054 /* ...depth buffer... */
1055 if (r300->framebuffer_state.zsbuf) {
1056 tex = (struct r300_texture*)r300->framebuffer_state.zsbuf->texture;
1057 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1058 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1059 0, RADEON_GEM_DOMAIN_VRAM)) {
1060 r300->context.flush(&r300->context, 0, NULL);
1061 goto validate;
1062 }
1063 }
1064 /* ...textures... */
1065 for (i = 0; i < r300->texture_count; i++) {
1066 tex = r300->textures[i];
1067 if (!tex)
1068 continue;
1069 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1070 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1071 r300->context.flush(&r300->context, 0, NULL);
1072 goto validate;
1073 }
1074 }
1075 /* ...occlusion query buffer... */
1076 if (r300->dirty_state & R300_NEW_QUERY) {
1077 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1078 0, RADEON_GEM_DOMAIN_GTT)) {
1079 r300->context.flush(&r300->context, 0, NULL);
1080 goto validate;
1081 }
1082 }
1083 /* ...and vertex buffer. */
1084 if (r300->vbo) {
1085 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1086 RADEON_GEM_DOMAIN_GTT, 0)) {
1087 r300->context.flush(&r300->context, 0, NULL);
1088 goto validate;
1089 }
1090 } else {
1091 /* debug_printf("No VBO while emitting dirty state!\n"); */
1092 }
1093 if (!r300->winsys->validate(r300->winsys)) {
1094 r300->context.flush(&r300->context, 0, NULL);
1095 if (invalid) {
1096 /* Well, hell. */
1097 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1098 exit(1);
1099 }
1100 invalid = TRUE;
1101 goto validate;
1102 }
1103
1104 if (r300->dirty_state & R300_NEW_QUERY) {
1105 r300_emit_query_start(r300);
1106 r300->dirty_state &= ~R300_NEW_QUERY;
1107 }
1108
1109 foreach(atom, &r300->atom_list) {
1110 if (atom->dirty || atom->always_dirty) {
1111 atom->emit(r300, atom->state);
1112 atom->dirty = FALSE;
1113 }
1114 }
1115
1116 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1117 r300_emit_fragment_depth_config(r300, r300->fs);
1118 if (r300screen->caps->is_r500) {
1119 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1120 } else {
1121 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1122 }
1123 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1124 }
1125
1126 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1127 if (r300screen->caps->is_r500) {
1128 r500_emit_fs_constant_buffer(r300,
1129 &r300->fs->shader->code.constants);
1130 } else {
1131 r300_emit_fs_constant_buffer(r300,
1132 &r300->fs->shader->code.constants);
1133 }
1134 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1135 }
1136
1137 if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
1138 r300_emit_fb_state(r300, &r300->framebuffer_state);
1139 r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
1140 }
1141
1142 if (r300->dirty_state & R300_NEW_RS_BLOCK) {
1143 r300_emit_rs_block_state(r300, r300->rs_block);
1144 r300->dirty_state &= ~R300_NEW_RS_BLOCK;
1145 }
1146
1147 /* Samplers and textures are tracked separately but emitted together. */
1148 if (r300->dirty_state &
1149 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1150 r300_emit_texture_count(r300);
1151
1152 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1153 if (r300->dirty_state &
1154 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1155 if (r300->textures[i])
1156 r300_emit_texture(r300,
1157 r300->sampler_states[i],
1158 r300->textures[i],
1159 i);
1160 r300->dirty_state &=
1161 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1162 dirty_tex++;
1163 }
1164 }
1165 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1166 }
1167
1168 if (dirty_tex) {
1169 r300_flush_textures(r300);
1170 }
1171
1172 if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
1173 r300_emit_vertex_format_state(r300);
1174 r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
1175 }
1176
1177 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1178 r300_flush_pvs(r300);
1179 }
1180
1181 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1182 r300_emit_vertex_shader(r300, r300->vs);
1183 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1184 }
1185
1186 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1187 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1188 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1189 }
1190
1191 /* XXX
1192 assert(r300->dirty_state == 0);
1193 */
1194
1195 /* Finally, emit the VBO. */
1196 /* r300_emit_vertex_buffer(r300); */
1197
1198 r300->dirty_hw++;
1199 }