r300g: implement instanced arrays
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29
30 #include "r300_context.h"
31 #include "r300_cb.h"
32 #include "r300_cs.h"
33 #include "r300_emit.h"
34 #include "r300_fs.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
37 #include "r300_vs.h"
38
39 void r300_emit_blend_state(struct r300_context* r300,
40 unsigned size, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 struct pipe_framebuffer_state* fb =
44 (struct pipe_framebuffer_state*)r300->fb_state.state;
45 CS_LOCALS(r300);
46
47 if (fb->nr_cbufs) {
48 WRITE_CS_TABLE(blend->cb, size);
49 } else {
50 WRITE_CS_TABLE(blend->cb_no_readwrite, size);
51 }
52 }
53
54 void r300_emit_blend_color_state(struct r300_context* r300,
55 unsigned size, void* state)
56 {
57 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
58 CS_LOCALS(r300);
59
60 WRITE_CS_TABLE(bc->cb, size);
61 }
62
63 void r300_emit_clip_state(struct r300_context* r300,
64 unsigned size, void* state)
65 {
66 struct r300_clip_state* clip = (struct r300_clip_state*)state;
67 CS_LOCALS(r300);
68
69 WRITE_CS_TABLE(clip->cb, size);
70 }
71
72 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
73 {
74 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
75 struct pipe_framebuffer_state* fb =
76 (struct pipe_framebuffer_state*)r300->fb_state.state;
77 CS_LOCALS(r300);
78
79 if (fb->zsbuf) {
80 if (fb->nr_cbufs && fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT)
81 WRITE_CS_TABLE(&dsa->cb_begin_fp16, size);
82 else
83 WRITE_CS_TABLE(&dsa->cb_begin, size);
84 } else {
85 if (fb->nr_cbufs && fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT)
86 WRITE_CS_TABLE(dsa->cb_fp16_zb_no_readwrite, size);
87 else
88 WRITE_CS_TABLE(dsa->cb_zb_no_readwrite, size);
89 }
90 }
91
92 static void get_rc_constant_state(
93 float vec[4],
94 struct r300_context * r300,
95 struct rc_constant * constant)
96 {
97 struct r300_textures_state* texstate = r300->textures_state.state;
98 struct r300_resource *tex;
99
100 assert(constant->Type == RC_CONSTANT_STATE);
101
102 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
103 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
104 * state factors. */
105
106 switch (constant->u.State[0]) {
107 /* Factor for converting rectangle coords to
108 * normalized coords. Should only show up on non-r500. */
109 case RC_STATE_R300_TEXRECT_FACTOR:
110 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
111 vec[0] = 1.0 / tex->tex.width0;
112 vec[1] = 1.0 / tex->tex.height0;
113 vec[2] = 0;
114 vec[3] = 1;
115 break;
116
117 case RC_STATE_R300_TEXSCALE_FACTOR:
118 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
119 /* Add a small number to the texture size to work around rounding errors in hw. */
120 vec[0] = tex->b.b.b.width0 / (tex->tex.width0 + 0.001f);
121 vec[1] = tex->b.b.b.height0 / (tex->tex.height0 + 0.001f);
122 vec[2] = tex->b.b.b.depth0 / (tex->tex.depth0 + 0.001f);
123 vec[3] = 1;
124 break;
125
126 case RC_STATE_R300_VIEWPORT_SCALE:
127 vec[0] = r300->viewport.scale[0];
128 vec[1] = r300->viewport.scale[1];
129 vec[2] = r300->viewport.scale[2];
130 vec[3] = 1;
131 break;
132
133 case RC_STATE_R300_VIEWPORT_OFFSET:
134 vec[0] = r300->viewport.translate[0];
135 vec[1] = r300->viewport.translate[1];
136 vec[2] = r300->viewport.translate[2];
137 vec[3] = 1;
138 break;
139
140 default:
141 fprintf(stderr, "r300: Implementation error: "
142 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
143 vec[0] = 0;
144 vec[1] = 0;
145 vec[2] = 0;
146 vec[3] = 1;
147 }
148 }
149
150 /* Convert a normal single-precision float into the 7.16 format
151 * used by the R300 fragment shader.
152 */
153 uint32_t pack_float24(float f)
154 {
155 union {
156 float fl;
157 uint32_t u;
158 } u;
159 float mantissa;
160 int exponent;
161 uint32_t float24 = 0;
162
163 if (f == 0.0)
164 return 0;
165
166 u.fl = f;
167
168 mantissa = frexpf(f, &exponent);
169
170 /* Handle -ve */
171 if (mantissa < 0) {
172 float24 |= (1 << 23);
173 mantissa = mantissa * -1.0;
174 }
175 /* Handle exponent, bias of 63 */
176 exponent += 62;
177 float24 |= (exponent << 16);
178 /* Kill 7 LSB of mantissa */
179 float24 |= (u.u & 0x7FFFFF) >> 7;
180
181 return float24;
182 }
183
184 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
185 {
186 struct r300_fragment_shader *fs = r300_fs(r300);
187 CS_LOCALS(r300);
188
189 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
190 }
191
192 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
193 {
194 struct r300_fragment_shader *fs = r300_fs(r300);
195 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
196 unsigned count = fs->shader->externals_count;
197 unsigned i, j;
198 CS_LOCALS(r300);
199
200 if (count == 0)
201 return;
202
203 BEGIN_CS(size);
204 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
205 if (buf->remap_table){
206 for (i = 0; i < count; i++) {
207 float *data = (float*)&buf->ptr[buf->remap_table[i]*4];
208 for (j = 0; j < 4; j++)
209 OUT_CS(pack_float24(data[j]));
210 }
211 } else {
212 for (i = 0; i < count; i++)
213 for (j = 0; j < 4; j++)
214 OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j]));
215 }
216
217 END_CS;
218 }
219
220 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
221 {
222 struct r300_fragment_shader *fs = r300_fs(r300);
223 struct rc_constant_list *constants = &fs->shader->code.constants;
224 unsigned i;
225 unsigned count = fs->shader->rc_state_count;
226 unsigned first = fs->shader->externals_count;
227 unsigned end = constants->Count;
228 unsigned j;
229 CS_LOCALS(r300);
230
231 if (count == 0)
232 return;
233
234 BEGIN_CS(size);
235 for(i = first; i < end; ++i) {
236 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
237 float data[4];
238
239 get_rc_constant_state(data, r300, &constants->Constants[i]);
240
241 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
242 for (j = 0; j < 4; j++)
243 OUT_CS(pack_float24(data[j]));
244 }
245 }
246 END_CS;
247 }
248
249 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
250 {
251 struct r300_fragment_shader *fs = r300_fs(r300);
252 CS_LOCALS(r300);
253
254 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
255 }
256
257 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
258 {
259 struct r300_fragment_shader *fs = r300_fs(r300);
260 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
261 unsigned count = fs->shader->externals_count;
262 CS_LOCALS(r300);
263
264 if (count == 0)
265 return;
266
267 BEGIN_CS(size);
268 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
269 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
270 if (buf->remap_table){
271 for (unsigned i = 0; i < count; i++) {
272 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
273 OUT_CS_TABLE(data, 4);
274 }
275 } else {
276 OUT_CS_TABLE(buf->ptr, count * 4);
277 }
278 END_CS;
279 }
280
281 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
282 {
283 struct r300_fragment_shader *fs = r300_fs(r300);
284 struct rc_constant_list *constants = &fs->shader->code.constants;
285 unsigned i;
286 unsigned count = fs->shader->rc_state_count;
287 unsigned first = fs->shader->externals_count;
288 unsigned end = constants->Count;
289 CS_LOCALS(r300);
290
291 if (count == 0)
292 return;
293
294 BEGIN_CS(size);
295 for(i = first; i < end; ++i) {
296 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
297 float data[4];
298
299 get_rc_constant_state(data, r300, &constants->Constants[i]);
300
301 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
302 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
303 (i & R500_GA_US_VECTOR_INDEX_MASK));
304 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
305 OUT_CS_TABLE(data, 4);
306 }
307 }
308 END_CS;
309 }
310
311 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
312 {
313 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
314 struct pipe_framebuffer_state* fb =
315 (struct pipe_framebuffer_state*)r300->fb_state.state;
316 uint32_t height = fb->height;
317 uint32_t width = fb->width;
318 CS_LOCALS(r300);
319
320 if (r300->cbzb_clear) {
321 struct r300_surface *surf = r300_surface(fb->cbufs[0]);
322
323 height = surf->cbzb_height;
324 width = surf->cbzb_width;
325 }
326
327 DBG(r300, DBG_SCISSOR,
328 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
329 width, height, r300->cbzb_clear ? "YES" : "NO");
330
331 BEGIN_CS(size);
332
333 /* Set up scissors.
334 * By writing to the SC registers, SC & US assert idle. */
335 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
336 if (r300->screen->caps.is_r500) {
337 OUT_CS(0);
338 OUT_CS(((width - 1) << R300_SCISSORS_X_SHIFT) |
339 ((height - 1) << R300_SCISSORS_Y_SHIFT));
340 } else {
341 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
342 (1440 << R300_SCISSORS_Y_SHIFT));
343 OUT_CS(((width + 1440-1) << R300_SCISSORS_X_SHIFT) |
344 ((height + 1440-1) << R300_SCISSORS_Y_SHIFT));
345 }
346
347 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
348 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
349 END_CS;
350 }
351
352 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
353 {
354 struct r300_aa_state *aa = (struct r300_aa_state*)state;
355 CS_LOCALS(r300);
356
357 BEGIN_CS(size);
358 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
359
360 if (aa->dest) {
361 OUT_CS_REG(R300_RB3D_AARESOLVE_OFFSET, aa->dest->offset);
362 OUT_CS_RELOC(aa->dest);
363 OUT_CS_REG(R300_RB3D_AARESOLVE_PITCH, aa->dest->pitch);
364 }
365
366 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, aa->aaresolve_ctl);
367 END_CS;
368 }
369
370 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
371 {
372 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
373 struct r300_surface* surf;
374 unsigned i;
375 boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
376 uint32_t rb3d_cctl = 0;
377
378 CS_LOCALS(r300);
379
380 BEGIN_CS(size);
381
382 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
383 * what we usually want. */
384 if (r300->screen->caps.is_r500) {
385 rb3d_cctl = R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE;
386 }
387 if (fb->nr_cbufs &&
388 r300_fragment_shader_writes_all(r300_fs(r300))) {
389 rb3d_cctl |= R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs);
390 }
391
392 OUT_CS_REG(R300_RB3D_CCTL, rb3d_cctl);
393
394 /* Set up colorbuffers. */
395 for (i = 0; i < fb->nr_cbufs; i++) {
396 surf = r300_surface(fb->cbufs[i]);
397
398 OUT_CS_REG(R300_RB3D_COLOROFFSET0 + (4 * i), surf->offset);
399 OUT_CS_RELOC(surf);
400
401 OUT_CS_REG(R300_RB3D_COLORPITCH0 + (4 * i), surf->pitch);
402 OUT_CS_RELOC(surf);
403 }
404
405 /* Set up the ZB part of the CBZB clear. */
406 if (r300->cbzb_clear) {
407 surf = r300_surface(fb->cbufs[0]);
408
409 OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format);
410
411 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->cbzb_midpoint_offset);
412 OUT_CS_RELOC(surf);
413
414 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->cbzb_pitch);
415 OUT_CS_RELOC(surf);
416
417 DBG(r300, DBG_CBZB,
418 "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format,
419 surf->cbzb_pitch);
420 }
421 /* Set up a zbuffer. */
422 else if (fb->zsbuf) {
423 surf = r300_surface(fb->zsbuf);
424
425 OUT_CS_REG(R300_ZB_FORMAT, surf->format);
426
427 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->offset);
428 OUT_CS_RELOC(surf);
429
430 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->pitch);
431 OUT_CS_RELOC(surf);
432
433 if (can_hyperz) {
434 /* HiZ RAM. */
435 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
436 OUT_CS_REG(R300_ZB_HIZ_PITCH, surf->pitch_hiz);
437 /* Z Mask RAM. (compressed zbuffer) */
438 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
439 OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf->pitch_zmask);
440 }
441 }
442
443 END_CS;
444 }
445
446 void r300_emit_hyperz_state(struct r300_context *r300,
447 unsigned size, void *state)
448 {
449 struct r300_hyperz_state *z = state;
450 CS_LOCALS(r300);
451
452 if (z->flush)
453 WRITE_CS_TABLE(&z->cb_flush_begin, size);
454 else
455 WRITE_CS_TABLE(&z->cb_begin, size - 2);
456 }
457
458 void r300_emit_hyperz_end(struct r300_context *r300)
459 {
460 struct r300_hyperz_state z =
461 *(struct r300_hyperz_state*)r300->hyperz_state.state;
462
463 z.flush = 1;
464 z.zb_bw_cntl = 0;
465 z.zb_depthclearvalue = 0;
466 z.sc_hyperz = R300_SC_HYPERZ_ADJ_2;
467 z.gb_z_peq_config = 0;
468
469 r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z);
470 }
471
472 void r300_emit_fb_state_pipelined(struct r300_context *r300,
473 unsigned size, void *state)
474 {
475 struct pipe_framebuffer_state* fb =
476 (struct pipe_framebuffer_state*)r300->fb_state.state;
477 unsigned i, num_cbufs = fb->nr_cbufs;
478 unsigned mspos0, mspos1;
479 CS_LOCALS(r300);
480
481 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be
482 * marked as UNUSED in the US block. */
483 if (r300_fragment_shader_writes_all(r300_fs(r300))) {
484 num_cbufs = MIN2(num_cbufs, 1);
485 }
486
487 BEGIN_CS(size);
488
489 /* Colorbuffer format in the US block.
490 * (must be written after unpipelined regs) */
491 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
492 for (i = 0; i < num_cbufs; i++) {
493 OUT_CS(r300_surface(fb->cbufs[i])->format);
494 }
495 for (; i < 4; i++) {
496 OUT_CS(R300_US_OUT_FMT_UNUSED);
497 }
498
499 /* Multisampling. Depends on framebuffer sample count.
500 * These are pipelined regs and as such cannot be moved
501 * to the AA state. */
502 mspos0 = 0x66666666;
503 mspos1 = 0x6666666;
504
505 if (fb->nr_cbufs && fb->cbufs[0]->texture->nr_samples > 1) {
506 /* Subsample placement. These may not be optimal. */
507 switch (fb->cbufs[0]->texture->nr_samples) {
508 case 2:
509 mspos0 = 0x33996633;
510 mspos1 = 0x6666663;
511 break;
512 case 3:
513 mspos0 = 0x33936933;
514 mspos1 = 0x6666663;
515 break;
516 case 4:
517 mspos0 = 0x33939933;
518 mspos1 = 0x3966663;
519 break;
520 case 6:
521 mspos0 = 0x22a2aa22;
522 mspos1 = 0x2a65672;
523 break;
524 default:
525 debug_printf("r300: Bad number of multisamples!\n");
526 }
527 }
528
529 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
530 OUT_CS(mspos0);
531 OUT_CS(mspos1);
532 END_CS;
533 }
534
535 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
536 {
537 struct r300_query *query = r300->query_current;
538 CS_LOCALS(r300);
539
540 if (!query)
541 return;
542
543 BEGIN_CS(size);
544 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
545 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
546 } else {
547 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
548 }
549 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
550 END_CS;
551 query->begin_emitted = TRUE;
552 }
553
554 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
555 struct r300_query *query)
556 {
557 struct r300_capabilities* caps = &r300->screen->caps;
558 CS_LOCALS(r300);
559
560 assert(caps->num_frag_pipes);
561
562 BEGIN_CS(6 * caps->num_frag_pipes + 2);
563 /* I'm not so sure I like this switch, but it's hard to be elegant
564 * when there's so many special cases...
565 *
566 * So here's the basic idea. For each pipe, enable writes to it only,
567 * then put out the relocation for ZPASS_ADDR, taking into account a
568 * 4-byte offset for each pipe. RV380 and older are special; they have
569 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
570 * so there's a chipset cap for that. */
571 switch (caps->num_frag_pipes) {
572 case 4:
573 /* pipe 3 only */
574 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
575 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 3) * 4);
576 OUT_CS_RELOC(r300->query_current);
577 case 3:
578 /* pipe 2 only */
579 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
580 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 2) * 4);
581 OUT_CS_RELOC(r300->query_current);
582 case 2:
583 /* pipe 1 only */
584 /* As mentioned above, accomodate RV380 and older. */
585 OUT_CS_REG(R300_SU_REG_DEST,
586 1 << (caps->high_second_pipe ? 3 : 1));
587 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4);
588 OUT_CS_RELOC(r300->query_current);
589 case 1:
590 /* pipe 0 only */
591 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
592 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4);
593 OUT_CS_RELOC(r300->query_current);
594 break;
595 default:
596 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
597 " pixel pipes!\n", caps->num_frag_pipes);
598 abort();
599 }
600
601 /* And, finally, reset it to normal... */
602 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
603 END_CS;
604 }
605
606 static void rv530_emit_query_end_single_z(struct r300_context *r300,
607 struct r300_query *query)
608 {
609 CS_LOCALS(r300);
610
611 BEGIN_CS(8);
612 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
613 OUT_CS_REG(R300_ZB_ZPASS_ADDR, query->num_results * 4);
614 OUT_CS_RELOC(r300->query_current);
615 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
616 END_CS;
617 }
618
619 static void rv530_emit_query_end_double_z(struct r300_context *r300,
620 struct r300_query *query)
621 {
622 CS_LOCALS(r300);
623
624 BEGIN_CS(14);
625 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
626 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4);
627 OUT_CS_RELOC(r300->query_current);
628 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
629 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4);
630 OUT_CS_RELOC(r300->query_current);
631 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
632 END_CS;
633 }
634
635 void r300_emit_query_end(struct r300_context* r300)
636 {
637 struct r300_capabilities *caps = &r300->screen->caps;
638 struct r300_query *query = r300->query_current;
639
640 if (!query)
641 return;
642
643 if (query->begin_emitted == FALSE)
644 return;
645
646 if (caps->family == CHIP_FAMILY_RV530) {
647 if (caps->num_z_pipes == 2)
648 rv530_emit_query_end_double_z(r300, query);
649 else
650 rv530_emit_query_end_single_z(r300, query);
651 } else
652 r300_emit_query_end_frag_pipes(r300, query);
653
654 query->begin_emitted = FALSE;
655 query->num_results += query->num_pipes;
656
657 /* XXX grab all the results and reset the counter. */
658 if (query->num_results >= query->buffer_size / 4 - 4) {
659 query->num_results = (query->buffer_size / 4) / 2;
660 fprintf(stderr, "r300: Rewinding OQBO...\n");
661 }
662 }
663
664 void r300_emit_invariant_state(struct r300_context *r300,
665 unsigned size, void *state)
666 {
667 CS_LOCALS(r300);
668 WRITE_CS_TABLE(state, size);
669 }
670
671 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
672 {
673 struct r300_rs_state* rs = state;
674 CS_LOCALS(r300);
675
676 BEGIN_CS(size);
677 OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE);
678 if (rs->polygon_offset_enable) {
679 if (r300->zbuffer_bpp == 16) {
680 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5);
681 } else {
682 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5);
683 }
684 }
685 END_CS;
686 }
687
688 void r300_emit_rs_block_state(struct r300_context* r300,
689 unsigned size, void* state)
690 {
691 struct r300_rs_block* rs = (struct r300_rs_block*)state;
692 unsigned i;
693 /* It's the same for both INST and IP tables */
694 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
695 CS_LOCALS(r300);
696
697 if (DBG_ON(r300, DBG_RS_BLOCK)) {
698 r500_dump_rs_block(rs);
699
700 fprintf(stderr, "r300: RS emit:\n");
701
702 for (i = 0; i < count; i++)
703 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]);
704
705 for (i = 0; i < count; i++)
706 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]);
707
708 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n",
709 rs->count, rs->inst_count);
710 }
711
712 BEGIN_CS(size);
713 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
714 OUT_CS(rs->vap_vtx_state_cntl);
715 OUT_CS(rs->vap_vsm_vtx_assm);
716 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
717 OUT_CS(rs->vap_out_vtx_fmt[0]);
718 OUT_CS(rs->vap_out_vtx_fmt[1]);
719 OUT_CS_REG_SEQ(R300_GB_ENABLE, 1);
720 OUT_CS(rs->gb_enable);
721
722 if (r300->screen->caps.is_r500) {
723 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
724 } else {
725 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
726 }
727 OUT_CS_TABLE(rs->ip, count);
728
729 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
730 OUT_CS(rs->count);
731 OUT_CS(rs->inst_count);
732
733 if (r300->screen->caps.is_r500) {
734 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
735 } else {
736 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
737 }
738 OUT_CS_TABLE(rs->inst, count);
739 END_CS;
740 }
741
742 void r300_emit_scissor_state(struct r300_context* r300,
743 unsigned size, void* state)
744 {
745 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
746 CS_LOCALS(r300);
747
748 BEGIN_CS(size);
749 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
750 if (r300->screen->caps.is_r500) {
751 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
752 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
753 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
754 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
755 } else {
756 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
757 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
758 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
759 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
760 }
761 END_CS;
762 }
763
764 void r300_emit_textures_state(struct r300_context *r300,
765 unsigned size, void *state)
766 {
767 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
768 struct r300_texture_sampler_state *texstate;
769 struct r300_resource *tex;
770 unsigned i;
771 CS_LOCALS(r300);
772
773 BEGIN_CS(size);
774 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
775
776 for (i = 0; i < allstate->count; i++) {
777 if ((1 << i) & allstate->tx_enable) {
778 texstate = &allstate->regs[i];
779 tex = r300_resource(allstate->sampler_views[i]->base.texture);
780
781 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
782 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
783 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
784 texstate->border_color);
785
786 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
787 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
788 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
789
790 OUT_CS_REG(R300_TX_OFFSET_0 + (i * 4), texstate->format.tile_config);
791 OUT_CS_RELOC(tex);
792 }
793 }
794 END_CS;
795 }
796
797 void r300_emit_vertex_arrays(struct r300_context* r300, int offset,
798 boolean indexed, int instance_id)
799 {
800 struct pipe_vertex_buffer *vbuf = r300->vbuf_mgr->vertex_buffer;
801 struct pipe_resource **valid_vbuf = r300->vbuf_mgr->real_vertex_buffer;
802 struct pipe_vertex_element *velem = r300->velems->velem;
803 struct r300_resource *buf;
804 int i;
805 unsigned vertex_array_count = r300->velems->count;
806 unsigned packet_size = (vertex_array_count * 3 + 1) / 2;
807 struct pipe_vertex_buffer *vb1, *vb2;
808 unsigned *hw_format_size = r300->velems->format_size;
809 unsigned size1, size2, offset1, offset2, stride1, stride2;
810 CS_LOCALS(r300);
811
812 BEGIN_CS(2 + packet_size + vertex_array_count * 2);
813 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
814 OUT_CS(vertex_array_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
815
816 if (instance_id == -1) {
817 /* Non-instanced arrays. This ignores instance_divisor and instance_id. */
818 for (i = 0; i < vertex_array_count - 1; i += 2) {
819 vb1 = &vbuf[velem[i].vertex_buffer_index];
820 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
821 size1 = hw_format_size[i];
822 size2 = hw_format_size[i+1];
823
824 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
825 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
826 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
827 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
828 }
829
830 if (vertex_array_count & 1) {
831 vb1 = &vbuf[velem[i].vertex_buffer_index];
832 size1 = hw_format_size[i];
833
834 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
835 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
836 }
837
838 for (i = 0; i < vertex_array_count; i++) {
839 buf = r300_resource(valid_vbuf[velem[i].vertex_buffer_index]);
840 OUT_CS_RELOC(buf);
841 }
842 } else {
843 /* Instanced arrays. */
844 for (i = 0; i < vertex_array_count - 1; i += 2) {
845 vb1 = &vbuf[velem[i].vertex_buffer_index];
846 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
847 size1 = hw_format_size[i];
848 size2 = hw_format_size[i+1];
849
850 if (velem[i].instance_divisor) {
851 stride1 = 0;
852 offset1 = vb1->buffer_offset + velem[i].src_offset +
853 (instance_id / velem[i].instance_divisor) * vb1->stride;
854 } else {
855 stride1 = vb1->stride;
856 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride;
857 }
858 if (velem[i+1].instance_divisor) {
859 stride2 = 0;
860 offset2 = vb2->buffer_offset + velem[i+1].src_offset +
861 (instance_id / velem[i+1].instance_divisor) * vb2->stride;
862 } else {
863 stride2 = vb2->stride;
864 offset2 = vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride;
865 }
866
867 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1) |
868 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(stride2));
869 OUT_CS(offset1);
870 OUT_CS(offset2);
871 }
872
873 if (vertex_array_count & 1) {
874 vb1 = &vbuf[velem[i].vertex_buffer_index];
875 size1 = hw_format_size[i];
876
877 if (velem[i].instance_divisor) {
878 stride1 = 0;
879 offset1 = vb1->buffer_offset + velem[i].src_offset +
880 (instance_id / velem[i].instance_divisor) * vb1->stride;
881 } else {
882 stride1 = vb1->stride;
883 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride;
884 }
885
886 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1));
887 OUT_CS(offset1);
888 }
889
890 for (i = 0; i < vertex_array_count; i++) {
891 buf = r300_resource(valid_vbuf[velem[i].vertex_buffer_index]);
892 OUT_CS_RELOC(buf);
893 }
894 }
895 END_CS;
896 }
897
898 void r300_emit_vertex_arrays_swtcl(struct r300_context *r300, boolean indexed)
899 {
900 CS_LOCALS(r300);
901
902 DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, "
903 "vertex size %d\n", r300->vbo,
904 r300->vertex_info.size);
905 /* Set the pointer to our vertex buffer. The emitted values are this:
906 * PACKET3 [3D_LOAD_VBPNTR]
907 * COUNT [1]
908 * FORMAT [size | stride << 8]
909 * OFFSET [offset into BO]
910 * VBPNTR [relocated BO]
911 */
912 BEGIN_CS(7);
913 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
914 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
915 OUT_CS(r300->vertex_info.size |
916 (r300->vertex_info.size << 8));
917 OUT_CS(r300->draw_vbo_offset);
918 OUT_CS(0);
919 OUT_CS_RELOC(r300_resource(r300->vbo));
920 END_CS;
921 }
922
923 void r300_emit_vertex_stream_state(struct r300_context* r300,
924 unsigned size, void* state)
925 {
926 struct r300_vertex_stream_state *streams =
927 (struct r300_vertex_stream_state*)state;
928 unsigned i;
929 CS_LOCALS(r300);
930
931 if (DBG_ON(r300, DBG_PSC)) {
932 fprintf(stderr, "r300: PSC emit:\n");
933
934 for (i = 0; i < streams->count; i++) {
935 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i,
936 streams->vap_prog_stream_cntl[i]);
937 }
938
939 for (i = 0; i < streams->count; i++) {
940 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
941 streams->vap_prog_stream_cntl_ext[i]);
942 }
943 }
944
945 BEGIN_CS(size);
946 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
947 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
948 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
949 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
950 END_CS;
951 }
952
953 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
954 {
955 CS_LOCALS(r300);
956
957 BEGIN_CS(size);
958 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
959 END_CS;
960 }
961
962 void r300_emit_vap_invariant_state(struct r300_context *r300,
963 unsigned size, void *state)
964 {
965 CS_LOCALS(r300);
966 WRITE_CS_TABLE(state, size);
967 }
968
969 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
970 {
971 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
972 struct r300_vertex_program_code* code = &vs->code;
973 struct r300_screen* r300screen = r300->screen;
974 unsigned instruction_count = code->length / 4;
975
976 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
977 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
978 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
979 unsigned temp_count = MAX2(code->num_temporaries, 1);
980
981 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
982 vtx_mem_size / output_count, 10);
983 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5);
984
985 CS_LOCALS(r300);
986
987 BEGIN_CS(size);
988
989 /* R300_VAP_PVS_CODE_CNTL_0
990 * R300_VAP_PVS_CONST_CNTL
991 * R300_VAP_PVS_CODE_CNTL_1
992 * See the r5xx docs for instructions on how to use these. */
993 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) |
994 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
995 R300_PVS_LAST_INST(instruction_count - 1));
996 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, instruction_count - 1);
997
998 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
999 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
1000 OUT_CS_TABLE(code->body.d, code->length);
1001
1002 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
1003 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
1004 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
1005 R300_PVS_VF_MAX_VTX_NUM(12) |
1006 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
1007
1008 /* Emit flow control instructions. */
1009 if (code->num_fc_ops) {
1010
1011 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops);
1012 if (r300screen->caps.is_r500) {
1013 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, code->num_fc_ops * 2);
1014 OUT_CS_TABLE(code->fc_op_addrs.r500, code->num_fc_ops * 2);
1015 } else {
1016 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, code->num_fc_ops);
1017 OUT_CS_TABLE(code->fc_op_addrs.r300, code->num_fc_ops);
1018 }
1019 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, code->num_fc_ops);
1020 OUT_CS_TABLE(code->fc_loop_index, code->num_fc_ops);
1021 }
1022
1023 END_CS;
1024 }
1025
1026 void r300_emit_vs_constants(struct r300_context* r300,
1027 unsigned size, void *state)
1028 {
1029 unsigned count =
1030 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
1031 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
1032 struct r300_vertex_shader *vs = (struct r300_vertex_shader*)r300->vs_state.state;
1033 unsigned i;
1034 int imm_first = vs->externals_count;
1035 int imm_end = vs->code.constants.Count;
1036 int imm_count = vs->immediates_count;
1037 CS_LOCALS(r300);
1038
1039 BEGIN_CS(size);
1040 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL,
1041 R300_PVS_CONST_BASE_OFFSET(buf->buffer_base) |
1042 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end - 1, 0)));
1043 if (vs->externals_count) {
1044 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1045 (r300->screen->caps.is_r500 ?
1046 R500_PVS_CONST_START : R300_PVS_CONST_START) + buf->buffer_base);
1047 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1048 if (buf->remap_table){
1049 for (i = 0; i < count; i++) {
1050 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
1051 OUT_CS_TABLE(data, 4);
1052 }
1053 } else {
1054 OUT_CS_TABLE(buf->ptr, count * 4);
1055 }
1056 }
1057
1058 /* Emit immediates. */
1059 if (imm_count) {
1060 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1061 (r300->screen->caps.is_r500 ?
1062 R500_PVS_CONST_START : R300_PVS_CONST_START) +
1063 buf->buffer_base + imm_first);
1064 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
1065 for (i = imm_first; i < imm_end; i++) {
1066 const float *data = vs->code.constants.Constants[i].u.Immediate;
1067 OUT_CS_TABLE(data, 4);
1068 }
1069 }
1070 END_CS;
1071 }
1072
1073 void r300_emit_viewport_state(struct r300_context* r300,
1074 unsigned size, void* state)
1075 {
1076 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1077 CS_LOCALS(r300);
1078
1079 BEGIN_CS(size);
1080 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1081 OUT_CS_TABLE(&viewport->xscale, 6);
1082 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1083 END_CS;
1084 }
1085
1086 void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state)
1087 {
1088 struct pipe_framebuffer_state *fb =
1089 (struct pipe_framebuffer_state*)r300->fb_state.state;
1090 struct r300_resource* tex;
1091 CS_LOCALS(r300);
1092
1093 tex = r300_resource(fb->zsbuf->texture);
1094
1095 BEGIN_CS(size);
1096 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2);
1097 OUT_CS(0);
1098 OUT_CS(tex->tex.hiz_dwords[fb->zsbuf->u.tex.level]);
1099 OUT_CS(r300->hiz_clear_value);
1100 END_CS;
1101
1102 /* Mark the current zbuffer's hiz ram as in use. */
1103 r300->hiz_in_use = TRUE;
1104 r300->hiz_func = HIZ_FUNC_NONE;
1105 r300_mark_atom_dirty(r300, &r300->hyperz_state);
1106 }
1107
1108 void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state)
1109 {
1110 struct pipe_framebuffer_state *fb =
1111 (struct pipe_framebuffer_state*)r300->fb_state.state;
1112 struct r300_resource *tex;
1113 CS_LOCALS(r300);
1114
1115 tex = r300_resource(fb->zsbuf->texture);
1116
1117 BEGIN_CS(size);
1118 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2);
1119 OUT_CS(0);
1120 OUT_CS(tex->tex.zmask_dwords[fb->zsbuf->u.tex.level]);
1121 OUT_CS(0);
1122 END_CS;
1123
1124 /* Mark the current zbuffer's zmask as in use. */
1125 r300->zmask_in_use = TRUE;
1126 r300_mark_atom_dirty(r300, &r300->hyperz_state);
1127 }
1128
1129 void r300_emit_ztop_state(struct r300_context* r300,
1130 unsigned size, void* state)
1131 {
1132 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1133 CS_LOCALS(r300);
1134
1135 BEGIN_CS(size);
1136 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1137 END_CS;
1138 }
1139
1140 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1141 {
1142 CS_LOCALS(r300);
1143
1144 BEGIN_CS(size);
1145 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1146 END_CS;
1147 }
1148
1149 boolean r300_emit_buffer_validate(struct r300_context *r300,
1150 boolean do_validate_vertex_buffers,
1151 struct pipe_resource *index_buffer)
1152 {
1153 struct pipe_framebuffer_state *fb =
1154 (struct pipe_framebuffer_state*)r300->fb_state.state;
1155 struct r300_textures_state *texstate =
1156 (struct r300_textures_state*)r300->textures_state.state;
1157 struct r300_resource *tex;
1158 unsigned i;
1159 boolean flushed = FALSE;
1160
1161 validate:
1162 if (r300->fb_state.dirty) {
1163 /* Color buffers... */
1164 for (i = 0; i < fb->nr_cbufs; i++) {
1165 tex = r300_resource(fb->cbufs[i]->texture);
1166 assert(tex && tex->buf && "cbuf is marked, but NULL!");
1167 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf, 0,
1168 r300_surface(fb->cbufs[i])->domain);
1169 }
1170 /* ...depth buffer... */
1171 if (fb->zsbuf) {
1172 tex = r300_resource(fb->zsbuf->texture);
1173 assert(tex && tex->buf && "zsbuf is marked, but NULL!");
1174 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf, 0,
1175 r300_surface(fb->zsbuf)->domain);
1176 }
1177 }
1178 if (r300->textures_state.dirty) {
1179 /* ...textures... */
1180 for (i = 0; i < texstate->count; i++) {
1181 if (!(texstate->tx_enable & (1 << i))) {
1182 continue;
1183 }
1184
1185 tex = r300_resource(texstate->sampler_views[i]->base.texture);
1186 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf, tex->domain, 0);
1187 }
1188 }
1189 /* ...occlusion query buffer... */
1190 if (r300->query_current)
1191 r300->rws->cs_add_reloc(r300->cs, r300->query_current->cs_buf,
1192 0, r300->query_current->domain);
1193 /* ...vertex buffer for SWTCL path... */
1194 if (r300->vbo)
1195 r300->rws->cs_add_reloc(r300->cs, r300_resource(r300->vbo)->cs_buf,
1196 r300_resource(r300->vbo)->domain, 0);
1197 /* ...vertex buffers for HWTCL path... */
1198 if (do_validate_vertex_buffers && r300->vertex_arrays_dirty) {
1199 struct pipe_resource **buf = r300->vbuf_mgr->real_vertex_buffer;
1200 struct pipe_resource **last = r300->vbuf_mgr->real_vertex_buffer +
1201 r300->vbuf_mgr->nr_real_vertex_buffers;
1202 for (; buf != last; buf++) {
1203 if (!*buf)
1204 continue;
1205
1206 r300->rws->cs_add_reloc(r300->cs, r300_resource(*buf)->cs_buf,
1207 r300_resource(*buf)->domain, 0);
1208 }
1209 }
1210 /* ...and index buffer for HWTCL path. */
1211 if (index_buffer)
1212 r300->rws->cs_add_reloc(r300->cs, r300_resource(index_buffer)->cs_buf,
1213 r300_resource(index_buffer)->domain, 0);
1214
1215 /* Now do the validation. */
1216 if (!r300->rws->cs_validate(r300->cs)) {
1217 /* Ooops, an infinite loop, give up. */
1218 if (flushed)
1219 return FALSE;
1220
1221 r300->context.flush(&r300->context, 0, NULL);
1222 flushed = TRUE;
1223 goto validate;
1224 }
1225
1226 return TRUE;
1227 }
1228
1229 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1230 {
1231 struct r300_atom* atom;
1232 unsigned dwords = 0;
1233
1234 foreach_dirty_atom(r300, atom) {
1235 if (atom->dirty) {
1236 dwords += atom->size;
1237 }
1238 }
1239
1240 /* let's reserve some more, just in case */
1241 dwords += 32;
1242
1243 return dwords;
1244 }
1245
1246 unsigned r300_get_num_cs_end_dwords(struct r300_context *r300)
1247 {
1248 unsigned dwords = 0;
1249
1250 /* Emitted in flush. */
1251 dwords += 26; /* emit_query_end */
1252 dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */
1253 if (r300->screen->caps.is_r500)
1254 dwords += 2;
1255
1256 return dwords;
1257 }
1258
1259 /* Emit all dirty state. */
1260 void r300_emit_dirty_state(struct r300_context* r300)
1261 {
1262 struct r300_atom *atom;
1263
1264 foreach_dirty_atom(r300, atom) {
1265 if (atom->dirty) {
1266 atom->emit(r300, atom->size, atom->state);
1267 atom->dirty = FALSE;
1268 }
1269 }
1270
1271 r300->first_dirty = NULL;
1272 r300->last_dirty = NULL;
1273 r300->dirty_hw++;
1274 }