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r300g: always disable unused colorbuffers
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_math.h"
27
28 #include "r300_context.h"
29 #include "r300_cs.h"
30 #include "r300_emit.h"
31 #include "r300_fs.h"
32 #include "r300_screen.h"
33 #include "r300_state_derived.h"
34 #include "r300_state_inlines.h"
35 #include "r300_texture.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300,
39 struct r300_blend_state* blend)
40 {
41 CS_LOCALS(r300);
42 BEGIN_CS(8);
43 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
44 OUT_CS(blend->blend_control);
45 OUT_CS(blend->alpha_blend_control);
46 OUT_CS(blend->color_channel_mask);
47 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
48 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
49 END_CS;
50 }
51
52 void r300_emit_blend_color_state(struct r300_context* r300,
53 struct r300_blend_color_state* bc)
54 {
55 struct r300_screen* r300screen = r300_screen(r300->context.screen);
56 CS_LOCALS(r300);
57
58 if (r300screen->caps->is_r500) {
59 BEGIN_CS(3);
60 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
61 OUT_CS(bc->blend_color_red_alpha);
62 OUT_CS(bc->blend_color_green_blue);
63 END_CS;
64 } else {
65 BEGIN_CS(2);
66 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
67 END_CS;
68 }
69 }
70
71 void r300_emit_clip_state(struct r300_context* r300,
72 struct pipe_clip_state* clip)
73 {
74 int i;
75 struct r300_screen* r300screen = r300_screen(r300->context.screen);
76 CS_LOCALS(r300);
77
78 if (r300screen->caps->has_tcl) {
79 BEGIN_CS(5 + (6 * 4));
80 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
81 (r300screen->caps->is_r500 ?
82 R500_PVS_UCP_START : R300_PVS_UCP_START));
83 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
84 for (i = 0; i < 6; i++) {
85 OUT_CS_32F(clip->ucp[i][0]);
86 OUT_CS_32F(clip->ucp[i][1]);
87 OUT_CS_32F(clip->ucp[i][2]);
88 OUT_CS_32F(clip->ucp[i][3]);
89 }
90 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
91 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
92 END_CS;
93 } else {
94 BEGIN_CS(2);
95 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
96 END_CS;
97 }
98
99 }
100
101 void r300_emit_dsa_state(struct r300_context* r300,
102 struct r300_dsa_state* dsa)
103 {
104 struct r300_screen* r300screen = r300_screen(r300->context.screen);
105 CS_LOCALS(r300);
106
107 BEGIN_CS(r300screen->caps->is_r500 ? 10 : 8);
108 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
109
110 /* not needed since we use the 8bit alpha ref */
111 /*if (r300screen->caps->is_r500) {
112 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
113 }*/
114
115 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
116 OUT_CS(dsa->z_buffer_control);
117 OUT_CS(dsa->z_stencil_control);
118 OUT_CS(dsa->stencil_ref_mask);
119 OUT_CS_REG(R300_ZB_ZTOP, r300->ztop_state.z_buffer_top);
120
121 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
122 if (r300screen->caps->is_r500) {
123 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
124 }
125 END_CS;
126 }
127
128 static const float * get_shader_constant(
129 struct r300_context * r300,
130 struct rc_constant * constant,
131 struct r300_constant_buffer * externals)
132 {
133 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
134 struct pipe_texture *tex;
135
136 switch(constant->Type) {
137 case RC_CONSTANT_EXTERNAL:
138 return externals->constants[constant->u.External];
139
140 case RC_CONSTANT_IMMEDIATE:
141 return constant->u.Immediate;
142
143 case RC_CONSTANT_STATE:
144 switch (constant->u.State[0]) {
145 /* Factor for converting rectangle coords to
146 * normalized coords. Should only show up on non-r500. */
147 case RC_STATE_R300_TEXRECT_FACTOR:
148 tex = &r300->textures[constant->u.State[1]]->tex;
149 vec[0] = 1.0 / tex->width0;
150 vec[1] = 1.0 / tex->height0;
151 break;
152
153 default:
154 debug_printf("r300: Implementation error: "
155 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
156 }
157 break;
158
159 default:
160 debug_printf("r300: Implementation error: "
161 "Unhandled constant type %d\n", constant->Type);
162 }
163
164 /* This should either be (0, 0, 0, 1), which should be a relatively safe
165 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
166 * state factors. */
167 return vec;
168 }
169
170 /* Convert a normal single-precision float into the 7.16 format
171 * used by the R300 fragment shader.
172 */
173 static uint32_t pack_float24(float f)
174 {
175 union {
176 float fl;
177 uint32_t u;
178 } u;
179 float mantissa;
180 int exponent;
181 uint32_t float24 = 0;
182
183 if (f == 0.0)
184 return 0;
185
186 u.fl = f;
187
188 mantissa = frexpf(f, &exponent);
189
190 /* Handle -ve */
191 if (mantissa < 0) {
192 float24 |= (1 << 23);
193 mantissa = mantissa * -1.0;
194 }
195 /* Handle exponent, bias of 63 */
196 exponent += 62;
197 float24 |= (exponent << 16);
198 /* Kill 7 LSB of mantissa */
199 float24 |= (u.u & 0x7FFFFF) >> 7;
200
201 return float24;
202 }
203
204 void r300_emit_fragment_program_code(struct r300_context* r300,
205 struct rX00_fragment_program_code* generic_code)
206 {
207 struct r300_fragment_program_code * code = &generic_code->code.r300;
208 int i;
209 CS_LOCALS(r300);
210
211 BEGIN_CS(15 +
212 code->alu.length * 4 +
213 (code->tex.length ? (1 + code->tex.length) : 0));
214
215 OUT_CS_REG(R300_US_CONFIG, code->config);
216 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
217 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
218
219 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
220 for(i = 0; i < 4; ++i)
221 OUT_CS(code->code_addr[i]);
222
223 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
224 for (i = 0; i < code->alu.length; i++)
225 OUT_CS(code->alu.inst[i].rgb_inst);
226
227 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
228 for (i = 0; i < code->alu.length; i++)
229 OUT_CS(code->alu.inst[i].rgb_addr);
230
231 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
232 for (i = 0; i < code->alu.length; i++)
233 OUT_CS(code->alu.inst[i].alpha_inst);
234
235 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
236 for (i = 0; i < code->alu.length; i++)
237 OUT_CS(code->alu.inst[i].alpha_addr);
238
239 if (code->tex.length) {
240 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
241 for(i = 0; i < code->tex.length; ++i)
242 OUT_CS(code->tex.inst[i]);
243 }
244
245 END_CS;
246 }
247
248 void r300_emit_fs_constant_buffer(struct r300_context* r300,
249 struct rc_constant_list* constants)
250 {
251 int i;
252 CS_LOCALS(r300);
253
254 if (constants->Count == 0)
255 return;
256
257 BEGIN_CS(constants->Count * 4 + 1);
258 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
259 for(i = 0; i < constants->Count; ++i) {
260 const float * data = get_shader_constant(r300,
261 &constants->Constants[i],
262 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
263 OUT_CS(pack_float24(data[0]));
264 OUT_CS(pack_float24(data[1]));
265 OUT_CS(pack_float24(data[2]));
266 OUT_CS(pack_float24(data[3]));
267 }
268 END_CS;
269 }
270
271 void r500_emit_fragment_program_code(struct r300_context* r300,
272 struct rX00_fragment_program_code* generic_code)
273 {
274 struct r500_fragment_program_code * code = &generic_code->code.r500;
275 int i;
276 CS_LOCALS(r300);
277
278 BEGIN_CS(13 +
279 ((code->inst_end + 1) * 6));
280 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
281 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
282 OUT_CS_REG(R500_US_CODE_RANGE,
283 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
284 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
285 OUT_CS_REG(R500_US_CODE_ADDR,
286 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
287
288 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
289 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
290 for (i = 0; i <= code->inst_end; i++) {
291 OUT_CS(code->inst[i].inst0);
292 OUT_CS(code->inst[i].inst1);
293 OUT_CS(code->inst[i].inst2);
294 OUT_CS(code->inst[i].inst3);
295 OUT_CS(code->inst[i].inst4);
296 OUT_CS(code->inst[i].inst5);
297 }
298
299 END_CS;
300 }
301
302 void r500_emit_fs_constant_buffer(struct r300_context* r300,
303 struct rc_constant_list* constants)
304 {
305 int i;
306 CS_LOCALS(r300);
307
308 if (constants->Count == 0)
309 return;
310
311 BEGIN_CS(constants->Count * 4 + 3);
312 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
313 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
314 for (i = 0; i < constants->Count; i++) {
315 const float * data = get_shader_constant(r300,
316 &constants->Constants[i],
317 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
318 OUT_CS_32F(data[0]);
319 OUT_CS_32F(data[1]);
320 OUT_CS_32F(data[2]);
321 OUT_CS_32F(data[3]);
322 }
323 END_CS;
324 }
325
326 void r300_emit_fb_state(struct r300_context* r300,
327 struct pipe_framebuffer_state* fb)
328 {
329 struct r300_texture* tex;
330 struct pipe_surface* surf;
331 int i;
332 CS_LOCALS(r300);
333
334 /* Shouldn't fail unless there is a bug in the state tracker. */
335 assert(fb->nr_cbufs <= 4);
336
337 BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
338 (fb->zsbuf ? 10 : 0) + 4);
339
340 /* Flush and free renderbuffer caches. */
341 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
342 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
343 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
344 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
345 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
346 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
347
348 /* Set up colorbuffers. */
349 for (i = 0; i < fb->nr_cbufs; i++) {
350 surf = fb->cbufs[i];
351 tex = (struct r300_texture*)surf->texture;
352 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
353
354 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
355 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
356
357 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
358 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
359 r300_translate_colorformat(tex->tex.format), 0,
360 RADEON_GEM_DOMAIN_VRAM, 0);
361
362 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
363 r300_translate_out_fmt(surf->format));
364 }
365
366 /* Disable unused colorbuffers. */
367 for (; i < 4; i++) {
368 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
369 }
370
371 /* Set up a zbuffer. */
372 if (fb->zsbuf) {
373 surf = fb->zsbuf;
374 tex = (struct r300_texture*)surf->texture;
375 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
376
377 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
378 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
379
380 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
381
382 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
383 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level], 0,
384 RADEON_GEM_DOMAIN_VRAM, 0);
385 }
386
387 END_CS;
388 }
389
390 static void r300_emit_query_start(struct r300_context *r300)
391 {
392 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
393 struct r300_query *query = r300->query_current;
394 CS_LOCALS(r300);
395
396 if (!query)
397 return;
398
399 BEGIN_CS(4);
400 if (caps->family == CHIP_FAMILY_RV530) {
401 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
402 } else {
403 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
404 }
405 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
406 END_CS;
407 query->begin_emitted = TRUE;
408 }
409
410
411 static void r300_emit_query_finish(struct r300_context *r300,
412 struct r300_query *query)
413 {
414 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
415 CS_LOCALS(r300);
416
417 assert(caps->num_frag_pipes);
418
419 BEGIN_CS(6 * caps->num_frag_pipes + 2);
420 /* I'm not so sure I like this switch, but it's hard to be elegant
421 * when there's so many special cases...
422 *
423 * So here's the basic idea. For each pipe, enable writes to it only,
424 * then put out the relocation for ZPASS_ADDR, taking into account a
425 * 4-byte offset for each pipe. RV380 and older are special; they have
426 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
427 * so there's a chipset cap for that. */
428 switch (caps->num_frag_pipes) {
429 case 4:
430 /* pipe 3 only */
431 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
432 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
433 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
434 0, RADEON_GEM_DOMAIN_GTT, 0);
435 case 3:
436 /* pipe 2 only */
437 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
438 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
439 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
440 0, RADEON_GEM_DOMAIN_GTT, 0);
441 case 2:
442 /* pipe 1 only */
443 /* As mentioned above, accomodate RV380 and older. */
444 OUT_CS_REG(R300_SU_REG_DEST,
445 1 << (caps->high_second_pipe ? 3 : 1));
446 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
447 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
448 0, RADEON_GEM_DOMAIN_GTT, 0);
449 case 1:
450 /* pipe 0 only */
451 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
452 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
453 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
454 0, RADEON_GEM_DOMAIN_GTT, 0);
455 break;
456 default:
457 debug_printf("r300: Implementation error: Chipset reports %d"
458 " pixel pipes!\n", caps->num_frag_pipes);
459 assert(0);
460 }
461
462 /* And, finally, reset it to normal... */
463 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
464 END_CS;
465 }
466
467 static void rv530_emit_query_single(struct r300_context *r300,
468 struct r300_query *query)
469 {
470 CS_LOCALS(r300);
471
472 BEGIN_CS(8);
473 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
474 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
475 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
476 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
477 END_CS;
478 }
479
480 static void rv530_emit_query_double(struct r300_context *r300,
481 struct r300_query *query)
482 {
483 CS_LOCALS(r300);
484
485 BEGIN_CS(14);
486 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
487 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
488 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
489 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
490 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
491 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
492 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
493 END_CS;
494 }
495
496 void r300_emit_query_end(struct r300_context* r300)
497 {
498 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
499 struct r300_query *query = r300->query_current;
500
501 if (!query)
502 return;
503
504 if (query->begin_emitted == FALSE)
505 return;
506
507 if (caps->family == CHIP_FAMILY_RV530) {
508 if (caps->num_z_pipes == 2)
509 rv530_emit_query_double(r300, query);
510 else
511 rv530_emit_query_single(r300, query);
512 } else
513 r300_emit_query_finish(r300, query);
514 }
515
516 void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs)
517 {
518 CS_LOCALS(r300);
519
520 BEGIN_CS(22);
521 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
522 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
523 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
524 OUT_CS(rs->point_minmax);
525 OUT_CS(rs->line_control);
526 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
527 OUT_CS(rs->depth_scale_front);
528 OUT_CS(rs->depth_offset_front);
529 OUT_CS(rs->depth_scale_back);
530 OUT_CS(rs->depth_offset_back);
531 OUT_CS(rs->polygon_offset_enable);
532 OUT_CS(rs->cull_mode);
533 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
534 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
535 OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
536 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
537 END_CS;
538 }
539
540 void r300_emit_rs_block_state(struct r300_context* r300,
541 struct r300_rs_block* rs)
542 {
543 int i;
544 struct r300_screen* r300screen = r300_screen(r300->context.screen);
545 CS_LOCALS(r300);
546
547 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
548
549 BEGIN_CS(21);
550 if (r300screen->caps->is_r500) {
551 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
552 } else {
553 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
554 }
555 for (i = 0; i < 8; i++) {
556 OUT_CS(rs->ip[i]);
557 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
558 }
559
560 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
561 OUT_CS(rs->count);
562 OUT_CS(rs->inst_count);
563
564 if (r300screen->caps->is_r500) {
565 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
566 } else {
567 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
568 }
569 for (i = 0; i < 8; i++) {
570 OUT_CS(rs->inst[i]);
571 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
572 }
573
574 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
575 rs->count, rs->inst_count);
576
577 END_CS;
578 }
579
580 static void r300_emit_scissor_regs(struct r300_context* r300,
581 struct r300_scissor_regs* scissor)
582 {
583 CS_LOCALS(r300);
584
585 BEGIN_CS(3);
586 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
587 OUT_CS(scissor->top_left);
588 OUT_CS(scissor->bottom_right);
589 END_CS;
590 }
591
592 void r300_emit_scissor_state(struct r300_context* r300,
593 struct r300_scissor_state* scissor)
594 {
595 if (r300->rs_state->rs.scissor) {
596 r300_emit_scissor_regs(r300, &scissor->scissor);
597 } else {
598 r300_emit_scissor_regs(r300, &scissor->framebuffer);
599 }
600 }
601
602 void r300_emit_texture(struct r300_context* r300,
603 struct r300_sampler_state* sampler,
604 struct r300_texture* tex,
605 unsigned offset)
606 {
607 uint32_t filter0 = sampler->filter0;
608 uint32_t format0 = tex->state.format0;
609 unsigned min_level, max_level;
610 CS_LOCALS(r300);
611
612 /* to emulate 1D textures through 2D ones correctly */
613 if (tex->tex.target == PIPE_TEXTURE_1D) {
614 filter0 &= ~R300_TX_WRAP_T_MASK;
615 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
616 }
617
618 /* determine min/max levels */
619 /* the MAX_MIP level is the largest (finest) one */
620 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
621 min_level = MIN2(sampler->min_lod, max_level);
622 format0 |= R300_TX_NUM_LEVELS(max_level);
623 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
624
625 BEGIN_CS(16);
626 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
627 (offset << 28));
628 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
629 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
630
631 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
632 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
633 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
634 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
635 OUT_CS_RELOC(tex->buffer, 0,
636 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
637 END_CS;
638 }
639
640 static boolean r300_validate_aos(struct r300_context *r300)
641 {
642 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
643 struct pipe_vertex_element *velem = r300->vertex_element;
644 int i;
645
646 /* Check if formats and strides are aligned to the size of DWORD. */
647 for (i = 0; i < r300->vertex_element_count; i++) {
648 if (vbuf[velem[i].vertex_buffer_index].stride % 4 != 0 ||
649 pf_get_blocksize(velem[i].src_format) % 4 != 0) {
650 return FALSE;
651 }
652 }
653 return TRUE;
654 }
655
656 void r300_emit_aos(struct r300_context* r300, unsigned offset)
657 {
658 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
659 struct pipe_vertex_element *velem = r300->vertex_element;
660 int i;
661 unsigned size1, size2, aos_count = r300->vertex_element_count;
662 unsigned packet_size = (aos_count * 3 + 1) / 2;
663 CS_LOCALS(r300);
664
665 /* XXX Move this checking to a more approriate place. */
666 if (!r300_validate_aos(r300)) {
667 /* XXX We should fallback using Draw. */
668 assert(0);
669 }
670
671 BEGIN_CS(2 + packet_size + aos_count * 2);
672 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
673 OUT_CS(aos_count);
674
675 for (i = 0; i < aos_count - 1; i += 2) {
676 vb1 = &vbuf[velem[i].vertex_buffer_index];
677 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
678 size1 = pf_get_blocksize(velem[i].src_format);
679 size2 = pf_get_blocksize(velem[i+1].src_format);
680
681 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
682 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
683 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
684 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
685 }
686
687 if (aos_count & 1) {
688 vb1 = &vbuf[velem[i].vertex_buffer_index];
689 size1 = pf_get_blocksize(velem[i].src_format);
690
691 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
692 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
693 }
694
695 for (i = 0; i < aos_count; i++) {
696 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
697 RADEON_GEM_DOMAIN_GTT, 0, 0);
698 }
699 END_CS;
700 }
701
702 #if 0
703 void r300_emit_draw_packet(struct r300_context* r300)
704 {
705 CS_LOCALS(r300);
706
707 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
708 "vertex size %d\n", r300->vbo,
709 r300->vertex_info->vinfo.size);
710 /* Set the pointer to our vertex buffer. The emitted values are this:
711 * PACKET3 [3D_LOAD_VBPNTR]
712 * COUNT [1]
713 * FORMAT [size | stride << 8]
714 * OFFSET [offset into BO]
715 * VBPNTR [relocated BO]
716 */
717 BEGIN_CS(7);
718 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
719 OUT_CS(1);
720 OUT_CS(r300->vertex_info->vinfo.size |
721 (r300->vertex_info->vinfo.size << 8));
722 OUT_CS(r300->vbo_offset);
723 OUT_CS_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
724 END_CS;
725 }
726 #endif
727
728 void r300_emit_vertex_format_state(struct r300_context* r300)
729 {
730 int i;
731 CS_LOCALS(r300);
732
733 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
734
735 BEGIN_CS(26);
736 OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info->vinfo.size);
737
738 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
739 OUT_CS(r300->vertex_info->vinfo.hwfmt[0]);
740 OUT_CS(r300->vertex_info->vinfo.hwfmt[1]);
741 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
742 OUT_CS(r300->vertex_info->vinfo.hwfmt[2]);
743 OUT_CS(r300->vertex_info->vinfo.hwfmt[3]);
744 for (i = 0; i < 4; i++) {
745 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
746 r300->vertex_info->vinfo.hwfmt[i]);
747 }
748
749 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
750 for (i = 0; i < 8; i++) {
751 OUT_CS(r300->vertex_info->vap_prog_stream_cntl[i]);
752 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
753 r300->vertex_info->vap_prog_stream_cntl[i]);
754 }
755 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
756 for (i = 0; i < 8; i++) {
757 OUT_CS(r300->vertex_info->vap_prog_stream_cntl_ext[i]);
758 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
759 r300->vertex_info->vap_prog_stream_cntl_ext[i]);
760 }
761 END_CS;
762 }
763
764
765 void r300_emit_vertex_program_code(struct r300_context* r300,
766 struct r300_vertex_program_code* code)
767 {
768 int i;
769 struct r300_screen* r300screen = r300_screen(r300->context.screen);
770 unsigned instruction_count = code->length / 4;
771
772 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
773 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
774 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
775 int temp_count = MAX2(code->num_temporaries, 1);
776 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
777 vtx_mem_size / output_count, 10);
778 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
779
780 CS_LOCALS(r300);
781
782 if (!r300screen->caps->has_tcl) {
783 debug_printf("r300: Implementation error: emit_vertex_shader called,"
784 " but has_tcl is FALSE!\n");
785 return;
786 }
787
788 BEGIN_CS(9 + code->length);
789 /* R300_VAP_PVS_CODE_CNTL_0
790 * R300_VAP_PVS_CONST_CNTL
791 * R300_VAP_PVS_CODE_CNTL_1
792 * See the r5xx docs for instructions on how to use these. */
793 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
794 OUT_CS(R300_PVS_FIRST_INST(0) |
795 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
796 R300_PVS_LAST_INST(instruction_count - 1));
797 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
798 OUT_CS(instruction_count - 1);
799
800 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
801 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
802 for (i = 0; i < code->length; i++)
803 OUT_CS(code->body.d[i]);
804
805 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
806 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
807 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
808 R300_PVS_VF_MAX_VTX_NUM(12) |
809 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
810 END_CS;
811 }
812
813 void r300_emit_vertex_shader(struct r300_context* r300,
814 struct r300_vertex_shader* vs)
815 {
816 r300_emit_vertex_program_code(r300, &vs->code);
817 }
818
819 void r300_emit_vs_constant_buffer(struct r300_context* r300,
820 struct rc_constant_list* constants)
821 {
822 int i;
823 struct r300_screen* r300screen = r300_screen(r300->context.screen);
824 CS_LOCALS(r300);
825
826 if (!r300screen->caps->has_tcl) {
827 debug_printf("r300: Implementation error: emit_vertex_shader called,"
828 " but has_tcl is FALSE!\n");
829 return;
830 }
831
832 if (constants->Count == 0)
833 return;
834
835 BEGIN_CS(constants->Count * 4 + 3);
836 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
837 (r300screen->caps->is_r500 ?
838 R500_PVS_CONST_START : R300_PVS_CONST_START));
839 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
840 for (i = 0; i < constants->Count; i++) {
841 const float * data = get_shader_constant(r300,
842 &constants->Constants[i],
843 &r300->shader_constants[PIPE_SHADER_VERTEX]);
844 OUT_CS_32F(data[0]);
845 OUT_CS_32F(data[1]);
846 OUT_CS_32F(data[2]);
847 OUT_CS_32F(data[3]);
848 }
849 END_CS;
850 }
851
852 void r300_emit_viewport_state(struct r300_context* r300,
853 struct r300_viewport_state* viewport)
854 {
855 CS_LOCALS(r300);
856
857 BEGIN_CS(9);
858 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
859 OUT_CS_32F(viewport->xscale);
860 OUT_CS_32F(viewport->xoffset);
861 OUT_CS_32F(viewport->yscale);
862 OUT_CS_32F(viewport->yoffset);
863 OUT_CS_32F(viewport->zscale);
864 OUT_CS_32F(viewport->zoffset);
865
866 if (r300->rs_state->enable_vte) {
867 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
868 } else {
869 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
870 }
871 END_CS;
872 }
873
874 void r300_emit_texture_count(struct r300_context* r300)
875 {
876 CS_LOCALS(r300);
877
878 BEGIN_CS(2);
879 OUT_CS_REG(R300_TX_ENABLE, (1 << r300->texture_count) - 1);
880 END_CS;
881
882 }
883
884 void r300_flush_textures(struct r300_context* r300)
885 {
886 CS_LOCALS(r300);
887
888 BEGIN_CS(2);
889 OUT_CS_REG(R300_TX_INVALTAGS, 0);
890 END_CS;
891 }
892
893 static void r300_flush_pvs(struct r300_context* r300)
894 {
895 CS_LOCALS(r300);
896
897 BEGIN_CS(2);
898 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
899 END_CS;
900 }
901
902 /* Emit all dirty state. */
903 void r300_emit_dirty_state(struct r300_context* r300)
904 {
905 struct r300_screen* r300screen = r300_screen(r300->context.screen);
906 struct r300_texture* tex;
907 int i, dirty_tex = 0;
908 boolean invalid = FALSE;
909
910 if (!(r300->dirty_state)) {
911 return;
912 }
913
914 /* Check size of CS. */
915 /* Make sure we have at least 8*1024 spare dwords. */
916 /* XXX It would be nice to know the number of dwords we really need to
917 * XXX emit. */
918 if (!r300->winsys->check_cs(r300->winsys, 8*1024)) {
919 r300->context.flush(&r300->context, 0, NULL);
920 }
921
922 /* Clean out BOs. */
923 r300->winsys->reset_bos(r300->winsys);
924
925 validate:
926 /* Color buffers... */
927 for (i = 0; i < r300->framebuffer_state.nr_cbufs; i++) {
928 tex = (struct r300_texture*)r300->framebuffer_state.cbufs[i]->texture;
929 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
930 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
931 0, RADEON_GEM_DOMAIN_VRAM)) {
932 r300->context.flush(&r300->context, 0, NULL);
933 goto validate;
934 }
935 }
936 /* ...depth buffer... */
937 if (r300->framebuffer_state.zsbuf) {
938 tex = (struct r300_texture*)r300->framebuffer_state.zsbuf->texture;
939 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
940 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
941 0, RADEON_GEM_DOMAIN_VRAM)) {
942 r300->context.flush(&r300->context, 0, NULL);
943 goto validate;
944 }
945 }
946 /* ...textures... */
947 for (i = 0; i < r300->texture_count; i++) {
948 tex = r300->textures[i];
949 if (!tex)
950 continue;
951 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
952 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
953 r300->context.flush(&r300->context, 0, NULL);
954 goto validate;
955 }
956 }
957 /* ...occlusion query buffer... */
958 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
959 0, RADEON_GEM_DOMAIN_GTT)) {
960 r300->context.flush(&r300->context, 0, NULL);
961 goto validate;
962 }
963 /* ...and vertex buffer. */
964 if (r300->vbo) {
965 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
966 RADEON_GEM_DOMAIN_GTT, 0)) {
967 r300->context.flush(&r300->context, 0, NULL);
968 goto validate;
969 }
970 } else {
971 // debug_printf("No VBO while emitting dirty state!\n");
972 }
973 if (!r300->winsys->validate(r300->winsys)) {
974 r300->context.flush(&r300->context, 0, NULL);
975 if (invalid) {
976 /* Well, hell. */
977 debug_printf("r300: Stuck in validation loop, gonna quit now.");
978 exit(1);
979 }
980 invalid = TRUE;
981 goto validate;
982 }
983
984 if (r300->dirty_state & R300_NEW_QUERY) {
985 r300_emit_query_start(r300);
986 r300->dirty_state &= ~R300_NEW_QUERY;
987 }
988
989 if (r300->dirty_state & R300_NEW_BLEND) {
990 r300_emit_blend_state(r300, r300->blend_state);
991 r300->dirty_state &= ~R300_NEW_BLEND;
992 }
993
994 if (r300->dirty_state & R300_NEW_BLEND_COLOR) {
995 r300_emit_blend_color_state(r300, r300->blend_color_state);
996 r300->dirty_state &= ~R300_NEW_BLEND_COLOR;
997 }
998
999 if (r300->dirty_state & R300_NEW_CLIP) {
1000 r300_emit_clip_state(r300, &r300->clip_state);
1001 r300->dirty_state &= ~R300_NEW_CLIP;
1002 }
1003
1004 if (r300->dirty_state & R300_NEW_DSA) {
1005 r300_emit_dsa_state(r300, r300->dsa_state);
1006 r300->dirty_state &= ~R300_NEW_DSA;
1007 }
1008
1009 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1010 if (r300screen->caps->is_r500) {
1011 r500_emit_fragment_program_code(r300, &r300->fs->code);
1012 } else {
1013 r300_emit_fragment_program_code(r300, &r300->fs->code);
1014 }
1015 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1016 }
1017
1018 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1019 if (r300screen->caps->is_r500) {
1020 r500_emit_fs_constant_buffer(r300, &r300->fs->code.constants);
1021 } else {
1022 r300_emit_fs_constant_buffer(r300, &r300->fs->code.constants);
1023 }
1024 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1025 }
1026
1027 if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
1028 r300_emit_fb_state(r300, &r300->framebuffer_state);
1029 r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
1030 }
1031
1032 if (r300->dirty_state & R300_NEW_RASTERIZER) {
1033 r300_emit_rs_state(r300, r300->rs_state);
1034 r300->dirty_state &= ~R300_NEW_RASTERIZER;
1035 }
1036
1037 if (r300->dirty_state & R300_NEW_RS_BLOCK) {
1038 r300_emit_rs_block_state(r300, r300->rs_block);
1039 r300->dirty_state &= ~R300_NEW_RS_BLOCK;
1040 }
1041
1042 if (r300->dirty_state & R300_NEW_SCISSOR) {
1043 r300_emit_scissor_state(r300, r300->scissor_state);
1044 r300->dirty_state &= ~R300_NEW_SCISSOR;
1045 }
1046
1047 /* Samplers and textures are tracked separately but emitted together. */
1048 if (r300->dirty_state &
1049 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1050 r300_emit_texture_count(r300);
1051
1052 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1053 if (r300->dirty_state &
1054 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1055 if (r300->textures[i])
1056 r300_emit_texture(r300,
1057 r300->sampler_states[i],
1058 r300->textures[i],
1059 i);
1060 r300->dirty_state &=
1061 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1062 dirty_tex++;
1063 }
1064 }
1065 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1066 }
1067
1068 if (r300->dirty_state & R300_NEW_VIEWPORT) {
1069 r300_emit_viewport_state(r300, r300->viewport_state);
1070 r300->dirty_state &= ~R300_NEW_VIEWPORT;
1071 }
1072
1073 if (dirty_tex) {
1074 r300_flush_textures(r300);
1075 }
1076
1077 if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
1078 r300_emit_vertex_format_state(r300);
1079 r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
1080 }
1081
1082 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1083 r300_flush_pvs(r300);
1084 }
1085
1086 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1087 r300_emit_vertex_shader(r300, r300->vs);
1088 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1089 }
1090
1091 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1092 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1093 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1094 }
1095
1096 /* XXX
1097 assert(r300->dirty_state == 0);
1098 */
1099
1100 /* Finally, emit the VBO. */
1101 //r300_emit_vertex_buffer(r300);
1102
1103 r300->dirty_hw++;
1104 }