r300g: fix glsl-fs-pointcoord
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29 #include "util/u_simple_list.h"
30
31 #include "r300_context.h"
32 #include "r300_cs.h"
33 #include "r300_emit.h"
34 #include "r300_fs.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
37 #include "r300_vs.h"
38
39 void r300_emit_blend_state(struct r300_context* r300,
40 unsigned size, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 struct pipe_framebuffer_state* fb =
44 (struct pipe_framebuffer_state*)r300->fb_state.state;
45 CS_LOCALS(r300);
46
47 if (fb->nr_cbufs) {
48 WRITE_CS_TABLE(blend->cb, size);
49 } else {
50 WRITE_CS_TABLE(blend->cb_no_readwrite, size);
51 }
52 }
53
54 void r300_emit_blend_color_state(struct r300_context* r300,
55 unsigned size, void* state)
56 {
57 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
58 CS_LOCALS(r300);
59
60 WRITE_CS_TABLE(bc->cb, size);
61 }
62
63 void r300_emit_clip_state(struct r300_context* r300,
64 unsigned size, void* state)
65 {
66 struct r300_clip_state* clip = (struct r300_clip_state*)state;
67 CS_LOCALS(r300);
68
69 WRITE_CS_TABLE(clip->cb, size);
70 }
71
72 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
73 {
74 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
75 struct pipe_framebuffer_state* fb =
76 (struct pipe_framebuffer_state*)r300->fb_state.state;
77 CS_LOCALS(r300);
78
79 if (fb->zsbuf) {
80 WRITE_CS_TABLE(&dsa->cb_begin, size);
81 } else {
82 WRITE_CS_TABLE(dsa->cb_no_readwrite, size);
83 }
84 }
85
86 static const float * get_rc_constant_state(
87 struct r300_context * r300,
88 struct rc_constant * constant)
89 {
90 struct r300_textures_state* texstate = r300->textures_state.state;
91 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
92 struct pipe_resource *tex;
93
94 assert(constant->Type == RC_CONSTANT_STATE);
95
96 switch (constant->u.State[0]) {
97 /* Factor for converting rectangle coords to
98 * normalized coords. Should only show up on non-r500. */
99 case RC_STATE_R300_TEXRECT_FACTOR:
100 tex = texstate->sampler_views[constant->u.State[1]]->base.texture;
101 vec[0] = 1.0 / tex->width0;
102 vec[1] = 1.0 / tex->height0;
103 break;
104
105 case RC_STATE_R300_VIEWPORT_SCALE:
106 vec[0] = r300->viewport.scale[0];
107 vec[1] = r300->viewport.scale[1];
108 vec[2] = r300->viewport.scale[2];
109 break;
110
111 case RC_STATE_R300_VIEWPORT_OFFSET:
112 vec[0] = r300->viewport.translate[0];
113 vec[1] = r300->viewport.translate[1];
114 vec[2] = r300->viewport.translate[2];
115 break;
116
117 default:
118 fprintf(stderr, "r300: Implementation error: "
119 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
120 }
121
122 /* This should either be (0, 0, 0, 1), which should be a relatively safe
123 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
124 * state factors. */
125 return vec;
126 }
127
128 /* Convert a normal single-precision float into the 7.16 format
129 * used by the R300 fragment shader.
130 */
131 uint32_t pack_float24(float f)
132 {
133 union {
134 float fl;
135 uint32_t u;
136 } u;
137 float mantissa;
138 int exponent;
139 uint32_t float24 = 0;
140
141 if (f == 0.0)
142 return 0;
143
144 u.fl = f;
145
146 mantissa = frexpf(f, &exponent);
147
148 /* Handle -ve */
149 if (mantissa < 0) {
150 float24 |= (1 << 23);
151 mantissa = mantissa * -1.0;
152 }
153 /* Handle exponent, bias of 63 */
154 exponent += 62;
155 float24 |= (exponent << 16);
156 /* Kill 7 LSB of mantissa */
157 float24 |= (u.u & 0x7FFFFF) >> 7;
158
159 return float24;
160 }
161
162 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
163 {
164 struct r300_fragment_shader *fs = r300_fs(r300);
165 CS_LOCALS(r300);
166
167 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
168 }
169
170 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
171 {
172 struct r300_fragment_shader *fs = r300_fs(r300);
173 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
174 unsigned count = fs->shader->externals_count;
175 unsigned i, j;
176 CS_LOCALS(r300);
177
178 if (count == 0)
179 return;
180
181 BEGIN_CS(size);
182 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
183 if (buf->remap_table){
184 for (i = 0; i < count; i++) {
185 float *data = (float*)&buf->ptr[buf->remap_table[i]*4];
186 for (j = 0; j < 4; j++)
187 OUT_CS(pack_float24(data[j]));
188 }
189 } else {
190 for (i = 0; i < count; i++)
191 for (j = 0; j < 4; j++)
192 OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j]));
193 }
194
195 END_CS;
196 }
197
198 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
199 {
200 struct r300_fragment_shader *fs = r300_fs(r300);
201 struct rc_constant_list *constants = &fs->shader->code.constants;
202 unsigned i;
203 unsigned count = fs->shader->rc_state_count;
204 unsigned first = fs->shader->externals_count;
205 unsigned end = constants->Count;
206 unsigned j;
207 CS_LOCALS(r300);
208
209 if (count == 0)
210 return;
211
212 BEGIN_CS(size);
213 for(i = first; i < end; ++i) {
214 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
215 const float *data =
216 get_rc_constant_state(r300, &constants->Constants[i]);
217
218 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
219 for (j = 0; j < 4; j++)
220 OUT_CS(pack_float24(data[j]));
221 }
222 }
223 END_CS;
224 }
225
226 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
227 {
228 struct r300_fragment_shader *fs = r300_fs(r300);
229 CS_LOCALS(r300);
230
231 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
232 }
233
234 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
235 {
236 struct r300_fragment_shader *fs = r300_fs(r300);
237 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
238 unsigned count = fs->shader->externals_count;
239 CS_LOCALS(r300);
240
241 if (count == 0)
242 return;
243
244 BEGIN_CS(size);
245 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
246 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
247 if (buf->remap_table){
248 for (unsigned i = 0; i < count; i++) {
249 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
250 OUT_CS_TABLE(data, 4);
251 }
252 } else {
253 OUT_CS_TABLE(buf->ptr, count * 4);
254 }
255 END_CS;
256 }
257
258 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
259 {
260 struct r300_fragment_shader *fs = r300_fs(r300);
261 struct rc_constant_list *constants = &fs->shader->code.constants;
262 unsigned i;
263 unsigned count = fs->shader->rc_state_count;
264 unsigned first = fs->shader->externals_count;
265 unsigned end = constants->Count;
266 CS_LOCALS(r300);
267
268 if (count == 0)
269 return;
270
271 BEGIN_CS(size);
272 for(i = first; i < end; ++i) {
273 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
274 const float *data =
275 get_rc_constant_state(r300, &constants->Constants[i]);
276
277 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
278 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
279 (i & R500_GA_US_VECTOR_INDEX_MASK));
280 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
281 OUT_CS_TABLE(data, 4);
282 }
283 }
284 END_CS;
285 }
286
287 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
288 {
289 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
290 struct pipe_framebuffer_state* fb =
291 (struct pipe_framebuffer_state*)r300->fb_state.state;
292 uint32_t height = fb->height;
293 uint32_t width = fb->width;
294 CS_LOCALS(r300);
295
296 if (r300->cbzb_clear) {
297 struct r300_surface *surf = r300_surface(fb->cbufs[0]);
298
299 height = surf->cbzb_height;
300 width = surf->cbzb_width;
301 }
302
303 DBG(r300, DBG_SCISSOR,
304 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
305 width, height, r300->cbzb_clear ? "YES" : "NO");
306
307 BEGIN_CS(size);
308
309 /* Set up scissors.
310 * By writing to the SC registers, SC & US assert idle. */
311 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
312 if (r300->screen->caps.is_r500) {
313 OUT_CS(0);
314 OUT_CS(((width - 1) << R300_SCISSORS_X_SHIFT) |
315 ((height - 1) << R300_SCISSORS_Y_SHIFT));
316 } else {
317 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
318 (1440 << R300_SCISSORS_Y_SHIFT));
319 OUT_CS(((width + 1440-1) << R300_SCISSORS_X_SHIFT) |
320 ((height + 1440-1) << R300_SCISSORS_Y_SHIFT));
321 }
322
323 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
324 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
325 END_CS;
326 }
327
328 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
329 {
330 struct r300_aa_state *aa = (struct r300_aa_state*)state;
331 CS_LOCALS(r300);
332
333 BEGIN_CS(size);
334 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
335
336 if (aa->dest) {
337 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET, 1);
338 OUT_CS_RELOC(aa->dest->buffer, aa->dest->offset, 0, aa->dest->domain);
339
340 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_PITCH, 1);
341 OUT_CS_RELOC(aa->dest->buffer, aa->dest->pitch, 0, aa->dest->domain);
342 }
343
344 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, aa->aaresolve_ctl);
345 END_CS;
346 }
347
348 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
349 {
350 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
351 struct r300_surface* surf;
352 unsigned i;
353 boolean has_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
354 CS_LOCALS(r300);
355
356 BEGIN_CS(size);
357
358 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
359 * what we usually want. */
360 if (r300->screen->caps.is_r500) {
361 OUT_CS_REG(R300_RB3D_CCTL,
362 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
363 } else {
364 OUT_CS_REG(R300_RB3D_CCTL, 0);
365 }
366
367 /* Set up colorbuffers. */
368 for (i = 0; i < fb->nr_cbufs; i++) {
369 surf = r300_surface(fb->cbufs[i]);
370
371 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
372 OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain);
373
374 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
375 OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain);
376 }
377
378 /* Set up the ZB part of the CBZB clear. */
379 if (r300->cbzb_clear) {
380 surf = r300_surface(fb->cbufs[0]);
381
382 OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format);
383
384 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
385 OUT_CS_RELOC(surf->buffer, surf->cbzb_midpoint_offset, 0, surf->domain);
386
387 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
388 OUT_CS_RELOC(surf->buffer, surf->cbzb_pitch, 0, surf->domain);
389
390 DBG(r300, DBG_CBZB,
391 "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format,
392 surf->cbzb_pitch);
393 }
394 /* Set up a zbuffer. */
395 else if (fb->zsbuf) {
396 surf = r300_surface(fb->zsbuf);
397
398 OUT_CS_REG(R300_ZB_FORMAT, surf->format);
399
400 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
401 OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain);
402
403 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
404 OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain);
405
406 if (has_hyperz) {
407 uint32_t surf_pitch;
408 struct r300_texture *tex;
409 int level = surf->base.level;
410 tex = r300_texture(surf->base.texture);
411
412 surf_pitch = surf->pitch & R300_DEPTHPITCH_MASK;
413 /* HiZ RAM. */
414 if (r300->screen->caps.hiz_ram) {
415 if (tex->hiz_mem[level]) {
416 OUT_CS_REG(R300_ZB_HIZ_OFFSET, tex->hiz_mem[level]->ofs << 2);
417 OUT_CS_REG(R300_ZB_HIZ_PITCH, surf_pitch);
418 } else {
419 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
420 OUT_CS_REG(R300_ZB_HIZ_PITCH, 0);
421 }
422 }
423 /* Z Mask RAM. (compressed zbuffer) */
424 if (tex->zmask_mem[level]) {
425 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, tex->zmask_mem[level]->ofs << 2);
426 OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf_pitch);
427 } else {
428 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
429 OUT_CS_REG(R300_ZB_ZMASK_PITCH, 0);
430 }
431 }
432 }
433
434 END_CS;
435 }
436
437 void r300_emit_hyperz_state(struct r300_context *r300,
438 unsigned size, void *state)
439 {
440 struct r300_hyperz_state *z = state;
441 CS_LOCALS(r300);
442 if (z->flush)
443 WRITE_CS_TABLE(&z->cb_flush_begin, size);
444 else
445 WRITE_CS_TABLE(&z->cb_begin, size - 2);
446 }
447
448 void r300_emit_hyperz_end(struct r300_context *r300)
449 {
450 struct r300_hyperz_state z =
451 *(struct r300_hyperz_state*)r300->hyperz_state.state;
452
453 z.flush = 1;
454 z.zb_bw_cntl = 0;
455 z.zb_depthclearvalue = 0;
456 z.sc_hyperz = R300_SC_HYPERZ_ADJ_2;
457 z.gb_z_peq_config = 0;
458
459 r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z);
460 }
461
462 void r300_emit_fb_state_pipelined(struct r300_context *r300,
463 unsigned size, void *state)
464 {
465 struct pipe_framebuffer_state* fb =
466 (struct pipe_framebuffer_state*)r300->fb_state.state;
467 unsigned i;
468 CS_LOCALS(r300);
469
470 BEGIN_CS(size);
471
472 /* Colorbuffer format in the US block.
473 * (must be written after unpipelined regs) */
474 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
475 for (i = 0; i < fb->nr_cbufs; i++) {
476 OUT_CS(r300_surface(fb->cbufs[i])->format);
477 }
478 for (; i < 4; i++) {
479 OUT_CS(R300_US_OUT_FMT_UNUSED);
480 }
481
482 /* Multisampling. Depends on framebuffer sample count.
483 * These are pipelined regs and as such cannot be moved
484 * to the AA state. */
485 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
486 unsigned mspos0 = 0x66666666;
487 unsigned mspos1 = 0x6666666;
488
489 if (fb->nr_cbufs && fb->cbufs[0]->texture->nr_samples > 1) {
490 /* Subsample placement. These may not be optimal. */
491 switch (fb->cbufs[0]->texture->nr_samples) {
492 case 2:
493 mspos0 = 0x33996633;
494 mspos1 = 0x6666663;
495 break;
496 case 3:
497 mspos0 = 0x33936933;
498 mspos1 = 0x6666663;
499 break;
500 case 4:
501 mspos0 = 0x33939933;
502 mspos1 = 0x3966663;
503 break;
504 case 6:
505 mspos0 = 0x22a2aa22;
506 mspos1 = 0x2a65672;
507 break;
508 default:
509 debug_printf("r300: Bad number of multisamples!\n");
510 }
511 }
512
513 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
514 OUT_CS(mspos0);
515 OUT_CS(mspos1);
516 }
517 END_CS;
518 }
519
520 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
521 {
522 struct r300_query *query = r300->query_current;
523 CS_LOCALS(r300);
524
525 if (!query)
526 return;
527
528 BEGIN_CS(size);
529 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
530 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
531 } else {
532 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
533 }
534 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
535 END_CS;
536 query->begin_emitted = TRUE;
537 query->flushed = FALSE;
538 }
539
540 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
541 struct r300_query *query)
542 {
543 struct r300_capabilities* caps = &r300->screen->caps;
544 struct r300_winsys_buffer *buf = r300->query_current->buffer;
545 CS_LOCALS(r300);
546
547 assert(caps->num_frag_pipes);
548
549 BEGIN_CS(6 * caps->num_frag_pipes + 2);
550 /* I'm not so sure I like this switch, but it's hard to be elegant
551 * when there's so many special cases...
552 *
553 * So here's the basic idea. For each pipe, enable writes to it only,
554 * then put out the relocation for ZPASS_ADDR, taking into account a
555 * 4-byte offset for each pipe. RV380 and older are special; they have
556 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
557 * so there's a chipset cap for that. */
558 switch (caps->num_frag_pipes) {
559 case 4:
560 /* pipe 3 only */
561 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
562 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
563 OUT_CS_RELOC(buf, (query->num_results + 3) * 4,
564 0, query->domain);
565 case 3:
566 /* pipe 2 only */
567 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
568 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
569 OUT_CS_RELOC(buf, (query->num_results + 2) * 4,
570 0, query->domain);
571 case 2:
572 /* pipe 1 only */
573 /* As mentioned above, accomodate RV380 and older. */
574 OUT_CS_REG(R300_SU_REG_DEST,
575 1 << (caps->high_second_pipe ? 3 : 1));
576 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
577 OUT_CS_RELOC(buf, (query->num_results + 1) * 4,
578 0, query->domain);
579 case 1:
580 /* pipe 0 only */
581 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
582 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
583 OUT_CS_RELOC(buf, (query->num_results + 0) * 4,
584 0, query->domain);
585 break;
586 default:
587 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
588 " pixel pipes!\n", caps->num_frag_pipes);
589 abort();
590 }
591
592 /* And, finally, reset it to normal... */
593 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
594 END_CS;
595 }
596
597 static void rv530_emit_query_end_single_z(struct r300_context *r300,
598 struct r300_query *query)
599 {
600 struct r300_winsys_buffer *buf = r300->query_current->buffer;
601 CS_LOCALS(r300);
602
603 BEGIN_CS(8);
604 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
605 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
606 OUT_CS_RELOC(buf, query->num_results * 4, 0, query->domain);
607 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
608 END_CS;
609 }
610
611 static void rv530_emit_query_end_double_z(struct r300_context *r300,
612 struct r300_query *query)
613 {
614 struct r300_winsys_buffer *buf = r300->query_current->buffer;
615 CS_LOCALS(r300);
616
617 BEGIN_CS(14);
618 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
619 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
620 OUT_CS_RELOC(buf, (query->num_results + 0) * 4, 0, query->domain);
621 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
622 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
623 OUT_CS_RELOC(buf, (query->num_results + 1) * 4, 0, query->domain);
624 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
625 END_CS;
626 }
627
628 void r300_emit_query_end(struct r300_context* r300)
629 {
630 struct r300_capabilities *caps = &r300->screen->caps;
631 struct r300_query *query = r300->query_current;
632
633 if (!query)
634 return;
635
636 if (query->begin_emitted == FALSE)
637 return;
638
639 if (caps->family == CHIP_FAMILY_RV530) {
640 if (caps->num_z_pipes == 2)
641 rv530_emit_query_end_double_z(r300, query);
642 else
643 rv530_emit_query_end_single_z(r300, query);
644 } else
645 r300_emit_query_end_frag_pipes(r300, query);
646
647 query->begin_emitted = FALSE;
648 query->num_results += query->num_pipes;
649
650 /* XXX grab all the results and reset the counter. */
651 if (query->num_results >= query->buffer_size / 4 - 4) {
652 query->num_results = (query->buffer_size / 4) / 2;
653 fprintf(stderr, "r300: Rewinding OQBO...\n");
654 }
655 }
656
657 void r300_emit_invariant_state(struct r300_context *r300,
658 unsigned size, void *state)
659 {
660 CS_LOCALS(r300);
661 WRITE_CS_TABLE(state, size);
662 }
663
664 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
665 {
666 struct r300_rs_state* rs = state;
667 CS_LOCALS(r300);
668
669 BEGIN_CS(size);
670 OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE);
671 if (rs->polygon_offset_enable) {
672 if (r300->zbuffer_bpp == 16) {
673 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5);
674 } else {
675 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5);
676 }
677 }
678 END_CS;
679 }
680
681 void r300_emit_rs_block_state(struct r300_context* r300,
682 unsigned size, void* state)
683 {
684 struct r300_rs_block* rs = (struct r300_rs_block*)state;
685 unsigned i;
686 /* It's the same for both INST and IP tables */
687 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
688 CS_LOCALS(r300);
689
690 if (DBG_ON(r300, DBG_RS_BLOCK)) {
691 r500_dump_rs_block(rs);
692
693 fprintf(stderr, "r300: RS emit:\n");
694
695 for (i = 0; i < count; i++)
696 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]);
697
698 for (i = 0; i < count; i++)
699 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]);
700
701 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n",
702 rs->count, rs->inst_count);
703 }
704
705 BEGIN_CS(size);
706 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
707 OUT_CS(rs->vap_vtx_state_cntl);
708 OUT_CS(rs->vap_vsm_vtx_assm);
709 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
710 OUT_CS(rs->vap_out_vtx_fmt[0]);
711 OUT_CS(rs->vap_out_vtx_fmt[1]);
712 OUT_CS_REG_SEQ(R300_GB_ENABLE, 1);
713 OUT_CS(rs->gb_enable);
714
715 if (r300->screen->caps.is_r500) {
716 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
717 } else {
718 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
719 }
720 OUT_CS_TABLE(rs->ip, count);
721
722 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
723 OUT_CS(rs->count);
724 OUT_CS(rs->inst_count);
725
726 if (r300->screen->caps.is_r500) {
727 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
728 } else {
729 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
730 }
731 OUT_CS_TABLE(rs->inst, count);
732 END_CS;
733 }
734
735 void r300_emit_scissor_state(struct r300_context* r300,
736 unsigned size, void* state)
737 {
738 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
739 CS_LOCALS(r300);
740
741 BEGIN_CS(size);
742 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
743 if (r300->screen->caps.is_r500) {
744 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
745 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
746 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
747 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
748 } else {
749 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
750 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
751 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
752 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
753 }
754 END_CS;
755 }
756
757 void r300_emit_textures_state(struct r300_context *r300,
758 unsigned size, void *state)
759 {
760 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
761 struct r300_texture_sampler_state *texstate;
762 struct r300_texture *tex;
763 unsigned i;
764 CS_LOCALS(r300);
765
766 BEGIN_CS(size);
767 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
768
769 for (i = 0; i < allstate->count; i++) {
770 if ((1 << i) & allstate->tx_enable) {
771 texstate = &allstate->regs[i];
772 tex = r300_texture(allstate->sampler_views[i]->base.texture);
773
774 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
775 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
776 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
777 texstate->border_color);
778
779 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
780 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
781 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
782
783 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
784 OUT_CS_TEX_RELOC(tex, texstate->format.tile_config, tex->domain,
785 0);
786 }
787 }
788 END_CS;
789 }
790
791 void r300_emit_aos(struct r300_context* r300, int offset, boolean indexed)
792 {
793 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
794 struct pipe_vertex_element *velem = r300->velems->velem;
795 struct r300_buffer *buf;
796 int i;
797 unsigned *hw_format_size = r300->velems->hw_format_size;
798 unsigned size1, size2, aos_count = r300->velems->count;
799 unsigned packet_size = (aos_count * 3 + 1) / 2;
800 CS_LOCALS(r300);
801
802 BEGIN_CS(2 + packet_size + aos_count * 2);
803 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
804 OUT_CS(aos_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
805
806 for (i = 0; i < aos_count - 1; i += 2) {
807 vb1 = &vbuf[velem[i].vertex_buffer_index];
808 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
809 size1 = hw_format_size[i];
810 size2 = hw_format_size[i+1];
811
812 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
813 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
814 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
815 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
816 }
817
818 if (aos_count & 1) {
819 vb1 = &vbuf[velem[i].vertex_buffer_index];
820 size1 = hw_format_size[i];
821
822 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
823 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
824 }
825
826 for (i = 0; i < aos_count; i++) {
827 buf = r300_buffer(vbuf[velem[i].vertex_buffer_index].buffer);
828 OUT_CS_BUF_RELOC_NO_OFFSET(&buf->b.b, buf->domain, 0);
829 }
830 END_CS;
831 }
832
833 void r300_emit_aos_swtcl(struct r300_context *r300, boolean indexed)
834 {
835 CS_LOCALS(r300);
836
837 DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, "
838 "vertex size %d\n", r300->vbo,
839 r300->vertex_info.size);
840 /* Set the pointer to our vertex buffer. The emitted values are this:
841 * PACKET3 [3D_LOAD_VBPNTR]
842 * COUNT [1]
843 * FORMAT [size | stride << 8]
844 * OFFSET [offset into BO]
845 * VBPNTR [relocated BO]
846 */
847 BEGIN_CS(7);
848 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
849 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
850 OUT_CS(r300->vertex_info.size |
851 (r300->vertex_info.size << 8));
852 OUT_CS(r300->draw_vbo_offset);
853 OUT_CS_BUF_RELOC(r300->vbo, 0, r300_buffer(r300->vbo)->domain, 0);
854 END_CS;
855 }
856
857 void r300_emit_vertex_stream_state(struct r300_context* r300,
858 unsigned size, void* state)
859 {
860 struct r300_vertex_stream_state *streams =
861 (struct r300_vertex_stream_state*)state;
862 unsigned i;
863 CS_LOCALS(r300);
864
865 if (DBG_ON(r300, DBG_PSC)) {
866 fprintf(stderr, "r300: PSC emit:\n");
867
868 for (i = 0; i < streams->count; i++) {
869 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i,
870 streams->vap_prog_stream_cntl[i]);
871 }
872
873 for (i = 0; i < streams->count; i++) {
874 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
875 streams->vap_prog_stream_cntl_ext[i]);
876 }
877 }
878
879 BEGIN_CS(size);
880 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
881 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
882 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
883 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
884 END_CS;
885 }
886
887 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
888 {
889 CS_LOCALS(r300);
890
891 BEGIN_CS(size);
892 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
893 END_CS;
894 }
895
896 void r300_emit_vap_invariant_state(struct r300_context *r300,
897 unsigned size, void *state)
898 {
899 CS_LOCALS(r300);
900 WRITE_CS_TABLE(state, size);
901 }
902
903 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
904 {
905 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
906 struct r300_vertex_program_code* code = &vs->code;
907 struct r300_screen* r300screen = r300->screen;
908 unsigned instruction_count = code->length / 4;
909 unsigned i;
910
911 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
912 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
913 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
914 unsigned temp_count = MAX2(code->num_temporaries, 1);
915
916 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
917 vtx_mem_size / output_count, 10);
918 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5);
919
920 unsigned imm_first = vs->externals_count;
921 unsigned imm_end = vs->code.constants.Count;
922 unsigned imm_count = vs->immediates_count;
923
924 CS_LOCALS(r300);
925
926 BEGIN_CS(size);
927
928 /* R300_VAP_PVS_CODE_CNTL_0
929 * R300_VAP_PVS_CONST_CNTL
930 * R300_VAP_PVS_CODE_CNTL_1
931 * See the r5xx docs for instructions on how to use these. */
932 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
933 OUT_CS(R300_PVS_FIRST_INST(0) |
934 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
935 R300_PVS_LAST_INST(instruction_count - 1));
936 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
937 OUT_CS(instruction_count - 1);
938
939 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
940 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
941 OUT_CS_TABLE(code->body.d, code->length);
942
943 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
944 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
945 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
946 R300_PVS_VF_MAX_VTX_NUM(12) |
947 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
948
949 /* Emit immediates. */
950 if (imm_count) {
951 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
952 (r300->screen->caps.is_r500 ?
953 R500_PVS_CONST_START : R300_PVS_CONST_START) +
954 imm_first);
955 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
956 for (i = imm_first; i < imm_end; i++) {
957 const float *data = vs->code.constants.Constants[i].u.Immediate;
958 OUT_CS_TABLE(data, 4);
959 }
960 }
961
962 /* Emit flow control instructions. */
963 if (code->num_fc_ops) {
964
965 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops);
966 if (r300screen->caps.is_r500) {
967 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, code->num_fc_ops * 2);
968 OUT_CS_TABLE(code->fc_op_addrs.r500, code->num_fc_ops * 2);
969 } else {
970 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, code->num_fc_ops);
971 OUT_CS_TABLE(code->fc_op_addrs.r300, code->num_fc_ops);
972 }
973 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, code->num_fc_ops);
974 OUT_CS_TABLE(code->fc_loop_index, code->num_fc_ops);
975 }
976
977 END_CS;
978 }
979
980 void r300_emit_vs_constants(struct r300_context* r300,
981 unsigned size, void *state)
982 {
983 unsigned count =
984 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
985 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
986 unsigned i;
987 CS_LOCALS(r300);
988
989 if (!count)
990 return;
991
992 BEGIN_CS(size);
993 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
994 (r300->screen->caps.is_r500 ?
995 R500_PVS_CONST_START : R300_PVS_CONST_START));
996 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
997 if (buf->remap_table){
998 for (i = 0; i < count; i++) {
999 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
1000 OUT_CS_TABLE(data, 4);
1001 }
1002 } else {
1003 OUT_CS_TABLE(buf->ptr, count * 4);
1004 }
1005 END_CS;
1006 }
1007
1008 void r300_emit_viewport_state(struct r300_context* r300,
1009 unsigned size, void* state)
1010 {
1011 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1012 CS_LOCALS(r300);
1013
1014 BEGIN_CS(size);
1015 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1016 OUT_CS_TABLE(&viewport->xscale, 6);
1017 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1018 END_CS;
1019 }
1020
1021 static void r300_emit_hiz_line_clear(struct r300_context *r300, int start, uint16_t count, uint32_t val)
1022 {
1023 CS_LOCALS(r300);
1024 BEGIN_CS(4);
1025 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2);
1026 OUT_CS(start);
1027 OUT_CS(count);
1028 OUT_CS(val);
1029 END_CS;
1030 }
1031
1032 static void r300_emit_zmask_line_clear(struct r300_context *r300, int start, uint16_t count, uint32_t val)
1033 {
1034 CS_LOCALS(r300);
1035 BEGIN_CS(4);
1036 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2);
1037 OUT_CS(start);
1038 OUT_CS(count);
1039 OUT_CS(val);
1040 END_CS;
1041 }
1042
1043 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1044
1045 void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state)
1046 {
1047 struct pipe_framebuffer_state *fb =
1048 (struct pipe_framebuffer_state*)r300->fb_state.state;
1049 struct r300_hyperz_state *z =
1050 (struct r300_hyperz_state*)r300->hyperz_state.state;
1051 struct r300_screen* r300screen = r300->screen;
1052 uint32_t stride, offset = 0, height, offset_shift;
1053 struct r300_texture* tex;
1054 int i;
1055
1056 tex = r300_texture(fb->zsbuf->texture);
1057
1058 offset = tex->hiz_mem[fb->zsbuf->level]->ofs;
1059 stride = tex->desc.stride_in_pixels[fb->zsbuf->level];
1060
1061 /* convert from pixels to 4x4 blocks */
1062 stride = ALIGN_DIVUP(stride, 4);
1063
1064 stride = ALIGN_DIVUP(stride, r300screen->caps.num_frag_pipes);
1065 /* there are 4 blocks per dwords */
1066 stride = ALIGN_DIVUP(stride, 4);
1067
1068 height = ALIGN_DIVUP(fb->zsbuf->height, 4);
1069
1070 offset_shift = 2;
1071 offset_shift += (r300screen->caps.num_frag_pipes / 2);
1072
1073 for (i = 0; i < height; i++) {
1074 offset = i * stride;
1075 offset <<= offset_shift;
1076 r300_emit_hiz_line_clear(r300, offset, stride, 0xffffffff);
1077 }
1078 z->current_func = -1;
1079
1080 /* Mark the current zbuffer's hiz ram as in use. */
1081 tex->hiz_in_use[fb->zsbuf->level] = TRUE;
1082 }
1083
1084 void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state)
1085 {
1086 struct pipe_framebuffer_state *fb =
1087 (struct pipe_framebuffer_state*)r300->fb_state.state;
1088 struct r300_screen* r300screen = r300->screen;
1089 uint32_t stride, offset = 0;
1090 struct r300_texture* tex;
1091 uint32_t i, height;
1092 int mult, offset_shift;
1093
1094 tex = r300_texture(fb->zsbuf->texture);
1095 stride = tex->desc.stride_in_pixels[fb->zsbuf->level];
1096
1097 offset = tex->zmask_mem[fb->zsbuf->level]->ofs;
1098
1099 if (r300->z_compression == RV350_Z_COMPRESS_88)
1100 mult = 8;
1101 else
1102 mult = 4;
1103
1104 height = ALIGN_DIVUP(fb->zsbuf->height, mult);
1105
1106 offset_shift = 4;
1107 offset_shift += (r300screen->caps.num_frag_pipes / 2);
1108 stride = ALIGN_DIVUP(stride, r300screen->caps.num_frag_pipes);
1109
1110 /* okay have width in pixels - divide by block width */
1111 stride = ALIGN_DIVUP(stride, mult);
1112 /* have width in blocks - divide by number of fragment pipes screen width */
1113 /* 16 blocks per dword */
1114 stride = ALIGN_DIVUP(stride, 16);
1115
1116 for (i = 0; i < height; i++) {
1117 offset = i * stride;
1118 offset <<= offset_shift;
1119 r300_emit_zmask_line_clear(r300, offset, stride, 0x0);//0xffffffff);
1120 }
1121
1122 /* Mark the current zbuffer's zmask as in use. */
1123 tex->zmask_in_use[fb->zsbuf->level] = TRUE;
1124 }
1125
1126 void r300_emit_ztop_state(struct r300_context* r300,
1127 unsigned size, void* state)
1128 {
1129 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1130 CS_LOCALS(r300);
1131
1132 BEGIN_CS(size);
1133 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1134 END_CS;
1135 }
1136
1137 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1138 {
1139 CS_LOCALS(r300);
1140
1141 BEGIN_CS(size);
1142 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1143 END_CS;
1144 }
1145
1146 boolean r300_emit_buffer_validate(struct r300_context *r300,
1147 boolean do_validate_vertex_buffers,
1148 struct pipe_resource *index_buffer)
1149 {
1150 struct pipe_framebuffer_state* fb =
1151 (struct pipe_framebuffer_state*)r300->fb_state.state;
1152 struct r300_textures_state *texstate =
1153 (struct r300_textures_state*)r300->textures_state.state;
1154 struct r300_texture* tex;
1155 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1156 struct pipe_vertex_element *velem = r300->velems->velem;
1157 struct pipe_resource *pbuf;
1158 unsigned i;
1159
1160 /* upload buffers first */
1161 if (r300->screen->caps.has_tcl && r300->any_user_vbs) {
1162 r300_upload_user_buffers(r300);
1163 r300->any_user_vbs = false;
1164 }
1165
1166 /* Clean out BOs. */
1167 r300->rws->cs_reset_buffers(r300->cs);
1168
1169 /* Color buffers... */
1170 for (i = 0; i < fb->nr_cbufs; i++) {
1171 tex = r300_texture(fb->cbufs[i]->texture);
1172 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1173 r300->rws->cs_add_buffer(r300->cs, tex->buffer, 0,
1174 r300_surface(fb->cbufs[i])->domain);
1175 }
1176 /* ...depth buffer... */
1177 if (fb->zsbuf) {
1178 tex = r300_texture(fb->zsbuf->texture);
1179 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1180 r300->rws->cs_add_buffer(r300->cs, tex->buffer, 0,
1181 r300_surface(fb->zsbuf)->domain);
1182 }
1183 /* ...textures... */
1184 for (i = 0; i < texstate->count; i++) {
1185 if (!(texstate->tx_enable & (1 << i))) {
1186 continue;
1187 }
1188
1189 tex = r300_texture(texstate->sampler_views[i]->base.texture);
1190 r300->rws->cs_add_buffer(r300->cs, tex->buffer, tex->domain, 0);
1191 }
1192 /* ...occlusion query buffer... */
1193 if (r300->query_current)
1194 r300->rws->cs_add_buffer(r300->cs, r300->query_current->buffer,
1195 0, r300->query_current->domain);
1196 /* ...vertex buffer for SWTCL path... */
1197 if (r300->vbo)
1198 r300->rws->cs_add_buffer(r300->cs, r300_buffer(r300->vbo)->buf,
1199 r300_buffer(r300->vbo)->domain, 0);
1200 /* ...vertex buffers for HWTCL path... */
1201 if (do_validate_vertex_buffers) {
1202 for (i = 0; i < r300->velems->count; i++) {
1203 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1204
1205 r300->rws->cs_add_buffer(r300->cs, r300_buffer(pbuf)->buf,
1206 r300_buffer(pbuf)->domain, 0);
1207 }
1208 }
1209 /* ...and index buffer for HWTCL path. */
1210 if (index_buffer)
1211 r300->rws->cs_add_buffer(r300->cs, r300_buffer(index_buffer)->buf,
1212 r300_buffer(index_buffer)->domain, 0);
1213
1214 if (!r300->rws->cs_validate(r300->cs)) {
1215 return FALSE;
1216 }
1217
1218 return TRUE;
1219 }
1220
1221 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1222 {
1223 struct r300_atom* atom;
1224 unsigned dwords = 0;
1225
1226 foreach(atom, &r300->atom_list) {
1227 if (atom->dirty) {
1228 dwords += atom->size;
1229 }
1230 }
1231
1232 /* let's reserve some more, just in case */
1233 dwords += 32;
1234
1235 return dwords;
1236 }
1237
1238 unsigned r300_get_num_cs_end_dwords(struct r300_context *r300)
1239 {
1240 unsigned dwords = 0;
1241
1242 /* Emitted in flush. */
1243 dwords += 26; /* emit_query_end */
1244 dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */
1245 if (r500_index_bias_supported(r300))
1246 dwords += 2;
1247
1248 return dwords;
1249 }
1250
1251 /* Emit all dirty state. */
1252 void r300_emit_dirty_state(struct r300_context* r300)
1253 {
1254 struct r300_atom* atom;
1255
1256 foreach(atom, &r300->atom_list) {
1257 if (atom->dirty) {
1258 atom->emit(r300, atom->size, atom->state);
1259 if (SCREEN_DBG_ON(r300->screen, DBG_STATS)) {
1260 atom->counter++;
1261 }
1262 atom->dirty = FALSE;
1263 }
1264 }
1265
1266 r300->dirty_hw++;
1267 }