src/gallium/drivers/r300/r300_emit.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2009 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 /* r300_emit: Functions for emitting state. */
  25
  26 #include "util/u_format.h"
  27 #include "util/u_math.h"
  28 #include "util/u_simple_list.h"
  29
  30 #include "r300_context.h"
  31 #include "r300_cs.h"
  32 #include "r300_emit.h"
  33 #include "r300_fs.h"
  34 #include "r300_screen.h"
  35 #include "r300_screen_buffer.h"
  36 #include "r300_vs.h"
  37
  38 void r300_emit_blend_state(struct r300_context* r300,
  39                            unsigned size, void* state)
  40 {
  41     struct r300_blend_state* blend = (struct r300_blend_state*)state;
  42     struct pipe_framebuffer_state* fb =
  43         (struct pipe_framebuffer_state*)r300->fb_state.state;
  44     CS_LOCALS(r300);
  45
  46     if (fb->nr_cbufs) {
  47         WRITE_CS_TABLE(blend->cb, size);
  48     } else {
  49         WRITE_CS_TABLE(blend->cb_no_readwrite, size);
  50     }
  51 }
  52
  53 void r300_emit_blend_color_state(struct r300_context* r300,
  54                                  unsigned size, void* state)
  55 {
  56     struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
  57     CS_LOCALS(r300);
  58
  59     WRITE_CS_TABLE(bc->cb, size);
  60 }
  61
  62 void r300_emit_clip_state(struct r300_context* r300,
  63                           unsigned size, void* state)
  64 {
  65     struct r300_clip_state* clip = (struct r300_clip_state*)state;
  66     CS_LOCALS(r300);
  67
  68     WRITE_CS_TABLE(clip->cb, size);
  69 }
  70
  71 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
  72 {
  73     struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
  74     struct pipe_framebuffer_state* fb =
  75         (struct pipe_framebuffer_state*)r300->fb_state.state;
  76     CS_LOCALS(r300);
  77
  78     if (fb->zsbuf) {
  79         WRITE_CS_TABLE(&dsa->cb_begin, size);
  80     } else {
  81         WRITE_CS_TABLE(dsa->cb_no_readwrite, size);
  82     }
  83 }
  84
  85 static const float * get_rc_constant_state(
  86     struct r300_context * r300,
  87     struct rc_constant * constant)
  88 {
  89     struct r300_textures_state* texstate = r300->textures_state.state;
  90     static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
  91     struct pipe_resource *tex;
  92
  93     assert(constant->Type == RC_CONSTANT_STATE);
  94
  95     switch (constant->u.State[0]) {
  96         /* Factor for converting rectangle coords to
  97          * normalized coords. Should only show up on non-r500. */
  98         case RC_STATE_R300_TEXRECT_FACTOR:
  99             tex = texstate->sampler_views[constant->u.State[1]]->base.texture;
 100             vec[0] = 1.0 / tex->width0;
 101             vec[1] = 1.0 / tex->height0;
 102             break;
 103
 104         case RC_STATE_R300_VIEWPORT_SCALE:
 105             vec[0] = r300->viewport.scale[0];
 106             vec[1] = r300->viewport.scale[1];
 107             vec[2] = r300->viewport.scale[2];
 108             break;
 109
 110         case RC_STATE_R300_VIEWPORT_OFFSET:
 111             vec[0] = r300->viewport.translate[0];
 112             vec[1] = r300->viewport.translate[1];
 113             vec[2] = r300->viewport.translate[2];
 114             break;
 115
 116         default:
 117             fprintf(stderr, "r300: Implementation error: "
 118                 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
 119     }
 120
 121     /* This should either be (0, 0, 0, 1), which should be a relatively safe
 122      * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
 123      * state factors. */
 124     return vec;
 125 }
 126
 127 /* Convert a normal single-precision float into the 7.16 format
 128  * used by the R300 fragment shader.
 129  */
 130 uint32_t pack_float24(float f)
 131 {
 132     union {
 133         float fl;
 134         uint32_t u;
 135     } u;
 136     float mantissa;
 137     int exponent;
 138     uint32_t float24 = 0;
 139
 140     if (f == 0.0)
 141         return 0;
 142
 143     u.fl = f;
 144
 145     mantissa = frexpf(f, &exponent);
 146
 147     /* Handle -ve */
 148     if (mantissa < 0) {
 149         float24 |= (1 << 23);
 150         mantissa = mantissa * -1.0;
 151     }
 152     /* Handle exponent, bias of 63 */
 153     exponent += 62;
 154     float24 |= (exponent << 16);
 155     /* Kill 7 LSB of mantissa */
 156     float24 |= (u.u & 0x7FFFFF) >> 7;
 157
 158     return float24;
 159 }
 160
 161 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
 162 {
 163     struct r300_fragment_shader *fs = r300_fs(r300);
 164     CS_LOCALS(r300);
 165
 166     WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
 167 }
 168
 169 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
 170 {
 171     struct r300_fragment_shader *fs = r300_fs(r300);
 172     struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
 173     unsigned count = fs->shader->externals_count * 4;
 174     CS_LOCALS(r300);
 175
 176     if (count == 0)
 177         return;
 178
 179     BEGIN_CS(size);
 180     OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count);
 181     OUT_CS_TABLE(buf->constants, count);
 182     END_CS;
 183 }
 184
 185 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
 186 {
 187     struct r300_fragment_shader *fs = r300_fs(r300);
 188     struct rc_constant_list *constants = &fs->shader->code.constants;
 189     unsigned i;
 190     unsigned count = fs->shader->rc_state_count;
 191     unsigned first = fs->shader->externals_count;
 192     unsigned end = constants->Count;
 193     uint32_t cdata[4];
 194     unsigned j;
 195     CS_LOCALS(r300);
 196
 197     if (count == 0)
 198         return;
 199
 200     BEGIN_CS(size);
 201     for(i = first; i < end; ++i) {
 202         if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
 203             const float *data =
 204                     get_rc_constant_state(r300, &constants->Constants[i]);
 205
 206             for (j = 0; j < 4; j++)
 207                 cdata[j] = pack_float24(data[j]);
 208
 209             OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
 210             OUT_CS_TABLE(cdata, 4);
 211         }
 212     }
 213     END_CS;
 214 }
 215
 216 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
 217 {
 218     struct r300_fragment_shader *fs = r300_fs(r300);
 219     CS_LOCALS(r300);
 220
 221     WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
 222 }
 223
 224 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
 225 {
 226     struct r300_fragment_shader *fs = r300_fs(r300);
 227     struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
 228     unsigned count = fs->shader->externals_count * 4;
 229     CS_LOCALS(r300);
 230
 231     if (count == 0)
 232         return;
 233
 234     BEGIN_CS(size);
 235     OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
 236     OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count);
 237     OUT_CS_TABLE(buf->constants, count);
 238     END_CS;
 239 }
 240
 241 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
 242 {
 243     struct r300_fragment_shader *fs = r300_fs(r300);
 244     struct rc_constant_list *constants = &fs->shader->code.constants;
 245     unsigned i;
 246     unsigned count = fs->shader->rc_state_count;
 247     unsigned first = fs->shader->externals_count;
 248     unsigned end = constants->Count;
 249     CS_LOCALS(r300);
 250
 251     if (count == 0)
 252         return;
 253
 254     BEGIN_CS(size);
 255     for(i = first; i < end; ++i) {
 256         if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
 257             const float *data =
 258                     get_rc_constant_state(r300, &constants->Constants[i]);
 259
 260             OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
 261                        R500_GA_US_VECTOR_INDEX_TYPE_CONST |
 262                        (i & R500_GA_US_VECTOR_INDEX_MASK));
 263             OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
 264             OUT_CS_TABLE(data, 4);
 265         }
 266     }
 267     END_CS;
 268 }
 269
 270 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
 271 {
 272     struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
 273     struct r300_surface* surf;
 274     unsigned i;
 275     CS_LOCALS(r300);
 276
 277     BEGIN_CS(size);
 278
 279     /* Set up scissors.
 280      * By writing to the SC registers, SC & US assert idle. */
 281     OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
 282     if (r300->screen->caps.is_r500) {
 283         OUT_CS(0);
 284         OUT_CS(((fb->width  - 1) << R300_SCISSORS_X_SHIFT) |
 285                ((fb->height - 1) << R300_SCISSORS_Y_SHIFT));
 286     } else {
 287         OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
 288                (1440 << R300_SCISSORS_Y_SHIFT));
 289         OUT_CS(((fb->width  + 1440-1) << R300_SCISSORS_X_SHIFT) |
 290                ((fb->height + 1440-1) << R300_SCISSORS_Y_SHIFT));
 291     }
 292
 293     /* Flush and free renderbuffer caches. */
 294     OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
 295         R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
 296         R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 297     OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
 298         R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
 299         R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
 300
 301     /* Wait until the GPU is idle.
 302      * This fixes random pixels sometimes appearing probably caused
 303      * by incomplete rendering. */
 304     OUT_CS_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
 305
 306     /* XXX unpipelined regs
 307     rb3d_aaresolve_ctl
 308     rb3d_aaresolve_offset
 309     rb3d_aaresolve_pitch
 310     gb_aa_config
 311     */
 312
 313     /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
 314      * what we usually want. */
 315     if (r300->screen->caps.is_r500) {
 316         OUT_CS_REG(R300_RB3D_CCTL,
 317             R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
 318     } else {
 319         OUT_CS_REG(R300_RB3D_CCTL, 0);
 320     }
 321
 322     /* Set up colorbuffers. */
 323     for (i = 0; i < fb->nr_cbufs; i++) {
 324         surf = r300_surface(fb->cbufs[i]);
 325
 326         OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
 327         OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain, 0);
 328
 329         OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
 330         OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain, 0);
 331     }
 332
 333     /* Set up a zbuffer. */
 334     if (fb->zsbuf) {
 335         surf = r300_surface(fb->zsbuf);
 336
 337         OUT_CS_REG(R300_ZB_FORMAT, surf->format);
 338         OUT_CS_REG(R300_ZB_BW_CNTL, 0);
 339
 340         OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
 341         OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain, 0);
 342
 343         OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
 344         OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain, 0);
 345
 346         OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0);
 347
 348         /* HiZ RAM. */
 349         if (r300->screen->caps.has_hiz) {
 350             OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
 351             OUT_CS_REG(R300_ZB_HIZ_PITCH, 0);
 352         }
 353
 354         /* Z Mask RAM. (compressed zbuffer) */
 355         OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
 356         OUT_CS_REG(R300_ZB_ZMASK_PITCH, 0);
 357     }
 358
 359     /* Colorbuffer format in the US block.
 360      * (must be written after unpipelined regs) */
 361     OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
 362     for (i = 0; i < fb->nr_cbufs; i++) {
 363         OUT_CS(r300_surface(fb->cbufs[i])->format);
 364     }
 365     for (; i < 4; i++) {
 366         OUT_CS(R300_US_OUT_FMT_UNUSED);
 367     }
 368     END_CS;
 369 }
 370
 371 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
 372 {
 373     struct r300_query *query = r300->query_current;
 374     CS_LOCALS(r300);
 375
 376     if (!query)
 377         return;
 378
 379     BEGIN_CS(size);
 380     if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
 381         OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 382     } else {
 383         OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 384     }
 385     OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
 386     END_CS;
 387     query->begin_emitted = TRUE;
 388     query->flushed = FALSE;
 389 }
 390
 391 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
 392                                            struct r300_query *query)
 393 {
 394     struct r300_capabilities* caps = &r300->screen->caps;
 395     struct r300_winsys_buffer *buf = r300->query_current->buffer;
 396     CS_LOCALS(r300);
 397
 398     assert(caps->num_frag_pipes);
 399
 400     BEGIN_CS(6 * caps->num_frag_pipes + 2);
 401     /* I'm not so sure I like this switch, but it's hard to be elegant
 402      * when there's so many special cases...
 403      *
 404      * So here's the basic idea. For each pipe, enable writes to it only,
 405      * then put out the relocation for ZPASS_ADDR, taking into account a
 406      * 4-byte offset for each pipe. RV380 and older are special; they have
 407      * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
 408      * so there's a chipset cap for that. */
 409     switch (caps->num_frag_pipes) {
 410         case 4:
 411             /* pipe 3 only */
 412             OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
 413             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 414             OUT_CS_RELOC(buf, (query->num_results + 3) * 4,
 415                     0, query->domain, 0);
 416         case 3:
 417             /* pipe 2 only */
 418             OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
 419             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 420             OUT_CS_RELOC(buf, (query->num_results + 2) * 4,
 421                     0, query->domain, 0);
 422         case 2:
 423             /* pipe 1 only */
 424             /* As mentioned above, accomodate RV380 and older. */
 425             OUT_CS_REG(R300_SU_REG_DEST,
 426                     1 << (caps->high_second_pipe ? 3 : 1));
 427             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 428             OUT_CS_RELOC(buf, (query->num_results + 1) * 4,
 429                     0, query->domain, 0);
 430         case 1:
 431             /* pipe 0 only */
 432             OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
 433             OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 434             OUT_CS_RELOC(buf, (query->num_results + 0) * 4,
 435                     0, query->domain, 0);
 436             break;
 437         default:
 438             fprintf(stderr, "r300: Implementation error: Chipset reports %d"
 439                     " pixel pipes!\n", caps->num_frag_pipes);
 440             abort();
 441     }
 442
 443     /* And, finally, reset it to normal... */
 444     OUT_CS_REG(R300_SU_REG_DEST, 0xF);
 445     END_CS;
 446 }
 447
 448 static void rv530_emit_query_end_single_z(struct r300_context *r300,
 449                                           struct r300_query *query)
 450 {
 451     struct r300_winsys_buffer *buf = r300->query_current->buffer;
 452     CS_LOCALS(r300);
 453
 454     BEGIN_CS(8);
 455     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 456     OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 457     OUT_CS_RELOC(buf, query->num_results * 4, 0, query->domain, 0);
 458     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 459     END_CS;
 460 }
 461
 462 static void rv530_emit_query_end_double_z(struct r300_context *r300,
 463                                           struct r300_query *query)
 464 {
 465     struct r300_winsys_buffer *buf = r300->query_current->buffer;
 466     CS_LOCALS(r300);
 467
 468     BEGIN_CS(14);
 469     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 470     OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 471     OUT_CS_RELOC(buf, (query->num_results + 0) * 4, 0, query->domain, 0);
 472     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 473     OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
 474     OUT_CS_RELOC(buf, (query->num_results + 1) * 4, 0, query->domain, 0);
 475     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 476     END_CS;
 477 }
 478
 479 void r300_emit_query_end(struct r300_context* r300)
 480 {
 481     struct r300_capabilities *caps = &r300->screen->caps;
 482     struct r300_query *query = r300->query_current;
 483
 484     if (!query)
 485         return;
 486
 487     if (query->begin_emitted == FALSE)
 488         return;
 489
 490     if (caps->family == CHIP_FAMILY_RV530) {
 491         if (caps->num_z_pipes == 2)
 492             rv530_emit_query_end_double_z(r300, query);
 493         else
 494             rv530_emit_query_end_single_z(r300, query);
 495     } else
 496         r300_emit_query_end_frag_pipes(r300, query);
 497
 498     query->begin_emitted = FALSE;
 499     query->num_results += query->num_pipes;
 500
 501     /* XXX grab all the results and reset the counter. */
 502     if (query->num_results >= query->buffer_size / 4 - 4) {
 503         query->num_results = (query->buffer_size / 4) / 2;
 504         fprintf(stderr, "r300: Rewinding OQBO...\n");
 505     }
 506 }
 507
 508 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
 509 {
 510     struct r300_rs_state* rs = state;
 511     struct pipe_framebuffer_state* fb = r300->fb_state.state;
 512     float scale, offset;
 513     unsigned mspos0, mspos1, aa_config;
 514     CS_LOCALS(r300);
 515
 516     BEGIN_CS(size);
 517     OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
 518
 519     /* Multisampling. Depends on framebuffer sample count. */
 520     if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
 521         if (fb->nr_cbufs && fb->cbufs[0]->texture->nr_samples > 1) {
 522             aa_config = R300_GB_AA_CONFIG_AA_ENABLE;
 523             /* Subsample placement. These may not be optimal. */
 524             switch (fb->cbufs[0]->texture->nr_samples) {
 525                 case 2:
 526                     aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2;
 527                     mspos0 = 0x33996633;
 528                     mspos1 = 0x6666663;
 529                     break;
 530                 case 3:
 531                     aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3;
 532                     mspos0 = 0x33936933;
 533                     mspos1 = 0x6666663;
 534                     break;
 535                 case 4:
 536                     aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4;
 537                     mspos0 = 0x33939933;
 538                     mspos1 = 0x3966663;
 539                     break;
 540                 case 6:
 541                     aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6;
 542                     mspos0 = 0x22a2aa22;
 543                     mspos1 = 0x2a65672;
 544                     break;
 545                 default:
 546                     debug_printf("r300: Bad number of multisamples!\n");
 547                     mspos0 = rs->multisample_position_0;
 548                     mspos1 = rs->multisample_position_1;
 549                     break;
 550             }
 551
 552             OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
 553             OUT_CS(mspos0);
 554             OUT_CS(mspos1);
 555
 556             OUT_CS_REG(R300_GB_AA_CONFIG, aa_config);
 557         } else {
 558             OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
 559             OUT_CS(rs->multisample_position_0);
 560             OUT_CS(rs->multisample_position_1);
 561
 562             OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
 563         }
 564     }
 565
 566     OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
 567     OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
 568     OUT_CS(rs->point_minmax);
 569     OUT_CS(rs->line_control);
 570
 571     if (rs->polygon_offset_enable) {
 572         scale = rs->depth_scale * 12;
 573         offset = rs->depth_offset;
 574
 575         switch (r300->zbuffer_bpp) {
 576             case 16:
 577                 offset *= 4;
 578                 break;
 579             case 24:
 580                 offset *= 2;
 581                 break;
 582         }
 583
 584         OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
 585         OUT_CS_32F(scale);
 586         OUT_CS_32F(offset);
 587         OUT_CS_32F(scale);
 588         OUT_CS_32F(offset);
 589     }
 590
 591     OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
 592     OUT_CS(rs->polygon_offset_enable);
 593     OUT_CS(rs->cull_mode);
 594     OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
 595     OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
 596     OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
 597     OUT_CS_REG(R300_SC_CLIP_RULE, rs->clip_rule);
 598     OUT_CS_REG(R300_GB_ENABLE, rs->stuffing_enable);
 599     OUT_CS_REG_SEQ(R300_GA_POINT_S0, 4);
 600     OUT_CS_32F(rs->point_texcoord_left);
 601     OUT_CS_32F(rs->point_texcoord_bottom);
 602     OUT_CS_32F(rs->point_texcoord_right);
 603     OUT_CS_32F(rs->point_texcoord_top);
 604     END_CS;
 605 }
 606
 607 void r300_emit_rs_block_state(struct r300_context* r300,
 608                               unsigned size, void* state)
 609 {
 610     struct r300_rs_block* rs = (struct r300_rs_block*)state;
 611     unsigned i;
 612     /* It's the same for both INST and IP tables */
 613     unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
 614     CS_LOCALS(r300);
 615
 616     if (SCREEN_DBG_ON(r300->screen, DBG_DRAW)) {
 617         r500_dump_rs_block(rs);
 618     }
 619
 620     DBG(r300, DBG_DRAW, "r300: RS emit:\n");
 621
 622     BEGIN_CS(size);
 623     OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
 624     OUT_CS(rs->vap_vtx_state_cntl);
 625     OUT_CS(rs->vap_vsm_vtx_assm);
 626     OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 627     OUT_CS(rs->vap_out_vtx_fmt[0]);
 628     OUT_CS(rs->vap_out_vtx_fmt[1]);
 629
 630     if (r300->screen->caps.is_r500) {
 631         OUT_CS_REG_SEQ(R500_RS_IP_0, count);
 632     } else {
 633         OUT_CS_REG_SEQ(R300_RS_IP_0, count);
 634     }
 635     OUT_CS_TABLE(rs->ip, count);
 636     for (i = 0; i < count; i++) {
 637         DBG(r300, DBG_DRAW, "    : ip %d: 0x%08x\n", i, rs->ip[i]);
 638     }
 639
 640     OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
 641     OUT_CS(rs->count);
 642     OUT_CS(rs->inst_count);
 643
 644     if (r300->screen->caps.is_r500) {
 645         OUT_CS_REG_SEQ(R500_RS_INST_0, count);
 646     } else {
 647         OUT_CS_REG_SEQ(R300_RS_INST_0, count);
 648     }
 649     OUT_CS_TABLE(rs->inst, count);
 650     for (i = 0; i < count; i++) {
 651         DBG(r300, DBG_DRAW, "    : inst %d: 0x%08x\n", i, rs->inst[i]);
 652     }
 653
 654     DBG(r300, DBG_DRAW, "    : count: 0x%08x inst_count: 0x%08x\n",
 655         rs->count, rs->inst_count);
 656
 657     END_CS;
 658 }
 659
 660 void r300_emit_scissor_state(struct r300_context* r300,
 661                              unsigned size, void* state)
 662 {
 663     struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
 664     CS_LOCALS(r300);
 665
 666     BEGIN_CS(size);
 667     OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
 668     if (r300->screen->caps.is_r500) {
 669         OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
 670                (scissor->miny << R300_CLIPRECT_Y_SHIFT));
 671         OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
 672                ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
 673     } else {
 674         OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
 675                ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
 676         OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
 677                ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
 678     }
 679     END_CS;
 680 }
 681
 682 void r300_emit_textures_state(struct r300_context *r300,
 683                               unsigned size, void *state)
 684 {
 685     struct r300_textures_state *allstate = (struct r300_textures_state*)state;
 686     struct r300_texture_sampler_state *texstate;
 687     struct r300_texture *tex;
 688     unsigned i;
 689     CS_LOCALS(r300);
 690
 691     BEGIN_CS(size);
 692     OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
 693
 694     for (i = 0; i < allstate->count; i++) {
 695         if ((1 << i) & allstate->tx_enable) {
 696             texstate = &allstate->regs[i];
 697             tex = r300_texture(allstate->sampler_views[i]->base.texture);
 698
 699             OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
 700             OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
 701             OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
 702                        texstate->border_color);
 703
 704             OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
 705             OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
 706             OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
 707
 708             OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 709             OUT_CS_TEX_RELOC(tex, texstate->format.tile_config, tex->domain,
 710                              0, 0);
 711         }
 712     }
 713     END_CS;
 714 }
 715
 716 void r300_emit_aos(struct r300_context* r300, int offset, boolean indexed)
 717 {
 718     struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
 719     struct pipe_vertex_element *velem = r300->velems->velem;
 720     struct r300_buffer *buf;
 721     int i;
 722     unsigned *hw_format_size = r300->velems->hw_format_size;
 723     unsigned size1, size2, aos_count = r300->velems->count;
 724     unsigned packet_size = (aos_count * 3 + 1) / 2;
 725     CS_LOCALS(r300);
 726
 727     BEGIN_CS(2 + packet_size + aos_count * 2);
 728     OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
 729     OUT_CS(aos_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
 730
 731     for (i = 0; i < aos_count - 1; i += 2) {
 732         vb1 = &vbuf[velem[i].vertex_buffer_index];
 733         vb2 = &vbuf[velem[i+1].vertex_buffer_index];
 734         size1 = hw_format_size[i];
 735         size2 = hw_format_size[i+1];
 736
 737         OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
 738                R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
 739         OUT_CS(vb1->buffer_offset + velem[i].src_offset   + offset * vb1->stride);
 740         OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
 741     }
 742
 743     if (aos_count & 1) {
 744         vb1 = &vbuf[velem[i].vertex_buffer_index];
 745         size1 = hw_format_size[i];
 746
 747         OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
 748         OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
 749     }
 750
 751     for (i = 0; i < aos_count; i++) {
 752         buf = r300_buffer(vbuf[velem[i].vertex_buffer_index].buffer);
 753         OUT_CS_BUF_RELOC_NO_OFFSET(&buf->b.b, buf->domain, 0, 0);
 754     }
 755     END_CS;
 756 }
 757
 758 void r300_emit_aos_swtcl(struct r300_context *r300, boolean indexed)
 759 {
 760     CS_LOCALS(r300);
 761
 762     DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
 763             "vertex size %d\n", r300->vbo,
 764             r300->vertex_info.size);
 765     /* Set the pointer to our vertex buffer. The emitted values are this:
 766      * PACKET3 [3D_LOAD_VBPNTR]
 767      * COUNT   [1]
 768      * FORMAT  [size | stride << 8]
 769      * OFFSET  [offset into BO]
 770      * VBPNTR  [relocated BO]
 771      */
 772     BEGIN_CS(7);
 773     OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
 774     OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
 775     OUT_CS(r300->vertex_info.size |
 776             (r300->vertex_info.size << 8));
 777     OUT_CS(r300->vbo_offset);
 778     OUT_CS_BUF_RELOC(r300->vbo, 0, r300_buffer(r300->vbo)->domain, 0, 0);
 779     END_CS;
 780 }
 781
 782 void r300_emit_vertex_stream_state(struct r300_context* r300,
 783                                    unsigned size, void* state)
 784 {
 785     struct r300_vertex_stream_state *streams =
 786         (struct r300_vertex_stream_state*)state;
 787     unsigned i;
 788     CS_LOCALS(r300);
 789
 790     DBG(r300, DBG_DRAW, "r300: PSC emit:\n");
 791
 792     BEGIN_CS(size);
 793     OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
 794     OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
 795     for (i = 0; i < streams->count; i++) {
 796         DBG(r300, DBG_DRAW, "    : prog_stream_cntl%d: 0x%08x\n", i,
 797                streams->vap_prog_stream_cntl[i]);
 798     }
 799     OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
 800     OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
 801     for (i = 0; i < streams->count; i++) {
 802         DBG(r300, DBG_DRAW, "    : prog_stream_cntl_ext%d: 0x%08x\n", i,
 803                streams->vap_prog_stream_cntl_ext[i]);
 804     }
 805     END_CS;
 806 }
 807
 808 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
 809 {
 810     CS_LOCALS(r300);
 811
 812     BEGIN_CS(size);
 813     OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
 814     END_CS;
 815 }
 816
 817 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
 818 {
 819     struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
 820     struct r300_vertex_program_code* code = &vs->code;
 821     struct r300_screen* r300screen = r300->screen;
 822     unsigned instruction_count = code->length / 4;
 823     unsigned i;
 824
 825     unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
 826     unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
 827     unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
 828     unsigned temp_count = MAX2(code->num_temporaries, 1);
 829
 830     unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
 831                                   vtx_mem_size / output_count, 10);
 832     unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
 833
 834     unsigned imm_first = vs->externals_count;
 835     unsigned imm_end = vs->code.constants.Count;
 836     unsigned imm_count = vs->immediates_count;
 837
 838     CS_LOCALS(r300);
 839
 840     BEGIN_CS(size);
 841     /* Amount of time to wait for vertex fetches in PVS */
 842     OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
 843
 844     OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
 845     OUT_CS_32F(1.0);
 846     OUT_CS_32F(1.0);
 847     OUT_CS_32F(1.0);
 848     OUT_CS_32F(1.0);
 849
 850     OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
 851
 852     /* R300_VAP_PVS_CODE_CNTL_0
 853      * R300_VAP_PVS_CONST_CNTL
 854      * R300_VAP_PVS_CODE_CNTL_1
 855      * See the r5xx docs for instructions on how to use these. */
 856     OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
 857     OUT_CS(R300_PVS_FIRST_INST(0) |
 858             R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
 859             R300_PVS_LAST_INST(instruction_count - 1));
 860     OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
 861     OUT_CS(instruction_count - 1);
 862
 863     OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
 864     OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
 865     OUT_CS_TABLE(code->body.d, code->length);
 866
 867     OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
 868             R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
 869             R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
 870             R300_PVS_VF_MAX_VTX_NUM(12) |
 871             (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
 872
 873     /* Emit immediates. */
 874     if (imm_count) {
 875         OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
 876                    (r300->screen->caps.is_r500 ?
 877                    R500_PVS_CONST_START : R300_PVS_CONST_START) +
 878                    imm_first);
 879         OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
 880         for (i = imm_first; i < imm_end; i++) {
 881             const float *data = vs->code.constants.Constants[i].u.Immediate;
 882             OUT_CS_TABLE(data, 4);
 883         }
 884     }
 885     END_CS;
 886 }
 887
 888 void r300_emit_vs_constants(struct r300_context* r300,
 889                             unsigned size, void *state)
 890 {
 891     unsigned count =
 892         ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
 893     struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
 894     CS_LOCALS(r300);
 895
 896     if (!count)
 897         return;
 898
 899     BEGIN_CS(size);
 900     OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
 901                (r300->screen->caps.is_r500 ?
 902                R500_PVS_CONST_START : R300_PVS_CONST_START));
 903     OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
 904     OUT_CS_TABLE(buf->constants, count * 4);
 905     END_CS;
 906 }
 907
 908 void r300_emit_viewport_state(struct r300_context* r300,
 909                               unsigned size, void* state)
 910 {
 911     struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
 912     CS_LOCALS(r300);
 913
 914     BEGIN_CS(size);
 915     OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
 916     OUT_CS_TABLE(&viewport->xscale, 6);
 917     OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
 918     END_CS;
 919 }
 920
 921 void r300_emit_ztop_state(struct r300_context* r300,
 922                           unsigned size, void* state)
 923 {
 924     struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
 925     CS_LOCALS(r300);
 926
 927     BEGIN_CS(size);
 928     OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
 929     END_CS;
 930 }
 931
 932 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
 933 {
 934     CS_LOCALS(r300);
 935
 936     BEGIN_CS(size);
 937     OUT_CS_REG(R300_TX_INVALTAGS, 0);
 938     END_CS;
 939 }
 940
 941 void r300_emit_buffer_validate(struct r300_context *r300,
 942                                boolean do_validate_vertex_buffers,
 943                                struct pipe_resource *index_buffer)
 944 {
 945     struct pipe_framebuffer_state* fb =
 946         (struct pipe_framebuffer_state*)r300->fb_state.state;
 947     struct r300_textures_state *texstate =
 948         (struct r300_textures_state*)r300->textures_state.state;
 949     struct r300_texture* tex;
 950     struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
 951     struct pipe_vertex_element *velem = r300->velems->velem;
 952     struct pipe_resource *pbuf;
 953     unsigned i;
 954     boolean invalid = FALSE;
 955
 956     /* upload buffers first */
 957     if (r300->screen->caps.has_tcl && r300->any_user_vbs) {
 958         r300_upload_user_buffers(r300);
 959         r300->any_user_vbs = false;
 960     }
 961
 962     /* Clean out BOs. */
 963     r300->rws->reset_bos(r300->rws);
 964
 965 validate:
 966     /* Color buffers... */
 967     for (i = 0; i < fb->nr_cbufs; i++) {
 968         tex = r300_texture(fb->cbufs[i]->texture);
 969         assert(tex && tex->buffer && "cbuf is marked, but NULL!");
 970         if (!r300_add_texture(r300->rws, tex, 0, tex->domain)) {
 971             r300->context.flush(&r300->context, 0, NULL);
 972             goto validate;
 973         }
 974     }
 975     /* ...depth buffer... */
 976     if (fb->zsbuf) {
 977         tex = r300_texture(fb->zsbuf->texture);
 978         assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
 979         if (!r300_add_texture(r300->rws, tex,
 980                               0, tex->domain)) {
 981             r300->context.flush(&r300->context, 0, NULL);
 982             goto validate;
 983         }
 984     }
 985     /* ...textures... */
 986     for (i = 0; i < texstate->count; i++) {
 987         if (!(texstate->tx_enable & (1 << i))) {
 988             continue;
 989         }
 990
 991         tex = r300_texture(texstate->sampler_views[i]->base.texture);
 992         if (!r300_add_texture(r300->rws, tex, tex->domain, 0)) {
 993             r300->context.flush(&r300->context, 0, NULL);
 994             goto validate;
 995         }
 996     }
 997     /* ...occlusion query buffer... */
 998     if (r300->query_current) {
 999         if (!r300->rws->add_buffer(r300->rws, r300->query_current->buffer,
1000                                    0, r300->query_current->domain)) {
1001             r300->context.flush(&r300->context, 0, NULL);
1002             goto validate;
1003         }
1004     }
1005     /* ...vertex buffer for SWTCL path... */
1006     if (r300->vbo) {
1007         if (!r300_add_buffer(r300->rws, r300->vbo,
1008                              r300_buffer(r300->vbo)->domain, 0)) {
1009             r300->context.flush(&r300->context, 0, NULL);
1010             goto validate;
1011         }
1012     }
1013     /* ...vertex buffers for HWTCL path... */
1014     if (do_validate_vertex_buffers) {
1015         for (i = 0; i < r300->velems->count; i++) {
1016             pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1017
1018             if (!r300_add_buffer(r300->rws, pbuf,
1019                                  r300_buffer(pbuf)->domain, 0)) {
1020                 r300->context.flush(&r300->context, 0, NULL);
1021                 goto validate;
1022             }
1023         }
1024     }
1025     /* ...and index buffer for HWTCL path. */
1026     if (index_buffer) {
1027         if (!r300_add_buffer(r300->rws, index_buffer,
1028                              r300_buffer(index_buffer)->domain, 0)) {
1029             r300->context.flush(&r300->context, 0, NULL);
1030             goto validate;
1031         }
1032     }
1033     if (!r300->rws->validate(r300->rws)) {
1034         r300->context.flush(&r300->context, 0, NULL);
1035         if (invalid) {
1036             /* Well, hell. */
1037             fprintf(stderr, "r300: Stuck in validation loop, gonna quit now.\n");
1038             abort();
1039         }
1040         invalid = TRUE;
1041         goto validate;
1042     }
1043 }
1044
1045 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1046 {
1047     struct r300_atom* atom;
1048     unsigned dwords = 0;
1049
1050     foreach(atom, &r300->atom_list) {
1051         if (atom->dirty) {
1052             dwords += atom->size;
1053         }
1054     }
1055
1056     /* let's reserve some more, just in case */
1057     dwords += 32;
1058
1059     return dwords;
1060 }
1061
1062 /* Emit all dirty state. */
1063 void r300_emit_dirty_state(struct r300_context* r300)
1064 {
1065     struct r300_atom* atom;
1066
1067     foreach(atom, &r300->atom_list) {
1068         if (atom->dirty) {
1069             atom->emit(r300, atom->size, atom->state);
1070             if (SCREEN_DBG_ON(r300->screen, DBG_STATS)) {
1071                 atom->counter++;
1072             }
1073             atom->dirty = FALSE;
1074         }
1075     }
1076
1077     r300->dirty_hw++;
1078 }