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r300g: put the emission of R300_US_OUT_FMT_UNUSED back
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_vs.h"
36
37 void r300_emit_blend_state(struct r300_context* r300, void* state)
38 {
39 struct r300_blend_state* blend = (struct r300_blend_state*)state;
40 struct pipe_framebuffer_state* fb =
41 (struct pipe_framebuffer_state*)r300->fb_state.state;
42 CS_LOCALS(r300);
43
44 BEGIN_CS(8);
45 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
46 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
47 if (fb->nr_cbufs) {
48 OUT_CS(blend->blend_control);
49 OUT_CS(blend->alpha_blend_control);
50 OUT_CS(blend->color_channel_mask);
51 } else {
52 OUT_CS(0);
53 OUT_CS(0);
54 OUT_CS(0);
55 /* XXX also disable fastfill here once it's supported */
56 }
57 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
58 END_CS;
59 }
60
61 void r300_emit_blend_color_state(struct r300_context* r300, void* state)
62 {
63 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
64 struct r300_screen* r300screen = r300_screen(r300->context.screen);
65 CS_LOCALS(r300);
66
67 if (r300screen->caps->is_r500) {
68 BEGIN_CS(3);
69 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
70 OUT_CS(bc->blend_color_red_alpha);
71 OUT_CS(bc->blend_color_green_blue);
72 END_CS;
73 } else {
74 BEGIN_CS(2);
75 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
76 END_CS;
77 }
78 }
79
80 void r300_emit_clip_state(struct r300_context* r300, void* state)
81 {
82 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
83 int i;
84 struct r300_screen* r300screen = r300_screen(r300->context.screen);
85 CS_LOCALS(r300);
86
87 if (r300screen->caps->has_tcl) {
88 BEGIN_CS(5 + (6 * 4));
89 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
90 (r300screen->caps->is_r500 ?
91 R500_PVS_UCP_START : R300_PVS_UCP_START));
92 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
93 for (i = 0; i < 6; i++) {
94 OUT_CS_32F(clip->ucp[i][0]);
95 OUT_CS_32F(clip->ucp[i][1]);
96 OUT_CS_32F(clip->ucp[i][2]);
97 OUT_CS_32F(clip->ucp[i][3]);
98 }
99 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
100 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
101 END_CS;
102 } else {
103 BEGIN_CS(2);
104 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
105 END_CS;
106 }
107
108 }
109
110 void r300_emit_dsa_state(struct r300_context* r300, void* state)
111 {
112 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
113 struct r300_screen* r300screen = r300_screen(r300->context.screen);
114 struct pipe_framebuffer_state* fb =
115 (struct pipe_framebuffer_state*)r300->fb_state.state;
116 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
117 CS_LOCALS(r300);
118
119 BEGIN_CS(r300screen->caps->is_r500 ? 8 : 6);
120 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
121 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
122
123 if (fb->zsbuf) {
124 OUT_CS(dsa->z_buffer_control);
125 OUT_CS(dsa->z_stencil_control);
126 } else {
127 OUT_CS(0);
128 OUT_CS(0);
129 }
130
131 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
132
133 if (r300screen->caps->is_r500) {
134 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
135 }
136 END_CS;
137 }
138
139 static const float * get_shader_constant(
140 struct r300_context * r300,
141 struct rc_constant * constant,
142 struct r300_constant_buffer * externals)
143 {
144 struct r300_viewport_state* viewport =
145 (struct r300_viewport_state*)r300->viewport_state.state;
146 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
147 struct pipe_texture *tex;
148
149 switch(constant->Type) {
150 case RC_CONSTANT_EXTERNAL:
151 return externals->constants[constant->u.External];
152
153 case RC_CONSTANT_IMMEDIATE:
154 return constant->u.Immediate;
155
156 case RC_CONSTANT_STATE:
157 switch (constant->u.State[0]) {
158 /* Factor for converting rectangle coords to
159 * normalized coords. Should only show up on non-r500. */
160 case RC_STATE_R300_TEXRECT_FACTOR:
161 tex = &r300->textures[constant->u.State[1]]->tex;
162 vec[0] = 1.0 / tex->width0;
163 vec[1] = 1.0 / tex->height0;
164 break;
165
166 /* Texture compare-fail value. Shouldn't ever show up, but if
167 * it does, we'll be ready. */
168 case RC_STATE_SHADOW_AMBIENT:
169 vec[3] = 0;
170 break;
171
172 case RC_STATE_R300_VIEWPORT_SCALE:
173 if (r300->tcl_bypass) {
174 vec[0] = 1;
175 vec[1] = 1;
176 vec[2] = 1;
177 } else {
178 vec[0] = viewport->xscale;
179 vec[1] = viewport->yscale;
180 vec[2] = viewport->zscale;
181 }
182 break;
183
184 case RC_STATE_R300_VIEWPORT_OFFSET:
185 if (!r300->tcl_bypass) {
186 vec[0] = viewport->xoffset;
187 vec[1] = viewport->yoffset;
188 vec[2] = viewport->zoffset;
189 }
190 break;
191
192 default:
193 debug_printf("r300: Implementation error: "
194 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
195 }
196 break;
197
198 default:
199 debug_printf("r300: Implementation error: "
200 "Unhandled constant type %d\n", constant->Type);
201 }
202
203 /* This should either be (0, 0, 0, 1), which should be a relatively safe
204 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
205 * state factors. */
206 return vec;
207 }
208
209 /* Convert a normal single-precision float into the 7.16 format
210 * used by the R300 fragment shader.
211 */
212 static uint32_t pack_float24(float f)
213 {
214 union {
215 float fl;
216 uint32_t u;
217 } u;
218 float mantissa;
219 int exponent;
220 uint32_t float24 = 0;
221
222 if (f == 0.0)
223 return 0;
224
225 u.fl = f;
226
227 mantissa = frexpf(f, &exponent);
228
229 /* Handle -ve */
230 if (mantissa < 0) {
231 float24 |= (1 << 23);
232 mantissa = mantissa * -1.0;
233 }
234 /* Handle exponent, bias of 63 */
235 exponent += 62;
236 float24 |= (exponent << 16);
237 /* Kill 7 LSB of mantissa */
238 float24 |= (u.u & 0x7FFFFF) >> 7;
239
240 return float24;
241 }
242
243 void r300_emit_fragment_program_code(struct r300_context* r300,
244 struct rX00_fragment_program_code* generic_code)
245 {
246 struct r300_fragment_program_code * code = &generic_code->code.r300;
247 int i;
248 CS_LOCALS(r300);
249
250 BEGIN_CS(15 +
251 code->alu.length * 4 +
252 (code->tex.length ? (1 + code->tex.length) : 0));
253
254 OUT_CS_REG(R300_US_CONFIG, code->config);
255 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
256 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
257
258 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
259 for(i = 0; i < 4; ++i)
260 OUT_CS(code->code_addr[i]);
261
262 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
263 for (i = 0; i < code->alu.length; i++)
264 OUT_CS(code->alu.inst[i].rgb_inst);
265
266 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
267 for (i = 0; i < code->alu.length; i++)
268 OUT_CS(code->alu.inst[i].rgb_addr);
269
270 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
271 for (i = 0; i < code->alu.length; i++)
272 OUT_CS(code->alu.inst[i].alpha_inst);
273
274 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
275 for (i = 0; i < code->alu.length; i++)
276 OUT_CS(code->alu.inst[i].alpha_addr);
277
278 if (code->tex.length) {
279 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
280 for(i = 0; i < code->tex.length; ++i)
281 OUT_CS(code->tex.inst[i]);
282 }
283
284 END_CS;
285 }
286
287 void r300_emit_fs_constant_buffer(struct r300_context* r300,
288 struct rc_constant_list* constants)
289 {
290 int i;
291 CS_LOCALS(r300);
292
293 if (constants->Count == 0)
294 return;
295
296 BEGIN_CS(constants->Count * 4 + 1);
297 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
298 for(i = 0; i < constants->Count; ++i) {
299 const float * data = get_shader_constant(r300,
300 &constants->Constants[i],
301 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
302 OUT_CS(pack_float24(data[0]));
303 OUT_CS(pack_float24(data[1]));
304 OUT_CS(pack_float24(data[2]));
305 OUT_CS(pack_float24(data[3]));
306 }
307 END_CS;
308 }
309
310 static void r300_emit_fragment_depth_config(struct r300_context* r300,
311 struct r300_fragment_shader* fs)
312 {
313 CS_LOCALS(r300);
314
315 BEGIN_CS(4);
316 if (r300_fragment_shader_writes_depth(fs)) {
317 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
318 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
319 } else {
320 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
321 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
322 }
323 END_CS;
324 }
325
326 void r500_emit_fragment_program_code(struct r300_context* r300,
327 struct rX00_fragment_program_code* generic_code)
328 {
329 struct r500_fragment_program_code * code = &generic_code->code.r500;
330 int i;
331 CS_LOCALS(r300);
332
333 BEGIN_CS(13 +
334 ((code->inst_end + 1) * 6));
335 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
336 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
337 OUT_CS_REG(R500_US_CODE_RANGE,
338 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
339 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
340 OUT_CS_REG(R500_US_CODE_ADDR,
341 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
342
343 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
344 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
345 for (i = 0; i <= code->inst_end; i++) {
346 OUT_CS(code->inst[i].inst0);
347 OUT_CS(code->inst[i].inst1);
348 OUT_CS(code->inst[i].inst2);
349 OUT_CS(code->inst[i].inst3);
350 OUT_CS(code->inst[i].inst4);
351 OUT_CS(code->inst[i].inst5);
352 }
353
354 END_CS;
355 }
356
357 void r500_emit_fs_constant_buffer(struct r300_context* r300,
358 struct rc_constant_list* constants)
359 {
360 int i;
361 CS_LOCALS(r300);
362
363 if (constants->Count == 0)
364 return;
365
366 BEGIN_CS(constants->Count * 4 + 3);
367 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
368 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
369 for (i = 0; i < constants->Count; i++) {
370 const float * data = get_shader_constant(r300,
371 &constants->Constants[i],
372 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
373 OUT_CS_32F(data[0]);
374 OUT_CS_32F(data[1]);
375 OUT_CS_32F(data[2]);
376 OUT_CS_32F(data[3]);
377 }
378 END_CS;
379 }
380
381 void r300_emit_fb_state(struct r300_context* r300, void* state)
382 {
383 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
384 struct r300_screen* r300screen = r300_screen(r300->context.screen);
385 struct r300_texture* tex;
386 struct pipe_surface* surf;
387 int i;
388 CS_LOCALS(r300);
389
390 BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
391 (fb->zsbuf ? 10 : 0) + 6);
392
393 /* Flush and free renderbuffer caches. */
394 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
395 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
396 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
397 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
398 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
399 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
400
401 /* Set the number of colorbuffers. */
402 if (fb->nr_cbufs > 1) {
403 if (r300screen->caps->is_r500) {
404 OUT_CS_REG(R300_RB3D_CCTL,
405 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
406 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
407 } else {
408 OUT_CS_REG(R300_RB3D_CCTL,
409 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
410 }
411 } else {
412 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
413 }
414
415 /* Set up colorbuffers. */
416 for (i = 0; i < fb->nr_cbufs; i++) {
417 surf = fb->cbufs[i];
418 tex = (struct r300_texture*)surf->texture;
419 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
420
421 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
422 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
423
424 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
425 OUT_CS_RELOC(tex->buffer, tex->fb_state.colorpitch[surf->level],
426 0, RADEON_GEM_DOMAIN_VRAM, 0);
427
428 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
429 }
430 for (; i < 4; i++) {
431 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
432 }
433
434 /* Set up a zbuffer. */
435 if (fb->zsbuf) {
436 surf = fb->zsbuf;
437 tex = (struct r300_texture*)surf->texture;
438 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
439
440 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
441 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
442
443 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
444
445 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
446 OUT_CS_RELOC(tex->buffer, tex->fb_state.depthpitch[surf->level],
447 0, RADEON_GEM_DOMAIN_VRAM, 0);
448 }
449
450 END_CS;
451 }
452
453 static void r300_emit_query_start(struct r300_context *r300)
454 {
455 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
456 struct r300_query *query = r300->query_current;
457 CS_LOCALS(r300);
458
459 if (!query)
460 return;
461
462 BEGIN_CS(4);
463 if (caps->family == CHIP_FAMILY_RV530) {
464 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
465 } else {
466 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
467 }
468 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
469 END_CS;
470 query->begin_emitted = TRUE;
471 }
472
473
474 static void r300_emit_query_finish(struct r300_context *r300,
475 struct r300_query *query)
476 {
477 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
478 CS_LOCALS(r300);
479
480 assert(caps->num_frag_pipes);
481
482 BEGIN_CS(6 * caps->num_frag_pipes + 2);
483 /* I'm not so sure I like this switch, but it's hard to be elegant
484 * when there's so many special cases...
485 *
486 * So here's the basic idea. For each pipe, enable writes to it only,
487 * then put out the relocation for ZPASS_ADDR, taking into account a
488 * 4-byte offset for each pipe. RV380 and older are special; they have
489 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
490 * so there's a chipset cap for that. */
491 switch (caps->num_frag_pipes) {
492 case 4:
493 /* pipe 3 only */
494 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
495 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
496 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
497 0, RADEON_GEM_DOMAIN_GTT, 0);
498 case 3:
499 /* pipe 2 only */
500 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
501 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
502 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
503 0, RADEON_GEM_DOMAIN_GTT, 0);
504 case 2:
505 /* pipe 1 only */
506 /* As mentioned above, accomodate RV380 and older. */
507 OUT_CS_REG(R300_SU_REG_DEST,
508 1 << (caps->high_second_pipe ? 3 : 1));
509 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
510 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
511 0, RADEON_GEM_DOMAIN_GTT, 0);
512 case 1:
513 /* pipe 0 only */
514 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
515 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
516 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
517 0, RADEON_GEM_DOMAIN_GTT, 0);
518 break;
519 default:
520 debug_printf("r300: Implementation error: Chipset reports %d"
521 " pixel pipes!\n", caps->num_frag_pipes);
522 assert(0);
523 }
524
525 /* And, finally, reset it to normal... */
526 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
527 END_CS;
528 }
529
530 static void rv530_emit_query_single(struct r300_context *r300,
531 struct r300_query *query)
532 {
533 CS_LOCALS(r300);
534
535 BEGIN_CS(8);
536 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
537 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
538 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
539 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
540 END_CS;
541 }
542
543 static void rv530_emit_query_double(struct r300_context *r300,
544 struct r300_query *query)
545 {
546 CS_LOCALS(r300);
547
548 BEGIN_CS(14);
549 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
550 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
551 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
552 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
553 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
554 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
555 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
556 END_CS;
557 }
558
559 void r300_emit_query_end(struct r300_context* r300)
560 {
561 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
562 struct r300_query *query = r300->query_current;
563
564 if (!query)
565 return;
566
567 if (query->begin_emitted == FALSE)
568 return;
569
570 if (caps->family == CHIP_FAMILY_RV530) {
571 if (caps->num_z_pipes == 2)
572 rv530_emit_query_double(r300, query);
573 else
574 rv530_emit_query_single(r300, query);
575 } else
576 r300_emit_query_finish(r300, query);
577 }
578
579 void r300_emit_rs_state(struct r300_context* r300, void* state)
580 {
581 struct r300_rs_state* rs = (struct r300_rs_state*)state;
582 float scale, offset;
583 CS_LOCALS(r300);
584
585 BEGIN_CS(18 + (rs->polygon_offset_enable ? 5 : 0));
586 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
587
588 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
589
590 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
591 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
592 OUT_CS(rs->point_minmax);
593 OUT_CS(rs->line_control);
594
595 if (rs->polygon_offset_enable) {
596 scale = rs->depth_scale * 12;
597 offset = rs->depth_offset;
598
599 switch (r300->zbuffer_bpp) {
600 case 16:
601 offset *= 4;
602 break;
603 case 24:
604 offset *= 2;
605 break;
606 }
607
608 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
609 OUT_CS_32F(scale);
610 OUT_CS_32F(offset);
611 OUT_CS_32F(scale);
612 OUT_CS_32F(offset);
613 }
614
615 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
616 OUT_CS(rs->polygon_offset_enable);
617 OUT_CS(rs->cull_mode);
618 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
619 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
620 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
621 END_CS;
622 }
623
624 void r300_emit_rs_block_state(struct r300_context* r300, void* state)
625 {
626 struct r300_rs_block* rs = (struct r300_rs_block*)state;
627 unsigned i;
628 struct r300_screen* r300screen = r300_screen(r300->context.screen);
629 /* It's the same for both INST and IP tables */
630 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
631 CS_LOCALS(r300);
632
633 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
634
635 BEGIN_CS(5 + count*2);
636 if (r300screen->caps->is_r500) {
637 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
638 } else {
639 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
640 }
641 for (i = 0; i < count; i++) {
642 OUT_CS(rs->ip[i]);
643 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
644 }
645
646 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
647 OUT_CS(rs->count);
648 OUT_CS(rs->inst_count);
649
650 if (r300screen->caps->is_r500) {
651 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
652 } else {
653 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
654 }
655 for (i = 0; i < count; i++) {
656 OUT_CS(rs->inst[i]);
657 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
658 }
659
660 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
661 rs->count, rs->inst_count);
662
663 END_CS;
664 }
665
666 void r300_emit_scissor_state(struct r300_context* r300, void* state)
667 {
668 unsigned minx, miny, maxx, maxy;
669 uint32_t top_left, bottom_right;
670 struct r300_screen* r300screen = r300_screen(r300->context.screen);
671 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
672 struct pipe_framebuffer_state* fb =
673 (struct pipe_framebuffer_state*)r300->fb_state.state;
674 CS_LOCALS(r300);
675
676 minx = miny = 0;
677 maxx = fb->width;
678 maxy = fb->height;
679
680 if (((struct r300_rs_state*)r300->rs_state.state)->rs.scissor) {
681 minx = MAX2(minx, scissor->minx);
682 miny = MAX2(miny, scissor->miny);
683 maxx = MIN2(maxx, scissor->maxx);
684 maxy = MIN2(maxy, scissor->maxy);
685 }
686
687 /* Special case for zero-area scissor.
688 *
689 * We can't allow the variables maxx and maxy to be zero because they are
690 * subtracted from later in the code, which would cause emitting ~0 and
691 * making the kernel checker angry.
692 *
693 * Let's consider we change maxx and maxy to 1, which is effectively
694 * a one-pixel area. We must then change minx and miny to a number which is
695 * greater than 1 to get the zero area back. */
696 if (!maxx || !maxy) {
697 minx = 2;
698 miny = 2;
699 maxx = 1;
700 maxy = 1;
701 }
702
703 if (r300screen->caps->is_r500) {
704 top_left =
705 (minx << R300_SCISSORS_X_SHIFT) |
706 (miny << R300_SCISSORS_Y_SHIFT);
707 bottom_right =
708 ((maxx - 1) << R300_SCISSORS_X_SHIFT) |
709 ((maxy - 1) << R300_SCISSORS_Y_SHIFT);
710 } else {
711 /* Offset of 1440 in non-R500 chipsets. */
712 top_left =
713 ((minx + 1440) << R300_SCISSORS_X_SHIFT) |
714 ((miny + 1440) << R300_SCISSORS_Y_SHIFT);
715 bottom_right =
716 (((maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
717 (((maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
718 }
719
720 BEGIN_CS(3);
721 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
722 OUT_CS(top_left);
723 OUT_CS(bottom_right);
724 END_CS;
725 }
726
727 void r300_emit_texture(struct r300_context* r300,
728 struct r300_sampler_state* sampler,
729 struct r300_texture* tex,
730 unsigned offset)
731 {
732 uint32_t filter0 = sampler->filter0;
733 uint32_t format0 = tex->state.format0;
734 unsigned min_level, max_level;
735 CS_LOCALS(r300);
736
737 /* to emulate 1D textures through 2D ones correctly */
738 if (tex->tex.target == PIPE_TEXTURE_1D) {
739 filter0 &= ~R300_TX_WRAP_T_MASK;
740 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
741 }
742
743 if (tex->is_npot) {
744 /* NPOT textures don't support mip filter, unfortunately.
745 * This prevents incorrect rendering. */
746 filter0 &= ~R300_TX_MIN_FILTER_MIP_MASK;
747 } else {
748 /* determine min/max levels */
749 /* the MAX_MIP level is the largest (finest) one */
750 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
751 min_level = MIN2(sampler->min_lod, max_level);
752 format0 |= R300_TX_NUM_LEVELS(max_level);
753 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
754 }
755
756 BEGIN_CS(16);
757 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
758 (offset << 28));
759 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
760 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
761
762 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
763 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
764 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
765 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
766 OUT_CS_RELOC(tex->buffer,
767 R300_TXO_MACRO_TILE(tex->macrotile) |
768 R300_TXO_MICRO_TILE(tex->microtile),
769 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
770 END_CS;
771 }
772
773 void r300_emit_aos(struct r300_context* r300, unsigned offset)
774 {
775 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
776 struct pipe_vertex_element *velem = r300->vertex_element;
777 int i;
778 unsigned size1, size2, aos_count = r300->vertex_element_count;
779 unsigned packet_size = (aos_count * 3 + 1) / 2;
780 CS_LOCALS(r300);
781
782 BEGIN_CS(2 + packet_size + aos_count * 2);
783 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
784 OUT_CS(aos_count);
785
786 for (i = 0; i < aos_count - 1; i += 2) {
787 vb1 = &vbuf[velem[i].vertex_buffer_index];
788 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
789 size1 = util_format_get_blocksize(velem[i].src_format);
790 size2 = util_format_get_blocksize(velem[i+1].src_format);
791
792 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
793 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
794 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
795 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
796 }
797
798 if (aos_count & 1) {
799 vb1 = &vbuf[velem[i].vertex_buffer_index];
800 size1 = util_format_get_blocksize(velem[i].src_format);
801
802 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
803 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
804 }
805
806 for (i = 0; i < aos_count; i++) {
807 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
808 RADEON_GEM_DOMAIN_GTT, 0, 0);
809 }
810 END_CS;
811 }
812
813 void r300_emit_vertex_format_state(struct r300_context* r300, void* state)
814 {
815 struct r300_vertex_info* vertex_info = (struct r300_vertex_info*)state;
816 unsigned i;
817 CS_LOCALS(r300);
818
819 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
820
821 BEGIN_CS(26);
822 OUT_CS_REG(R300_VAP_VTX_SIZE, vertex_info->vinfo.size);
823
824 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
825 OUT_CS(vertex_info->vinfo.hwfmt[0]);
826 OUT_CS(vertex_info->vinfo.hwfmt[1]);
827 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
828 OUT_CS(vertex_info->vinfo.hwfmt[2]);
829 OUT_CS(vertex_info->vinfo.hwfmt[3]);
830 for (i = 0; i < 4; i++) {
831 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
832 vertex_info->vinfo.hwfmt[i]);
833 }
834
835 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
836 for (i = 0; i < 8; i++) {
837 OUT_CS(vertex_info->vap_prog_stream_cntl[i]);
838 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
839 vertex_info->vap_prog_stream_cntl[i]);
840 }
841 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
842 for (i = 0; i < 8; i++) {
843 OUT_CS(vertex_info->vap_prog_stream_cntl_ext[i]);
844 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
845 vertex_info->vap_prog_stream_cntl_ext[i]);
846 }
847 END_CS;
848 }
849
850 static void r300_flush_pvs(struct r300_context* r300)
851 {
852 CS_LOCALS(r300);
853
854 BEGIN_CS(2);
855 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
856 END_CS;
857 }
858
859 void r300_emit_vs_state(struct r300_context* r300, void* state)
860 {
861 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
862 struct r300_vertex_program_code* code = &vs->code;
863 struct r300_screen* r300screen = r300_screen(r300->context.screen);
864 unsigned instruction_count = code->length / 4;
865 unsigned i;
866
867 unsigned vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
868 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
869 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
870 unsigned temp_count = MAX2(code->num_temporaries, 1);
871
872 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
873 vtx_mem_size / output_count, 10);
874 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
875
876 CS_LOCALS(r300);
877
878 if (!r300screen->caps->has_tcl) {
879 debug_printf("r300: Implementation error: emit_vertex_shader called,"
880 " but has_tcl is FALSE!\n");
881 return;
882 }
883
884 r300_flush_pvs(r300);
885
886 BEGIN_CS(9 + code->length);
887 /* R300_VAP_PVS_CODE_CNTL_0
888 * R300_VAP_PVS_CONST_CNTL
889 * R300_VAP_PVS_CODE_CNTL_1
890 * See the r5xx docs for instructions on how to use these. */
891 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
892 OUT_CS(R300_PVS_FIRST_INST(0) |
893 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
894 R300_PVS_LAST_INST(instruction_count - 1));
895 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
896 OUT_CS(instruction_count - 1);
897
898 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
899 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
900 for (i = 0; i < code->length; i++) {
901 OUT_CS(code->body.d[i]);
902 }
903
904 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
905 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
906 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
907 R300_PVS_VF_MAX_VTX_NUM(12) |
908 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
909 END_CS;
910 }
911
912 void r300_emit_vs_constant_buffer(struct r300_context* r300,
913 struct rc_constant_list* constants)
914 {
915 int i;
916 struct r300_screen* r300screen = r300_screen(r300->context.screen);
917 CS_LOCALS(r300);
918
919 if (!r300screen->caps->has_tcl) {
920 debug_printf("r300: Implementation error: emit_vertex_shader called,"
921 " but has_tcl is FALSE!\n");
922 return;
923 }
924
925 if (constants->Count == 0)
926 return;
927
928 BEGIN_CS(constants->Count * 4 + 3);
929 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
930 (r300screen->caps->is_r500 ?
931 R500_PVS_CONST_START : R300_PVS_CONST_START));
932 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
933 for (i = 0; i < constants->Count; i++) {
934 const float * data = get_shader_constant(r300,
935 &constants->Constants[i],
936 &r300->shader_constants[PIPE_SHADER_VERTEX]);
937 OUT_CS_32F(data[0]);
938 OUT_CS_32F(data[1]);
939 OUT_CS_32F(data[2]);
940 OUT_CS_32F(data[3]);
941 }
942 END_CS;
943 }
944
945 void r300_emit_viewport_state(struct r300_context* r300, void* state)
946 {
947 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
948 CS_LOCALS(r300);
949
950 if (r300->tcl_bypass) {
951 BEGIN_CS(2);
952 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
953 END_CS;
954 } else {
955 BEGIN_CS(9);
956 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
957 OUT_CS_32F(viewport->xscale);
958 OUT_CS_32F(viewport->xoffset);
959 OUT_CS_32F(viewport->yscale);
960 OUT_CS_32F(viewport->yoffset);
961 OUT_CS_32F(viewport->zscale);
962 OUT_CS_32F(viewport->zoffset);
963 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
964 END_CS;
965 }
966 }
967
968 void r300_emit_texture_count(struct r300_context* r300)
969 {
970 uint32_t tx_enable = 0;
971 int i;
972 CS_LOCALS(r300);
973
974 /* Notice that texture_count and sampler_count are just sizes
975 * of the respective arrays. We still have to check for the individual
976 * elements. */
977 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
978 if (r300->textures[i]) {
979 tx_enable |= 1 << i;
980 }
981 }
982
983 BEGIN_CS(2);
984 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
985 END_CS;
986
987 }
988
989 void r300_emit_ztop_state(struct r300_context* r300, void* state)
990 {
991 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
992 CS_LOCALS(r300);
993
994 BEGIN_CS(2);
995 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
996 END_CS;
997 }
998
999 void r300_flush_textures(struct r300_context* r300)
1000 {
1001 CS_LOCALS(r300);
1002
1003 BEGIN_CS(2);
1004 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1005 END_CS;
1006 }
1007
1008 void r300_emit_buffer_validate(struct r300_context *r300)
1009 {
1010 struct pipe_framebuffer_state* fb =
1011 (struct pipe_framebuffer_state*)r300->fb_state.state;
1012 struct r300_texture* tex;
1013 unsigned i;
1014 boolean invalid = FALSE;
1015
1016 /* Clean out BOs. */
1017 r300->winsys->reset_bos(r300->winsys);
1018
1019 validate:
1020 /* Color buffers... */
1021 for (i = 0; i < fb->nr_cbufs; i++) {
1022 tex = (struct r300_texture*)fb->cbufs[i]->texture;
1023 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1024 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1025 0, RADEON_GEM_DOMAIN_VRAM)) {
1026 r300->context.flush(&r300->context, 0, NULL);
1027 goto validate;
1028 }
1029 }
1030 /* ...depth buffer... */
1031 if (fb->zsbuf) {
1032 tex = (struct r300_texture*)fb->zsbuf->texture;
1033 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1034 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1035 0, RADEON_GEM_DOMAIN_VRAM)) {
1036 r300->context.flush(&r300->context, 0, NULL);
1037 goto validate;
1038 }
1039 }
1040 /* ...textures... */
1041 for (i = 0; i < r300->texture_count; i++) {
1042 tex = r300->textures[i];
1043 if (!tex)
1044 continue;
1045 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1046 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1047 r300->context.flush(&r300->context, 0, NULL);
1048 goto validate;
1049 }
1050 }
1051 /* ...occlusion query buffer... */
1052 if (r300->dirty_state & R300_NEW_QUERY) {
1053 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1054 0, RADEON_GEM_DOMAIN_GTT)) {
1055 r300->context.flush(&r300->context, 0, NULL);
1056 goto validate;
1057 }
1058 }
1059 /* ...and vertex buffer. */
1060 if (r300->vbo) {
1061 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1062 RADEON_GEM_DOMAIN_GTT, 0)) {
1063 r300->context.flush(&r300->context, 0, NULL);
1064 goto validate;
1065 }
1066 } else {
1067 /* debug_printf("No VBO while emitting dirty state!\n"); */
1068 }
1069 if (!r300->winsys->validate(r300->winsys)) {
1070 r300->context.flush(&r300->context, 0, NULL);
1071 if (invalid) {
1072 /* Well, hell. */
1073 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1074 exit(1);
1075 }
1076 invalid = TRUE;
1077 goto validate;
1078 }
1079 }
1080
1081 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1082 {
1083 struct r300_atom* atom;
1084 unsigned dwords = 0;
1085
1086 foreach(atom, &r300->atom_list) {
1087 if (atom->dirty || atom->always_dirty) {
1088 dwords += atom->size;
1089 }
1090 }
1091
1092 /* XXX This is the compensation for the non-atomized states. */
1093 dwords += 1024;
1094
1095 return dwords;
1096 }
1097
1098 /* Emit all dirty state. */
1099 void r300_emit_dirty_state(struct r300_context* r300)
1100 {
1101 struct r300_screen* r300screen = r300_screen(r300->context.screen);
1102 struct r300_atom* atom;
1103 unsigned i;
1104 int dirty_tex = 0;
1105
1106 if (r300->dirty_state & R300_NEW_QUERY) {
1107 r300_emit_query_start(r300);
1108 r300->dirty_state &= ~R300_NEW_QUERY;
1109 }
1110
1111 foreach(atom, &r300->atom_list) {
1112 if (atom->dirty || atom->always_dirty) {
1113 atom->emit(r300, atom->state);
1114 atom->dirty = FALSE;
1115 }
1116 }
1117
1118 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1119 r300_emit_fragment_depth_config(r300, r300->fs);
1120 if (r300screen->caps->is_r500) {
1121 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1122 } else {
1123 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1124 }
1125 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1126 }
1127
1128 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1129 if (r300screen->caps->is_r500) {
1130 r500_emit_fs_constant_buffer(r300,
1131 &r300->fs->shader->code.constants);
1132 } else {
1133 r300_emit_fs_constant_buffer(r300,
1134 &r300->fs->shader->code.constants);
1135 }
1136 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1137 }
1138
1139 /* Samplers and textures are tracked separately but emitted together. */
1140 if (r300->dirty_state &
1141 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1142 r300_emit_texture_count(r300);
1143
1144 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1145 if (r300->dirty_state &
1146 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1147 if (r300->textures[i]) {
1148 r300_emit_texture(r300,
1149 r300->sampler_states[i],
1150 r300->textures[i],
1151 i);
1152 dirty_tex |= r300->dirty_state & (R300_NEW_TEXTURE << i);
1153 }
1154 r300->dirty_state &=
1155 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1156 }
1157 }
1158 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1159 }
1160
1161 if (dirty_tex) {
1162 r300_flush_textures(r300);
1163 }
1164
1165 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS || r300->vs_state.dirty) {
1166 r300_flush_pvs(r300);
1167 }
1168
1169 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1170 struct r300_vertex_shader* vs = r300->vs_state.state;
1171 r300_emit_vs_constant_buffer(r300, &vs->code.constants);
1172 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1173 }
1174
1175 /* XXX
1176 assert(r300->dirty_state == 0);
1177 */
1178
1179 /* Finally, emit the VBO. */
1180 /* r300_emit_vertex_buffer(r300); */
1181
1182 r300->dirty_hw++;
1183 }