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Merge branch '7.8'
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
36 #include "r300_state_inlines.h"
37 #include "r300_vs.h"
38
39 void r300_emit_blend_state(struct r300_context* r300,
40 unsigned size, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 struct pipe_framebuffer_state* fb =
44 (struct pipe_framebuffer_state*)r300->fb_state.state;
45 CS_LOCALS(r300);
46
47 BEGIN_CS(size);
48 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
49 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
50 if (fb->nr_cbufs) {
51 OUT_CS(blend->blend_control);
52 OUT_CS(blend->alpha_blend_control);
53 OUT_CS(blend->color_channel_mask);
54 } else {
55 OUT_CS(0);
56 OUT_CS(0);
57 OUT_CS(0);
58 /* XXX also disable fastfill here once it's supported */
59 }
60 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
61 END_CS;
62 }
63
64 void r300_emit_blend_color_state(struct r300_context* r300,
65 unsigned size, void* state)
66 {
67 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
68 struct r300_screen* r300screen = r300_screen(r300->context.screen);
69 CS_LOCALS(r300);
70
71 if (r300screen->caps->is_r500) {
72 BEGIN_CS(size);
73 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
74 OUT_CS(bc->blend_color_red_alpha);
75 OUT_CS(bc->blend_color_green_blue);
76 END_CS;
77 } else {
78 BEGIN_CS(size);
79 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
80 END_CS;
81 }
82 }
83
84 void r300_emit_clip_state(struct r300_context* r300,
85 unsigned size, void* state)
86 {
87 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
88 int i;
89 struct r300_screen* r300screen = r300_screen(r300->context.screen);
90 CS_LOCALS(r300);
91
92 if (r300screen->caps->has_tcl) {
93 BEGIN_CS(size);
94 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
95 (r300screen->caps->is_r500 ?
96 R500_PVS_UCP_START : R300_PVS_UCP_START));
97 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
98 for (i = 0; i < 6; i++) {
99 OUT_CS_32F(clip->ucp[i][0]);
100 OUT_CS_32F(clip->ucp[i][1]);
101 OUT_CS_32F(clip->ucp[i][2]);
102 OUT_CS_32F(clip->ucp[i][3]);
103 }
104 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
105 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
106 END_CS;
107 } else {
108 BEGIN_CS(size);
109 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
110 END_CS;
111 }
112
113 }
114
115 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
116 {
117 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
118 struct r300_screen* r300screen = r300_screen(r300->context.screen);
119 struct pipe_framebuffer_state* fb =
120 (struct pipe_framebuffer_state*)r300->fb_state.state;
121 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
122 CS_LOCALS(r300);
123
124 BEGIN_CS(size);
125 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
126 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
127
128 if (fb->zsbuf) {
129 OUT_CS(dsa->z_buffer_control);
130 OUT_CS(dsa->z_stencil_control);
131 } else {
132 OUT_CS(0);
133 OUT_CS(0);
134 }
135
136 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
137
138 if (r300screen->caps->is_r500) {
139 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
140 }
141 END_CS;
142 }
143
144 static const float * get_shader_constant(
145 struct r300_context * r300,
146 struct rc_constant * constant,
147 struct r300_constant_buffer * externals)
148 {
149 struct r300_viewport_state* viewport = r300->viewport_state.state;
150 struct r300_textures_state* texstate = r300->textures_state.state;
151 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
152 struct pipe_texture *tex;
153
154 switch(constant->Type) {
155 case RC_CONSTANT_EXTERNAL:
156 return externals->constants[constant->u.External];
157
158 case RC_CONSTANT_IMMEDIATE:
159 return constant->u.Immediate;
160
161 case RC_CONSTANT_STATE:
162 switch (constant->u.State[0]) {
163 /* Factor for converting rectangle coords to
164 * normalized coords. Should only show up on non-r500. */
165 case RC_STATE_R300_TEXRECT_FACTOR:
166 tex = texstate->fragment_sampler_views[constant->u.State[1]]->texture;
167 vec[0] = 1.0 / tex->width0;
168 vec[1] = 1.0 / tex->height0;
169 break;
170
171 /* Texture compare-fail value. Shouldn't ever show up, but if
172 * it does, we'll be ready. */
173 case RC_STATE_SHADOW_AMBIENT:
174 vec[3] = 0;
175 break;
176
177 case RC_STATE_R300_VIEWPORT_SCALE:
178 vec[0] = viewport->xscale;
179 vec[1] = viewport->yscale;
180 vec[2] = viewport->zscale;
181 break;
182
183 case RC_STATE_R300_VIEWPORT_OFFSET:
184 vec[0] = viewport->xoffset;
185 vec[1] = viewport->yoffset;
186 vec[2] = viewport->zoffset;
187 break;
188
189 default:
190 debug_printf("r300: Implementation error: "
191 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
192 }
193 break;
194
195 default:
196 debug_printf("r300: Implementation error: "
197 "Unhandled constant type %d\n", constant->Type);
198 }
199
200 /* This should either be (0, 0, 0, 1), which should be a relatively safe
201 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
202 * state factors. */
203 return vec;
204 }
205
206 /* Convert a normal single-precision float into the 7.16 format
207 * used by the R300 fragment shader.
208 */
209 static uint32_t pack_float24(float f)
210 {
211 union {
212 float fl;
213 uint32_t u;
214 } u;
215 float mantissa;
216 int exponent;
217 uint32_t float24 = 0;
218
219 if (f == 0.0)
220 return 0;
221
222 u.fl = f;
223
224 mantissa = frexpf(f, &exponent);
225
226 /* Handle -ve */
227 if (mantissa < 0) {
228 float24 |= (1 << 23);
229 mantissa = mantissa * -1.0;
230 }
231 /* Handle exponent, bias of 63 */
232 exponent += 62;
233 float24 |= (exponent << 16);
234 /* Kill 7 LSB of mantissa */
235 float24 |= (u.u & 0x7FFFFF) >> 7;
236
237 return float24;
238 }
239
240 void r300_emit_fragment_program_code(struct r300_context* r300,
241 struct rX00_fragment_program_code* generic_code)
242 {
243 struct r300_fragment_program_code * code = &generic_code->code.r300;
244 int i;
245 CS_LOCALS(r300);
246
247 BEGIN_CS(15 +
248 code->alu.length * 4 +
249 (code->tex.length ? (1 + code->tex.length) : 0));
250
251 OUT_CS_REG(R300_US_CONFIG, code->config);
252 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
253 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
254
255 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
256 for(i = 0; i < 4; ++i)
257 OUT_CS(code->code_addr[i]);
258
259 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
260 for (i = 0; i < code->alu.length; i++)
261 OUT_CS(code->alu.inst[i].rgb_inst);
262
263 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
264 for (i = 0; i < code->alu.length; i++)
265 OUT_CS(code->alu.inst[i].rgb_addr);
266
267 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
268 for (i = 0; i < code->alu.length; i++)
269 OUT_CS(code->alu.inst[i].alpha_inst);
270
271 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
272 for (i = 0; i < code->alu.length; i++)
273 OUT_CS(code->alu.inst[i].alpha_addr);
274
275 if (code->tex.length) {
276 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
277 for(i = 0; i < code->tex.length; ++i)
278 OUT_CS(code->tex.inst[i]);
279 }
280
281 END_CS;
282 }
283
284 void r300_emit_fs_constant_buffer(struct r300_context* r300,
285 struct rc_constant_list* constants)
286 {
287 int i;
288 CS_LOCALS(r300);
289
290 if (constants->Count == 0)
291 return;
292
293 BEGIN_CS(constants->Count * 4 + 1);
294 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
295 for(i = 0; i < constants->Count; ++i) {
296 const float * data = get_shader_constant(r300,
297 &constants->Constants[i],
298 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
299 OUT_CS(pack_float24(data[0]));
300 OUT_CS(pack_float24(data[1]));
301 OUT_CS(pack_float24(data[2]));
302 OUT_CS(pack_float24(data[3]));
303 }
304 END_CS;
305 }
306
307 static void r300_emit_fragment_depth_config(struct r300_context* r300,
308 struct r300_fragment_shader* fs)
309 {
310 CS_LOCALS(r300);
311
312 BEGIN_CS(4);
313 if (r300_fragment_shader_writes_depth(fs)) {
314 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
315 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
316 } else {
317 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
318 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
319 }
320 END_CS;
321 }
322
323 void r500_emit_fragment_program_code(struct r300_context* r300,
324 struct rX00_fragment_program_code* generic_code)
325 {
326 struct r500_fragment_program_code * code = &generic_code->code.r500;
327 int i;
328 CS_LOCALS(r300);
329
330 BEGIN_CS(13 +
331 ((code->inst_end + 1) * 6));
332 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
333 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
334 OUT_CS_REG(R500_US_CODE_RANGE,
335 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
336 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
337 OUT_CS_REG(R500_US_CODE_ADDR,
338 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
339
340 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
341 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
342 for (i = 0; i <= code->inst_end; i++) {
343 OUT_CS(code->inst[i].inst0);
344 OUT_CS(code->inst[i].inst1);
345 OUT_CS(code->inst[i].inst2);
346 OUT_CS(code->inst[i].inst3);
347 OUT_CS(code->inst[i].inst4);
348 OUT_CS(code->inst[i].inst5);
349 }
350
351 END_CS;
352 }
353
354 void r500_emit_fs_constant_buffer(struct r300_context* r300,
355 struct rc_constant_list* constants)
356 {
357 int i;
358 CS_LOCALS(r300);
359
360 if (constants->Count == 0)
361 return;
362
363 BEGIN_CS(constants->Count * 4 + 3);
364 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
365 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
366 for (i = 0; i < constants->Count; i++) {
367 const float * data = get_shader_constant(r300,
368 &constants->Constants[i],
369 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
370 OUT_CS_32F(data[0]);
371 OUT_CS_32F(data[1]);
372 OUT_CS_32F(data[2]);
373 OUT_CS_32F(data[3]);
374 }
375 END_CS;
376 }
377
378 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
379 {
380 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
381 struct r300_screen* r300screen = r300_screen(r300->context.screen);
382 struct r300_texture* tex;
383 struct pipe_surface* surf;
384 int i;
385 CS_LOCALS(r300);
386
387 BEGIN_CS(size);
388
389 /* Flush and free renderbuffer caches. */
390 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
391 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
392 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
393 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
394 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
395 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
396
397 /* Set the number of colorbuffers. */
398 if (fb->nr_cbufs > 1) {
399 if (r300screen->caps->is_r500) {
400 OUT_CS_REG(R300_RB3D_CCTL,
401 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
402 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
403 } else {
404 OUT_CS_REG(R300_RB3D_CCTL,
405 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
406 }
407 } else {
408 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
409 }
410
411 /* Set up colorbuffers. */
412 for (i = 0; i < fb->nr_cbufs; i++) {
413 surf = fb->cbufs[i];
414 tex = (struct r300_texture*)surf->texture;
415 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
416
417 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
418 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
419
420 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
421 OUT_CS_TEX_RELOC(tex, tex->fb_state.colorpitch[surf->level],
422 0, RADEON_GEM_DOMAIN_VRAM, 0);
423
424 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
425 }
426 for (; i < 4; i++) {
427 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
428 }
429
430 /* Set up a zbuffer. */
431 if (fb->zsbuf) {
432 surf = fb->zsbuf;
433 tex = (struct r300_texture*)surf->texture;
434 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
435
436 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
437 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
438
439 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
440
441 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
442 OUT_CS_TEX_RELOC(tex, tex->fb_state.depthpitch[surf->level],
443 0, RADEON_GEM_DOMAIN_VRAM, 0);
444 }
445
446 OUT_CS_REG(R300_GA_POINT_MINMAX,
447 (MAX2(fb->width, fb->height) * 6) << R300_GA_POINT_MINMAX_MAX_SHIFT);
448 END_CS;
449 }
450
451 void r300_emit_query_start(struct r300_context *r300)
452 {
453 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
454 struct r300_query *query = r300->query_current;
455 CS_LOCALS(r300);
456
457 if (!query)
458 return;
459
460 BEGIN_CS(4);
461 if (caps->family == CHIP_FAMILY_RV530) {
462 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
463 } else {
464 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
465 }
466 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
467 END_CS;
468 query->begin_emitted = TRUE;
469 }
470
471
472 static void r300_emit_query_finish(struct r300_context *r300,
473 struct r300_query *query)
474 {
475 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
476 CS_LOCALS(r300);
477
478 assert(caps->num_frag_pipes);
479
480 BEGIN_CS(6 * caps->num_frag_pipes + 2);
481 /* I'm not so sure I like this switch, but it's hard to be elegant
482 * when there's so many special cases...
483 *
484 * So here's the basic idea. For each pipe, enable writes to it only,
485 * then put out the relocation for ZPASS_ADDR, taking into account a
486 * 4-byte offset for each pipe. RV380 and older are special; they have
487 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
488 * so there's a chipset cap for that. */
489 switch (caps->num_frag_pipes) {
490 case 4:
491 /* pipe 3 only */
492 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
493 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
494 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
495 0, RADEON_GEM_DOMAIN_GTT, 0);
496 case 3:
497 /* pipe 2 only */
498 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
499 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
500 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
501 0, RADEON_GEM_DOMAIN_GTT, 0);
502 case 2:
503 /* pipe 1 only */
504 /* As mentioned above, accomodate RV380 and older. */
505 OUT_CS_REG(R300_SU_REG_DEST,
506 1 << (caps->high_second_pipe ? 3 : 1));
507 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
508 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
509 0, RADEON_GEM_DOMAIN_GTT, 0);
510 case 1:
511 /* pipe 0 only */
512 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
513 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
514 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
515 0, RADEON_GEM_DOMAIN_GTT, 0);
516 break;
517 default:
518 debug_printf("r300: Implementation error: Chipset reports %d"
519 " pixel pipes!\n", caps->num_frag_pipes);
520 assert(0);
521 }
522
523 /* And, finally, reset it to normal... */
524 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
525 END_CS;
526 }
527
528 static void rv530_emit_query_single(struct r300_context *r300,
529 struct r300_query *query)
530 {
531 CS_LOCALS(r300);
532
533 BEGIN_CS(8);
534 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
535 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
536 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
537 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
538 END_CS;
539 }
540
541 static void rv530_emit_query_double(struct r300_context *r300,
542 struct r300_query *query)
543 {
544 CS_LOCALS(r300);
545
546 BEGIN_CS(14);
547 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
548 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
549 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
550 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
551 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
552 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
553 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
554 END_CS;
555 }
556
557 void r300_emit_query_end(struct r300_context* r300)
558 {
559 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
560 struct r300_query *query = r300->query_current;
561
562 if (!query)
563 return;
564
565 if (query->begin_emitted == FALSE)
566 return;
567
568 if (caps->family == CHIP_FAMILY_RV530) {
569 if (caps->num_z_pipes == 2)
570 rv530_emit_query_double(r300, query);
571 else
572 rv530_emit_query_single(r300, query);
573 } else
574 r300_emit_query_finish(r300, query);
575 }
576
577 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
578 {
579 struct r300_rs_state* rs = (struct r300_rs_state*)state;
580 float scale, offset;
581 CS_LOCALS(r300);
582
583 BEGIN_CS(size);
584 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
585
586 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
587
588 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
589 OUT_CS_REG(R300_GA_LINE_CNTL, rs->line_control);
590
591 if (rs->polygon_offset_enable) {
592 scale = rs->depth_scale * 12;
593 offset = rs->depth_offset;
594
595 switch (r300->zbuffer_bpp) {
596 case 16:
597 offset *= 4;
598 break;
599 case 24:
600 offset *= 2;
601 break;
602 }
603
604 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
605 OUT_CS_32F(scale);
606 OUT_CS_32F(offset);
607 OUT_CS_32F(scale);
608 OUT_CS_32F(offset);
609 }
610
611 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
612 OUT_CS(rs->polygon_offset_enable);
613 OUT_CS(rs->cull_mode);
614 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
615 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
616 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
617 OUT_CS_REG(R300_GB_ENABLE, rs->stuffing_enable);
618 OUT_CS_REG_SEQ(R300_GA_POINT_S0, 4);
619 OUT_CS_32F(rs->point_texcoord_left);
620 OUT_CS_32F(rs->point_texcoord_bottom);
621 OUT_CS_32F(rs->point_texcoord_right);
622 OUT_CS_32F(rs->point_texcoord_top);
623 END_CS;
624 }
625
626 void r300_emit_rs_block_state(struct r300_context* r300,
627 unsigned size, void* state)
628 {
629 struct r300_rs_block* rs = (struct r300_rs_block*)state;
630 unsigned i;
631 struct r300_screen* r300screen = r300_screen(r300->context.screen);
632 /* It's the same for both INST and IP tables */
633 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
634 CS_LOCALS(r300);
635
636 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
637
638 BEGIN_CS(size);
639 if (r300screen->caps->is_r500) {
640 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
641 } else {
642 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
643 }
644 for (i = 0; i < count; i++) {
645 OUT_CS(rs->ip[i]);
646 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
647 }
648
649 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
650 OUT_CS(rs->count);
651 OUT_CS(rs->inst_count);
652
653 if (r300screen->caps->is_r500) {
654 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
655 } else {
656 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
657 }
658 for (i = 0; i < count; i++) {
659 OUT_CS(rs->inst[i]);
660 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
661 }
662
663 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
664 rs->count, rs->inst_count);
665
666 END_CS;
667 }
668
669 void r300_emit_scissor_state(struct r300_context* r300,
670 unsigned size, void* state)
671 {
672 unsigned minx, miny, maxx, maxy;
673 uint32_t top_left, bottom_right;
674 struct r300_screen* r300screen = r300_screen(r300->context.screen);
675 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
676 struct pipe_framebuffer_state* fb =
677 (struct pipe_framebuffer_state*)r300->fb_state.state;
678 CS_LOCALS(r300);
679
680 minx = miny = 0;
681 maxx = fb->width;
682 maxy = fb->height;
683
684 if (r300->scissor_enabled) {
685 minx = MAX2(minx, scissor->minx);
686 miny = MAX2(miny, scissor->miny);
687 maxx = MIN2(maxx, scissor->maxx);
688 maxy = MIN2(maxy, scissor->maxy);
689 }
690
691 /* Special case for zero-area scissor.
692 *
693 * We can't allow the variables maxx and maxy to be zero because they are
694 * subtracted from later in the code, which would cause emitting ~0 and
695 * making the kernel checker angry.
696 *
697 * Let's consider we change maxx and maxy to 1, which is effectively
698 * a one-pixel area. We must then change minx and miny to a number which is
699 * greater than 1 to get the zero area back. */
700 if (!maxx || !maxy) {
701 minx = 2;
702 miny = 2;
703 maxx = 1;
704 maxy = 1;
705 }
706
707 if (r300screen->caps->is_r500) {
708 top_left =
709 (minx << R300_SCISSORS_X_SHIFT) |
710 (miny << R300_SCISSORS_Y_SHIFT);
711 bottom_right =
712 ((maxx - 1) << R300_SCISSORS_X_SHIFT) |
713 ((maxy - 1) << R300_SCISSORS_Y_SHIFT);
714 } else {
715 /* Offset of 1440 in non-R500 chipsets. */
716 top_left =
717 ((minx + 1440) << R300_SCISSORS_X_SHIFT) |
718 ((miny + 1440) << R300_SCISSORS_Y_SHIFT);
719 bottom_right =
720 (((maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
721 (((maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
722 }
723
724 BEGIN_CS(size);
725 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
726 OUT_CS(top_left);
727 OUT_CS(bottom_right);
728 END_CS;
729 }
730
731 void r300_emit_textures_state(struct r300_context *r300,
732 unsigned size, void *state)
733 {
734 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
735 struct r300_texture_sampler_state *texstate;
736 unsigned i;
737 CS_LOCALS(r300);
738
739 BEGIN_CS(size);
740 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
741
742 for (i = 0; i < allstate->count; i++) {
743 if ((1 << i) & allstate->tx_enable) {
744 texstate = &allstate->regs[i];
745
746 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter[0]);
747 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter[1]);
748 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
749 texstate->border_color);
750
751 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format[0]);
752 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format[1]);
753 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format[2]);
754
755 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
756 OUT_CS_TEX_RELOC((struct r300_texture *)allstate->fragment_sampler_views[i]->texture,
757 texstate->tile_config,
758 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
759 }
760 }
761 END_CS;
762 }
763
764 void r300_emit_aos(struct r300_context* r300, unsigned offset)
765 {
766 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
767 struct pipe_vertex_element *velem = r300->velems->velem;
768 int i;
769 unsigned size1, size2, aos_count = r300->velems->count;
770 unsigned packet_size = (aos_count * 3 + 1) / 2;
771 CS_LOCALS(r300);
772
773 BEGIN_CS(2 + packet_size + aos_count * 2);
774 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
775 OUT_CS(aos_count);
776
777 for (i = 0; i < aos_count - 1; i += 2) {
778 vb1 = &vbuf[velem[i].vertex_buffer_index];
779 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
780 size1 = util_format_get_blocksize(velem[i].src_format);
781 size2 = util_format_get_blocksize(velem[i+1].src_format);
782
783 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
784 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
785 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
786 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
787 }
788
789 if (aos_count & 1) {
790 vb1 = &vbuf[velem[i].vertex_buffer_index];
791 size1 = util_format_get_blocksize(velem[i].src_format);
792
793 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
794 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
795 }
796
797 for (i = 0; i < aos_count; i++) {
798 OUT_CS_BUF_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
799 RADEON_GEM_DOMAIN_GTT, 0, 0);
800 }
801 END_CS;
802 }
803
804 void r300_emit_vertex_buffer(struct r300_context* r300)
805 {
806 CS_LOCALS(r300);
807
808 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
809 "vertex size %d\n", r300->vbo,
810 r300->vertex_info.size);
811 /* Set the pointer to our vertex buffer. The emitted values are this:
812 * PACKET3 [3D_LOAD_VBPNTR]
813 * COUNT [1]
814 * FORMAT [size | stride << 8]
815 * OFFSET [offset into BO]
816 * VBPNTR [relocated BO]
817 */
818 BEGIN_CS(7);
819 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
820 OUT_CS(1);
821 OUT_CS(r300->vertex_info.size |
822 (r300->vertex_info.size << 8));
823 OUT_CS(r300->vbo_offset);
824 OUT_CS_BUF_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
825 END_CS;
826 }
827
828 void r300_emit_vertex_stream_state(struct r300_context* r300,
829 unsigned size, void* state)
830 {
831 struct r300_vertex_stream_state *streams =
832 (struct r300_vertex_stream_state*)state;
833 unsigned i;
834 CS_LOCALS(r300);
835
836 DBG(r300, DBG_DRAW, "r300: PSC emit:\n");
837
838 BEGIN_CS(size);
839 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
840 for (i = 0; i < streams->count; i++) {
841 OUT_CS(streams->vap_prog_stream_cntl[i]);
842 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
843 streams->vap_prog_stream_cntl[i]);
844 }
845 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
846 for (i = 0; i < streams->count; i++) {
847 OUT_CS(streams->vap_prog_stream_cntl_ext[i]);
848 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
849 streams->vap_prog_stream_cntl_ext[i]);
850 }
851 END_CS;
852 }
853
854 void r300_emit_vap_output_state(struct r300_context* r300,
855 unsigned size, void* state)
856 {
857 struct r300_vap_output_state *vap_out_state =
858 (struct r300_vap_output_state*)state;
859 CS_LOCALS(r300);
860
861 DBG(r300, DBG_DRAW, "r300: VAP emit:\n");
862
863 BEGIN_CS(size);
864 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
865 OUT_CS(vap_out_state->vap_vtx_state_cntl);
866 OUT_CS(vap_out_state->vap_vsm_vtx_assm);
867 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
868 OUT_CS(vap_out_state->vap_out_vtx_fmt[0]);
869 OUT_CS(vap_out_state->vap_out_vtx_fmt[1]);
870 END_CS;
871 }
872
873 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
874 {
875 CS_LOCALS(r300);
876
877 BEGIN_CS(size);
878 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
879 END_CS;
880 }
881
882 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
883 {
884 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
885 struct r300_vertex_program_code* code = &vs->code;
886 struct r300_screen* r300screen = r300_screen(r300->context.screen);
887 unsigned instruction_count = code->length / 4;
888 unsigned i;
889
890 unsigned vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
891 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
892 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
893 unsigned temp_count = MAX2(code->num_temporaries, 1);
894
895 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
896 vtx_mem_size / output_count, 10);
897 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
898
899 CS_LOCALS(r300);
900
901 BEGIN_CS(size);
902 /* R300_VAP_PVS_CODE_CNTL_0
903 * R300_VAP_PVS_CONST_CNTL
904 * R300_VAP_PVS_CODE_CNTL_1
905 * See the r5xx docs for instructions on how to use these. */
906 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
907 OUT_CS(R300_PVS_FIRST_INST(0) |
908 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
909 R300_PVS_LAST_INST(instruction_count - 1));
910 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
911 OUT_CS(instruction_count - 1);
912
913 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
914 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
915 for (i = 0; i < code->length; i++) {
916 OUT_CS(code->body.d[i]);
917 }
918
919 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
920 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
921 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
922 R300_PVS_VF_MAX_VTX_NUM(12) |
923 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
924 END_CS;
925 }
926
927 void r300_emit_vs_constant_buffer(struct r300_context* r300,
928 struct rc_constant_list* constants)
929 {
930 struct r300_screen* r300screen = r300_screen(r300->context.screen);
931 unsigned i;
932 CS_LOCALS(r300);
933
934 BEGIN_CS(constants->Count * 4 + 3);
935 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
936 (r300screen->caps->is_r500 ?
937 R500_PVS_CONST_START : R300_PVS_CONST_START));
938 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
939 for (i = 0; i < constants->Count; i++) {
940 const float *data = get_shader_constant(r300,
941 &constants->Constants[i],
942 &r300->shader_constants[PIPE_SHADER_VERTEX]);
943 OUT_CS_32F(data[0]);
944 OUT_CS_32F(data[1]);
945 OUT_CS_32F(data[2]);
946 OUT_CS_32F(data[3]);
947 }
948 END_CS;
949 }
950
951 void r300_emit_viewport_state(struct r300_context* r300,
952 unsigned size, void* state)
953 {
954 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
955 CS_LOCALS(r300);
956
957 BEGIN_CS(size);
958 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
959 OUT_CS_32F(viewport->xscale);
960 OUT_CS_32F(viewport->xoffset);
961 OUT_CS_32F(viewport->yscale);
962 OUT_CS_32F(viewport->yoffset);
963 OUT_CS_32F(viewport->zscale);
964 OUT_CS_32F(viewport->zoffset);
965 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
966 END_CS;
967 }
968
969 void r300_emit_ztop_state(struct r300_context* r300,
970 unsigned size, void* state)
971 {
972 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
973 CS_LOCALS(r300);
974
975 BEGIN_CS(size);
976 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
977 END_CS;
978 }
979
980 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
981 {
982 CS_LOCALS(r300);
983
984 BEGIN_CS(size);
985 OUT_CS_REG(R300_TX_INVALTAGS, 0);
986 END_CS;
987 }
988
989 void r300_emit_buffer_validate(struct r300_context *r300,
990 boolean do_validate_vertex_buffers,
991 struct pipe_buffer *index_buffer)
992 {
993 struct pipe_framebuffer_state* fb =
994 (struct pipe_framebuffer_state*)r300->fb_state.state;
995 struct r300_textures_state *texstate =
996 (struct r300_textures_state*)r300->textures_state.state;
997 struct r300_texture* tex;
998 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
999 struct pipe_vertex_element *velem = r300->velems->velem;
1000 struct pipe_buffer *pbuf;
1001 unsigned i;
1002 boolean invalid = FALSE;
1003
1004 /* upload buffers first */
1005 if (r300->any_user_vbs) {
1006 r300_upload_user_buffers(r300);
1007 r300->any_user_vbs = false;
1008 }
1009
1010 /* Clean out BOs. */
1011 r300->rws->reset_bos(r300->rws);
1012
1013 validate:
1014 /* Color buffers... */
1015 for (i = 0; i < fb->nr_cbufs; i++) {
1016 tex = (struct r300_texture*)fb->cbufs[i]->texture;
1017 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1018 if (!r300_add_texture(r300->rws, tex,
1019 0, RADEON_GEM_DOMAIN_VRAM)) {
1020 r300->context.flush(&r300->context, 0, NULL);
1021 goto validate;
1022 }
1023 }
1024 /* ...depth buffer... */
1025 if (fb->zsbuf) {
1026 tex = (struct r300_texture*)fb->zsbuf->texture;
1027 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1028 if (!r300_add_texture(r300->rws, tex,
1029 0, RADEON_GEM_DOMAIN_VRAM)) {
1030 r300->context.flush(&r300->context, 0, NULL);
1031 goto validate;
1032 }
1033 }
1034 /* ...textures... */
1035 for (i = 0; i < texstate->count; i++) {
1036 if (!(texstate->tx_enable & (1 << i))) {
1037 continue;
1038 }
1039
1040 tex = (struct r300_texture*)texstate->fragment_sampler_views[i]->texture;
1041 if (!r300_add_texture(r300->rws, tex,
1042 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1043 r300->context.flush(&r300->context, 0, NULL);
1044 goto validate;
1045 }
1046 }
1047 /* ...occlusion query buffer... */
1048 if (r300->dirty_state & R300_NEW_QUERY) {
1049 if (!r300_add_buffer(r300->rws, r300->oqbo,
1050 0, RADEON_GEM_DOMAIN_GTT)) {
1051 r300->context.flush(&r300->context, 0, NULL);
1052 goto validate;
1053 }
1054 }
1055 /* ...vertex buffer for SWTCL path... */
1056 if (r300->vbo) {
1057 if (!r300_add_buffer(r300->rws, r300->vbo,
1058 RADEON_GEM_DOMAIN_GTT, 0)) {
1059 r300->context.flush(&r300->context, 0, NULL);
1060 goto validate;
1061 }
1062 }
1063 /* ...vertex buffers for HWTCL path... */
1064 if (do_validate_vertex_buffers) {
1065 for (i = 0; i < r300->velems->count; i++) {
1066 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1067
1068 if (!r300_add_buffer(r300->rws, pbuf,
1069 RADEON_GEM_DOMAIN_GTT, 0)) {
1070 r300->context.flush(&r300->context, 0, NULL);
1071 goto validate;
1072 }
1073 }
1074 }
1075 /* ...and index buffer for HWTCL path. */
1076 if (index_buffer) {
1077 if (!r300_add_buffer(r300->rws, index_buffer,
1078 RADEON_GEM_DOMAIN_GTT, 0)) {
1079 r300->context.flush(&r300->context, 0, NULL);
1080 goto validate;
1081 }
1082 }
1083 if (!r300->rws->validate(r300->rws)) {
1084 r300->context.flush(&r300->context, 0, NULL);
1085 if (invalid) {
1086 /* Well, hell. */
1087 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1088 exit(1);
1089 }
1090 invalid = TRUE;
1091 goto validate;
1092 }
1093 }
1094
1095 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1096 {
1097 struct r300_atom* atom;
1098 unsigned dwords = 0;
1099
1100 foreach(atom, &r300->atom_list) {
1101 if (atom->dirty || atom->always_dirty) {
1102 dwords += atom->size;
1103 }
1104 }
1105
1106 /* XXX This is the compensation for the non-atomized states. */
1107 dwords += 1024;
1108
1109 return dwords;
1110 }
1111
1112 /* Emit all dirty state. */
1113 void r300_emit_dirty_state(struct r300_context* r300)
1114 {
1115 struct r300_screen* r300screen = r300_screen(r300->context.screen);
1116 struct r300_atom* atom;
1117
1118 if (r300->dirty_state & R300_NEW_QUERY) {
1119 r300_emit_query_start(r300);
1120 r300->dirty_state &= ~R300_NEW_QUERY;
1121 }
1122
1123 foreach(atom, &r300->atom_list) {
1124 if (atom->dirty || atom->always_dirty) {
1125 atom->emit(r300, atom->size, atom->state);
1126 atom->dirty = FALSE;
1127 }
1128 }
1129
1130 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1131 r300_emit_fragment_depth_config(r300, r300->fs);
1132 if (r300screen->caps->is_r500) {
1133 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1134 } else {
1135 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1136 }
1137 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1138 }
1139
1140 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1141 if (r300screen->caps->is_r500) {
1142 r500_emit_fs_constant_buffer(r300,
1143 &r300->fs->shader->code.constants);
1144 } else {
1145 r300_emit_fs_constant_buffer(r300,
1146 &r300->fs->shader->code.constants);
1147 }
1148 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1149 }
1150
1151 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1152 struct r300_vertex_shader* vs = r300->vs_state.state;
1153 if (vs->code.constants.Count) {
1154 r300_emit_vs_constant_buffer(r300, &vs->code.constants);
1155 }
1156 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1157 }
1158
1159 /* XXX
1160 assert(r300->dirty_state == 0);
1161 */
1162
1163 /* Emit the VBO for SWTCL. */
1164 if (!r300screen->caps->has_tcl) {
1165 r300_emit_vertex_buffer(r300);
1166 }
1167
1168 r300->dirty_hw++;
1169 }