2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
30 #include "r300_context.h"
33 #include "r300_emit.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
39 void r300_emit_blend_state(struct r300_context
* r300
,
40 unsigned size
, void* state
)
42 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
43 struct pipe_framebuffer_state
* fb
=
44 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
48 if (fb
->cbufs
[0]->format
== PIPE_FORMAT_R16G16B16A16_FLOAT
) {
49 WRITE_CS_TABLE(blend
->cb_noclamp
, size
);
51 unsigned swz
= r300_surface(fb
->cbufs
[0])->colormask_swizzle
;
52 WRITE_CS_TABLE(blend
->cb_clamp
[swz
], size
);
55 WRITE_CS_TABLE(blend
->cb_no_readwrite
, size
);
59 void r300_emit_blend_color_state(struct r300_context
* r300
,
60 unsigned size
, void* state
)
62 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
65 WRITE_CS_TABLE(bc
->cb
, size
);
68 void r300_emit_clip_state(struct r300_context
* r300
,
69 unsigned size
, void* state
)
71 struct r300_clip_state
* clip
= (struct r300_clip_state
*)state
;
74 WRITE_CS_TABLE(clip
->cb
, size
);
77 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
79 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
80 struct pipe_framebuffer_state
* fb
=
81 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
82 boolean is_r500
= r300
->screen
->caps
.is_r500
;
84 uint32_t alpha_func
= dsa
->alpha_function
;
86 /* Choose the alpha ref value between 8-bit (FG_ALPHA_FUNC.AM_VAL) and
87 * 16-bit (FG_ALPHA_VALUE). */
88 if (is_r500
&& (alpha_func
& R300_FG_ALPHA_FUNC_ENABLE
)) {
89 if (fb
->nr_cbufs
&& fb
->cbufs
[0]->format
== PIPE_FORMAT_R16G16B16A16_FLOAT
) {
90 alpha_func
|= R500_FG_ALPHA_FUNC_FP16_ENABLE
;
92 alpha_func
|= R500_FG_ALPHA_FUNC_8BIT
;
96 /* Setup alpha-to-coverage. */
97 if (r300
->alpha_to_coverage
&& r300
->msaa_enable
) {
98 /* Always set 3/6, it improves precision even for 2x and 4x MSAA. */
99 alpha_func
|= R300_FG_ALPHA_FUNC_MASK_ENABLE
|
100 R300_FG_ALPHA_FUNC_CFG_3_OF_6
;
104 OUT_CS_REG(R300_FG_ALPHA_FUNC
, alpha_func
);
105 OUT_CS_TABLE(fb
->zsbuf
? &dsa
->cb_begin
: dsa
->cb_zb_no_readwrite
, size
-2);
109 static void get_rc_constant_state(
111 struct r300_context
* r300
,
112 struct rc_constant
* constant
)
114 struct r300_textures_state
* texstate
= r300
->textures_state
.state
;
115 struct r300_resource
*tex
;
117 assert(constant
->Type
== RC_CONSTANT_STATE
);
119 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
120 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
123 switch (constant
->u
.State
[0]) {
124 /* Factor for converting rectangle coords to
125 * normalized coords. Should only show up on non-r500. */
126 case RC_STATE_R300_TEXRECT_FACTOR
:
127 tex
= r300_resource(texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
);
128 vec
[0] = 1.0 / tex
->tex
.width0
;
129 vec
[1] = 1.0 / tex
->tex
.height0
;
134 case RC_STATE_R300_TEXSCALE_FACTOR
:
135 tex
= r300_resource(texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
);
136 /* Add a small number to the texture size to work around rounding errors in hw. */
137 vec
[0] = tex
->b
.b
.width0
/ (tex
->tex
.width0
+ 0.001f
);
138 vec
[1] = tex
->b
.b
.height0
/ (tex
->tex
.height0
+ 0.001f
);
139 vec
[2] = tex
->b
.b
.depth0
/ (tex
->tex
.depth0
+ 0.001f
);
143 case RC_STATE_R300_VIEWPORT_SCALE
:
144 vec
[0] = r300
->viewport
.scale
[0];
145 vec
[1] = r300
->viewport
.scale
[1];
146 vec
[2] = r300
->viewport
.scale
[2];
150 case RC_STATE_R300_VIEWPORT_OFFSET
:
151 vec
[0] = r300
->viewport
.translate
[0];
152 vec
[1] = r300
->viewport
.translate
[1];
153 vec
[2] = r300
->viewport
.translate
[2];
158 fprintf(stderr
, "r300: Implementation error: "
159 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
167 /* Convert a normal single-precision float into the 7.16 format
168 * used by the R300 fragment shader.
170 uint32_t pack_float24(float f
)
178 uint32_t float24
= 0;
185 mantissa
= frexpf(f
, &exponent
);
189 float24
|= (1 << 23);
190 mantissa
= mantissa
* -1.0;
192 /* Handle exponent, bias of 63 */
194 float24
|= (exponent
<< 16);
195 /* Kill 7 LSB of mantissa */
196 float24
|= (u
.u
& 0x7FFFFF) >> 7;
201 void r300_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
203 struct r300_fragment_shader
*fs
= r300_fs(r300
);
206 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
209 void r300_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
211 struct r300_fragment_shader
*fs
= r300_fs(r300
);
212 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
213 unsigned count
= fs
->shader
->externals_count
;
221 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, count
* 4);
222 if (buf
->remap_table
){
223 for (i
= 0; i
< count
; i
++) {
224 float *data
= (float*)&buf
->ptr
[buf
->remap_table
[i
]*4];
225 for (j
= 0; j
< 4; j
++)
226 OUT_CS(pack_float24(data
[j
]));
229 for (i
= 0; i
< count
; i
++)
230 for (j
= 0; j
< 4; j
++)
231 OUT_CS(pack_float24(*(float*)&buf
->ptr
[i
*4+j
]));
237 void r300_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
239 struct r300_fragment_shader
*fs
= r300_fs(r300
);
240 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
242 unsigned count
= fs
->shader
->rc_state_count
;
243 unsigned first
= fs
->shader
->externals_count
;
244 unsigned end
= constants
->Count
;
252 for(i
= first
; i
< end
; ++i
) {
253 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
256 get_rc_constant_state(data
, r300
, &constants
->Constants
[i
]);
258 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
259 for (j
= 0; j
< 4; j
++)
260 OUT_CS(pack_float24(data
[j
]));
266 void r500_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
268 struct r300_fragment_shader
*fs
= r300_fs(r300
);
271 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
274 void r500_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
276 struct r300_fragment_shader
*fs
= r300_fs(r300
);
277 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
278 unsigned count
= fs
->shader
->externals_count
;
285 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
286 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, count
* 4);
287 if (buf
->remap_table
){
288 for (unsigned i
= 0; i
< count
; i
++) {
289 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
290 OUT_CS_TABLE(data
, 4);
293 OUT_CS_TABLE(buf
->ptr
, count
* 4);
298 void r500_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
300 struct r300_fragment_shader
*fs
= r300_fs(r300
);
301 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
303 unsigned count
= fs
->shader
->rc_state_count
;
304 unsigned first
= fs
->shader
->externals_count
;
305 unsigned end
= constants
->Count
;
312 for(i
= first
; i
< end
; ++i
) {
313 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
316 get_rc_constant_state(data
, r300
, &constants
->Constants
[i
]);
318 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
319 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
320 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
321 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
322 OUT_CS_TABLE(data
, 4);
328 void r300_emit_gpu_flush(struct r300_context
*r300
, unsigned size
, void *state
)
330 struct r300_gpu_flush
*gpuflush
= (struct r300_gpu_flush
*)state
;
331 struct pipe_framebuffer_state
* fb
=
332 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
333 uint32_t height
= fb
->height
;
334 uint32_t width
= fb
->width
;
337 if (r300
->cbzb_clear
) {
338 struct r300_surface
*surf
= r300_surface(fb
->cbufs
[0]);
340 height
= surf
->cbzb_height
;
341 width
= surf
->cbzb_width
;
344 DBG(r300
, DBG_SCISSOR
,
345 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
346 width
, height
, r300
->cbzb_clear
? "YES" : "NO");
351 * By writing to the SC registers, SC & US assert idle. */
352 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
353 if (r300
->screen
->caps
.is_r500
) {
355 OUT_CS(((width
- 1) << R300_SCISSORS_X_SHIFT
) |
356 ((height
- 1) << R300_SCISSORS_Y_SHIFT
));
358 OUT_CS((1440 << R300_SCISSORS_X_SHIFT
) |
359 (1440 << R300_SCISSORS_Y_SHIFT
));
360 OUT_CS(((width
+ 1440-1) << R300_SCISSORS_X_SHIFT
) |
361 ((height
+ 1440-1) << R300_SCISSORS_Y_SHIFT
));
364 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
365 OUT_CS_TABLE(gpuflush
->cb_flush_clean
, 6);
369 void r300_emit_aa_state(struct r300_context
*r300
, unsigned size
, void *state
)
371 struct r300_aa_state
*aa
= (struct r300_aa_state
*)state
;
375 OUT_CS_REG(R300_GB_AA_CONFIG
, aa
->aa_config
);
378 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET
, 3);
379 OUT_CS(aa
->dest
->offset
);
380 OUT_CS(aa
->dest
->pitch
& R300_RB3D_AARESOLVE_PITCH_MASK
);
381 OUT_CS(R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE
|
382 R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE
);
383 OUT_CS_RELOC(aa
->dest
);
385 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL
, 0);
391 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
393 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
394 struct r300_surface
* surf
;
396 uint32_t rb3d_cctl
= 0;
402 if (r300
->screen
->caps
.is_r500
) {
403 rb3d_cctl
= R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
;
405 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers. */
406 if (fb
->nr_cbufs
&& r300
->fb_multiwrite
) {
407 rb3d_cctl
|= R300_RB3D_CCTL_NUM_MULTIWRITES(fb
->nr_cbufs
);
409 if (r300
->cmask_in_use
) {
410 rb3d_cctl
|= R300_RB3D_CCTL_AA_COMPRESSION_ENABLE
|
411 R300_RB3D_CCTL_CMASK_ENABLE
;
414 OUT_CS_REG(R300_RB3D_CCTL
, rb3d_cctl
);
416 /* Set up colorbuffers. */
417 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
418 surf
= r300_surface(fb
->cbufs
[i
]);
420 OUT_CS_REG(R300_RB3D_COLOROFFSET0
+ (4 * i
), surf
->offset
);
423 OUT_CS_REG(R300_RB3D_COLORPITCH0
+ (4 * i
), surf
->pitch
);
426 if (r300
->cmask_in_use
&& i
== 0) {
427 OUT_CS_REG(R300_RB3D_CMASK_OFFSET0
, 0);
428 OUT_CS_REG(R300_RB3D_CMASK_PITCH0
, surf
->pitch_cmask
);
429 OUT_CS_REG(R300_RB3D_COLOR_CLEAR_VALUE
, r300
->color_clear_value
);
430 if (r300
->screen
->caps
.is_r500
&& r300
->screen
->info
.drm_minor
>= 29) {
431 OUT_CS_REG_SEQ(R500_RB3D_COLOR_CLEAR_VALUE_AR
, 2);
432 OUT_CS(r300
->color_clear_value_ar
);
433 OUT_CS(r300
->color_clear_value_gb
);
438 /* Set up the ZB part of the CBZB clear. */
439 if (r300
->cbzb_clear
) {
440 surf
= r300_surface(fb
->cbufs
[0]);
442 OUT_CS_REG(R300_ZB_FORMAT
, surf
->cbzb_format
);
444 OUT_CS_REG(R300_ZB_DEPTHOFFSET
, surf
->cbzb_midpoint_offset
);
447 OUT_CS_REG(R300_ZB_DEPTHPITCH
, surf
->cbzb_pitch
);
451 "CBZB clearing cbuf %08x %08x\n", surf
->cbzb_format
,
454 /* Set up a zbuffer. */
455 else if (fb
->zsbuf
) {
456 surf
= r300_surface(fb
->zsbuf
);
458 OUT_CS_REG(R300_ZB_FORMAT
, surf
->format
);
460 OUT_CS_REG(R300_ZB_DEPTHOFFSET
, surf
->offset
);
463 OUT_CS_REG(R300_ZB_DEPTHPITCH
, surf
->pitch
);
466 if (r300
->hyperz_enabled
) {
468 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, 0);
469 OUT_CS_REG(R300_ZB_HIZ_PITCH
, surf
->pitch_hiz
);
470 /* Z Mask RAM. (compressed zbuffer) */
471 OUT_CS_REG(R300_ZB_ZMASK_OFFSET
, 0);
472 OUT_CS_REG(R300_ZB_ZMASK_PITCH
, surf
->pitch_zmask
);
479 void r300_emit_hyperz_state(struct r300_context
*r300
,
480 unsigned size
, void *state
)
482 struct r300_hyperz_state
*z
= state
;
486 WRITE_CS_TABLE(&z
->cb_flush_begin
, size
);
488 WRITE_CS_TABLE(&z
->cb_begin
, size
- 2);
491 void r300_emit_hyperz_end(struct r300_context
*r300
)
493 struct r300_hyperz_state z
=
494 *(struct r300_hyperz_state
*)r300
->hyperz_state
.state
;
498 z
.zb_depthclearvalue
= 0;
499 z
.sc_hyperz
= R300_SC_HYPERZ_ADJ_2
;
500 z
.gb_z_peq_config
= 0;
502 r300_emit_hyperz_state(r300
, r300
->hyperz_state
.size
, &z
);
505 #define R300_NIBBLES(x0, y0, x1, y1, x2, y2, d0y, d0x) \
506 (((x0) & 0xf) | (((y0) & 0xf) << 4) | \
507 (((x1) & 0xf) << 8) | (((y1) & 0xf) << 12) | \
508 (((x2) & 0xf) << 16) | (((y2) & 0xf) << 20) | \
509 (((d0y) & 0xf) << 24) | (((d0x) & 0xf) << 28))
511 static unsigned r300_get_mspos(int index
, unsigned *p
)
513 unsigned reg
, i
, distx
, disty
, dist
;
516 /* MSPOS0 contains positions for samples 0,1,2 as (X,Y) pairs of nibbles,
517 * followed by a (Y,X) pair containing the minimum distance from the pixel
519 * X0, Y0, X1, Y1, X2, Y2, D0_Y, D0_X
521 * There is a quirk when setting D0_X. The value represents the distance
522 * from the left edge of the pixel quad to the first sample in subpixels.
523 * All values less than eight should use the actual value, but „7‟ should
524 * be used for the distance „8‟. The hardware will convert 7 into 8 internally.
527 for (i
= 0; i
< 12; i
+= 2) {
533 for (i
= 1; i
< 12; i
+= 2) {
541 reg
= R300_NIBBLES(p
[0], p
[1], p
[2], p
[3], p
[4], p
[5], disty
, distx
);
543 /* MSPOS1 contains positions for samples 3,4,5 as (X,Y) pairs of nibbles,
544 * followed by the minimum distance from the pixel edge (not sure if X or Y):
545 * X3, Y3, X4, Y4, X5, Y5, D1
548 for (i
= 0; i
< 12; i
++) {
553 reg
= R300_NIBBLES(p
[6], p
[7], p
[8], p
[9], p
[10], p
[11], dist
, 0);
558 void r300_emit_fb_state_pipelined(struct r300_context
*r300
,
559 unsigned size
, void *state
)
561 /* The sample coordinates are in the range [0,11], because
562 * GB_TILE_CONFIG.SUBPIXEL is set to the 1/12 subpixel precision.
564 * Some sample coordinates reach to neighboring pixels and should not be used.
567 * The unused samples must be set to the positions of other valid samples. */
568 static unsigned sample_locs_1x
[12] = {
569 6,6, 6,6, 6,6, 6,6, 6,6, 6,6
571 static unsigned sample_locs_2x
[12] = {
572 3,9, 9,3, 9,3, 9,3, 9,3, 9,3
574 static unsigned sample_locs_4x
[12] = {
575 4,4, 8,8, 2,10, 10,2, 10,2, 10,2
577 static unsigned sample_locs_6x
[12] = {
578 3,1, 7,3, 11,5, 1,7, 5,9, 9,10
581 struct pipe_framebuffer_state
* fb
=
582 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
583 unsigned i
, num_cbufs
= fb
->nr_cbufs
;
584 unsigned mspos0
, mspos1
;
587 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be
588 * marked as UNUSED in the US block. */
589 if (r300
->fb_multiwrite
) {
590 num_cbufs
= MIN2(num_cbufs
, 1);
595 /* Colorbuffer format in the US block.
596 * (must be written after unpipelined regs) */
597 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0
, 4);
598 for (i
= 0; i
< num_cbufs
; i
++) {
599 OUT_CS(r300_surface(fb
->cbufs
[i
])->format
);
602 OUT_CS(R300_US_OUT_FMT_C4_8
|
603 R300_C0_SEL_B
| R300_C1_SEL_G
|
604 R300_C2_SEL_R
| R300_C3_SEL_A
);
607 OUT_CS(R300_US_OUT_FMT_UNUSED
);
610 /* Set sample positions. It depends on the framebuffer sample count.
611 * These are pipelined regs and as such cannot be moved to the AA state.
613 switch (r300
->num_samples
) {
615 mspos0
= r300_get_mspos(0, sample_locs_1x
);
616 mspos1
= r300_get_mspos(1, sample_locs_1x
);
619 mspos0
= r300_get_mspos(0, sample_locs_2x
);
620 mspos1
= r300_get_mspos(1, sample_locs_2x
);
623 mspos0
= r300_get_mspos(0, sample_locs_4x
);
624 mspos1
= r300_get_mspos(1, sample_locs_4x
);
627 mspos0
= r300_get_mspos(0, sample_locs_6x
);
628 mspos1
= r300_get_mspos(1, sample_locs_6x
);
632 OUT_CS_REG_SEQ(R300_GB_MSPOS0
, 2);
638 void r300_emit_query_start(struct r300_context
*r300
, unsigned size
, void*state
)
640 struct r300_query
*query
= r300
->query_current
;
647 if (r300
->screen
->caps
.family
== CHIP_RV530
) {
648 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
650 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
652 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
654 query
->begin_emitted
= TRUE
;
657 static void r300_emit_query_end_frag_pipes(struct r300_context
*r300
,
658 struct r300_query
*query
)
660 struct r300_capabilities
* caps
= &r300
->screen
->caps
;
661 uint32_t gb_pipes
= r300
->screen
->info
.r300_num_gb_pipes
;
666 BEGIN_CS(6 * gb_pipes
+ 2);
667 /* I'm not so sure I like this switch, but it's hard to be elegant
668 * when there's so many special cases...
670 * So here's the basic idea. For each pipe, enable writes to it only,
671 * then put out the relocation for ZPASS_ADDR, taking into account a
672 * 4-byte offset for each pipe. RV380 and older are special; they have
673 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
674 * so there's a chipset cap for that. */
678 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
679 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 3) * 4);
680 OUT_CS_RELOC(r300
->query_current
);
683 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
684 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 2) * 4);
685 OUT_CS_RELOC(r300
->query_current
);
688 /* As mentioned above, accomodate RV380 and older. */
689 OUT_CS_REG(R300_SU_REG_DEST
,
690 1 << (caps
->high_second_pipe
? 3 : 1));
691 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 1) * 4);
692 OUT_CS_RELOC(r300
->query_current
);
695 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
696 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 0) * 4);
697 OUT_CS_RELOC(r300
->query_current
);
700 fprintf(stderr
, "r300: Implementation error: Chipset reports %d"
701 " pixel pipes!\n", gb_pipes
);
705 /* And, finally, reset it to normal... */
706 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
710 static void rv530_emit_query_end_single_z(struct r300_context
*r300
,
711 struct r300_query
*query
)
716 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
717 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, query
->num_results
* 4);
718 OUT_CS_RELOC(r300
->query_current
);
719 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
723 static void rv530_emit_query_end_double_z(struct r300_context
*r300
,
724 struct r300_query
*query
)
729 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
730 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 0) * 4);
731 OUT_CS_RELOC(r300
->query_current
);
732 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
733 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 1) * 4);
734 OUT_CS_RELOC(r300
->query_current
);
735 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
739 void r300_emit_query_end(struct r300_context
* r300
)
741 struct r300_capabilities
*caps
= &r300
->screen
->caps
;
742 struct r300_query
*query
= r300
->query_current
;
747 if (query
->begin_emitted
== FALSE
)
750 if (caps
->family
== CHIP_RV530
) {
751 if (r300
->screen
->info
.r300_num_z_pipes
== 2)
752 rv530_emit_query_end_double_z(r300
, query
);
754 rv530_emit_query_end_single_z(r300
, query
);
756 r300_emit_query_end_frag_pipes(r300
, query
);
758 query
->begin_emitted
= FALSE
;
759 query
->num_results
+= query
->num_pipes
;
761 /* XXX grab all the results and reset the counter. */
762 if (query
->num_results
>= query
->buf
->size
/ 4 - 4) {
763 query
->num_results
= (query
->buf
->size
/ 4) / 2;
764 fprintf(stderr
, "r300: Rewinding OQBO...\n");
768 void r300_emit_invariant_state(struct r300_context
*r300
,
769 unsigned size
, void *state
)
772 WRITE_CS_TABLE(state
, size
);
775 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
777 struct r300_rs_state
* rs
= state
;
781 OUT_CS_TABLE(rs
->cb_main
, RS_STATE_MAIN_SIZE
);
782 if (rs
->polygon_offset_enable
) {
783 if (r300
->zbuffer_bpp
== 16) {
784 OUT_CS_TABLE(rs
->cb_poly_offset_zb16
, 5);
786 OUT_CS_TABLE(rs
->cb_poly_offset_zb24
, 5);
792 void r300_emit_rs_block_state(struct r300_context
* r300
,
793 unsigned size
, void* state
)
795 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
797 /* It's the same for both INST and IP tables */
798 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
801 if (DBG_ON(r300
, DBG_RS_BLOCK
)) {
802 r500_dump_rs_block(rs
);
804 fprintf(stderr
, "r300: RS emit:\n");
806 for (i
= 0; i
< count
; i
++)
807 fprintf(stderr
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
809 for (i
= 0; i
< count
; i
++)
810 fprintf(stderr
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
812 fprintf(stderr
, " : count: 0x%08x inst_count: 0x%08x\n",
813 rs
->count
, rs
->inst_count
);
817 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
818 OUT_CS(rs
->vap_vtx_state_cntl
);
819 OUT_CS(rs
->vap_vsm_vtx_assm
);
820 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
821 OUT_CS(rs
->vap_out_vtx_fmt
[0]);
822 OUT_CS(rs
->vap_out_vtx_fmt
[1]);
823 OUT_CS_REG_SEQ(R300_GB_ENABLE
, 1);
824 OUT_CS(rs
->gb_enable
);
826 if (r300
->screen
->caps
.is_r500
) {
827 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
829 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
831 OUT_CS_TABLE(rs
->ip
, count
);
833 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
835 OUT_CS(rs
->inst_count
);
837 if (r300
->screen
->caps
.is_r500
) {
838 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
840 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
842 OUT_CS_TABLE(rs
->inst
, count
);
846 void r300_emit_sample_mask(struct r300_context
*r300
,
847 unsigned size
, void *state
)
849 unsigned mask
= (*(unsigned*)state
) & ((1 << 6)-1);
853 OUT_CS_REG(R300_SC_SCREENDOOR
,
854 mask
| (mask
<< 6) | (mask
<< 12) | (mask
<< 18));
858 void r300_emit_scissor_state(struct r300_context
* r300
,
859 unsigned size
, void* state
)
861 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
865 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0
, 2);
866 if (r300
->screen
->caps
.is_r500
) {
867 OUT_CS((scissor
->minx
<< R300_CLIPRECT_X_SHIFT
) |
868 (scissor
->miny
<< R300_CLIPRECT_Y_SHIFT
));
869 OUT_CS(((scissor
->maxx
- 1) << R300_CLIPRECT_X_SHIFT
) |
870 ((scissor
->maxy
- 1) << R300_CLIPRECT_Y_SHIFT
));
872 OUT_CS(((scissor
->minx
+ 1440) << R300_CLIPRECT_X_SHIFT
) |
873 ((scissor
->miny
+ 1440) << R300_CLIPRECT_Y_SHIFT
));
874 OUT_CS(((scissor
->maxx
+ 1440-1) << R300_CLIPRECT_X_SHIFT
) |
875 ((scissor
->maxy
+ 1440-1) << R300_CLIPRECT_Y_SHIFT
));
880 void r300_emit_textures_state(struct r300_context
*r300
,
881 unsigned size
, void *state
)
883 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
884 struct r300_texture_sampler_state
*texstate
;
885 struct r300_resource
*tex
;
887 boolean has_us_format
= r300
->screen
->caps
.has_us_format
;
891 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
893 for (i
= 0; i
< allstate
->count
; i
++) {
894 if ((1 << i
) & allstate
->tx_enable
) {
895 texstate
= &allstate
->regs
[i
];
896 tex
= r300_resource(allstate
->sampler_views
[i
]->base
.texture
);
898 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter0
);
899 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter1
);
900 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
901 texstate
->border_color
);
903 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
.format0
);
904 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
.format1
);
905 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
.format2
);
907 OUT_CS_REG(R300_TX_OFFSET_0
+ (i
* 4), texstate
->format
.tile_config
);
911 OUT_CS_REG(R500_US_FORMAT0_0
+ (i
* 4),
912 texstate
->format
.us_format0
);
919 void r300_emit_vertex_arrays(struct r300_context
* r300
, int offset
,
920 boolean indexed
, int instance_id
)
922 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
923 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
924 struct r300_resource
*buf
;
926 unsigned vertex_array_count
= r300
->velems
->count
;
927 unsigned packet_size
= (vertex_array_count
* 3 + 1) / 2;
928 struct pipe_vertex_buffer
*vb1
, *vb2
;
929 unsigned *hw_format_size
= r300
->velems
->format_size
;
930 unsigned size1
, size2
, offset1
, offset2
, stride1
, stride2
;
933 BEGIN_CS(2 + packet_size
+ vertex_array_count
* 2);
934 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
935 OUT_CS(vertex_array_count
| (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
937 if (instance_id
== -1) {
938 /* Non-instanced arrays. This ignores instance_divisor and instance_id. */
939 for (i
= 0; i
< vertex_array_count
- 1; i
+= 2) {
940 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
941 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
942 size1
= hw_format_size
[i
];
943 size2
= hw_format_size
[i
+1];
945 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
946 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
947 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
948 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
951 if (vertex_array_count
& 1) {
952 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
953 size1
= hw_format_size
[i
];
955 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
956 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
959 for (i
= 0; i
< vertex_array_count
; i
++) {
960 buf
= r300_resource(vbuf
[velem
[i
].vertex_buffer_index
].buffer
);
964 /* Instanced arrays. */
965 for (i
= 0; i
< vertex_array_count
- 1; i
+= 2) {
966 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
967 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
968 size1
= hw_format_size
[i
];
969 size2
= hw_format_size
[i
+1];
971 if (velem
[i
].instance_divisor
) {
973 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+
974 (instance_id
/ velem
[i
].instance_divisor
) * vb1
->stride
;
976 stride1
= vb1
->stride
;
977 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
;
979 if (velem
[i
+1].instance_divisor
) {
981 offset2
= vb2
->buffer_offset
+ velem
[i
+1].src_offset
+
982 (instance_id
/ velem
[i
+1].instance_divisor
) * vb2
->stride
;
984 stride2
= vb2
->stride
;
985 offset2
= vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
;
988 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(stride1
) |
989 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(stride2
));
994 if (vertex_array_count
& 1) {
995 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
996 size1
= hw_format_size
[i
];
998 if (velem
[i
].instance_divisor
) {
1000 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+
1001 (instance_id
/ velem
[i
].instance_divisor
) * vb1
->stride
;
1003 stride1
= vb1
->stride
;
1004 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
;
1007 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(stride1
));
1011 for (i
= 0; i
< vertex_array_count
; i
++) {
1012 buf
= r300_resource(vbuf
[velem
[i
].vertex_buffer_index
].buffer
);
1019 void r300_emit_vertex_arrays_swtcl(struct r300_context
*r300
, boolean indexed
)
1023 DBG(r300
, DBG_SWTCL
, "r300: Preparing vertex buffer %p for render, "
1024 "vertex size %d\n", r300
->vbo
,
1025 r300
->vertex_info
.size
);
1026 /* Set the pointer to our vertex buffer. The emitted values are this:
1027 * PACKET3 [3D_LOAD_VBPNTR]
1029 * FORMAT [size | stride << 8]
1030 * OFFSET [offset into BO]
1031 * VBPNTR [relocated BO]
1034 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
1035 OUT_CS(1 | (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
1036 OUT_CS(r300
->vertex_info
.size
|
1037 (r300
->vertex_info
.size
<< 8));
1038 OUT_CS(r300
->draw_vbo_offset
);
1041 assert(r300
->vbo_cs
);
1042 cs_winsys
->cs_write_reloc(cs_copy
, r300
->vbo_cs
);
1047 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
1048 unsigned size
, void* state
)
1050 struct r300_vertex_stream_state
*streams
=
1051 (struct r300_vertex_stream_state
*)state
;
1055 if (DBG_ON(r300
, DBG_PSC
)) {
1056 fprintf(stderr
, "r300: PSC emit:\n");
1058 for (i
= 0; i
< streams
->count
; i
++) {
1059 fprintf(stderr
, " : prog_stream_cntl%d: 0x%08x\n", i
,
1060 streams
->vap_prog_stream_cntl
[i
]);
1063 for (i
= 0; i
< streams
->count
; i
++) {
1064 fprintf(stderr
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
1065 streams
->vap_prog_stream_cntl_ext
[i
]);
1070 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
1071 OUT_CS_TABLE(streams
->vap_prog_stream_cntl
, streams
->count
);
1072 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
1073 OUT_CS_TABLE(streams
->vap_prog_stream_cntl_ext
, streams
->count
);
1077 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
1082 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
1086 void r300_emit_vap_invariant_state(struct r300_context
*r300
,
1087 unsigned size
, void *state
)
1090 WRITE_CS_TABLE(state
, size
);
1093 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
1095 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
1096 struct r300_vertex_program_code
* code
= &vs
->code
;
1097 struct r300_screen
* r300screen
= r300
->screen
;
1098 unsigned instruction_count
= code
->length
/ 4;
1100 unsigned vtx_mem_size
= r300screen
->caps
.is_r500
? 128 : 72;
1101 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
1102 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
1103 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
1105 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
1106 vtx_mem_size
/ output_count
, 10);
1107 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 5);
1113 /* R300_VAP_PVS_CODE_CNTL_0
1114 * R300_VAP_PVS_CONST_CNTL
1115 * R300_VAP_PVS_CODE_CNTL_1
1116 * See the r5xx docs for instructions on how to use these. */
1117 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0
, R300_PVS_FIRST_INST(0) |
1118 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
1119 R300_PVS_LAST_INST(instruction_count
- 1));
1120 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1
, instruction_count
- 1);
1122 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
1123 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
1124 OUT_CS_TABLE(code
->body
.d
, code
->length
);
1126 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
1127 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
1128 R300_PVS_NUM_FPUS(r300screen
->caps
.num_vert_fpus
) |
1129 R300_PVS_VF_MAX_VTX_NUM(12) |
1130 (r300screen
->caps
.is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
1132 /* Emit flow control instructions. Even if there are no fc instructions,
1133 * we still need to write the registers to make sure they are cleared. */
1134 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC
, code
->fc_ops
);
1135 if (r300screen
->caps
.is_r500
) {
1136 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0
, R300_VS_MAX_FC_OPS
* 2);
1137 OUT_CS_TABLE(code
->fc_op_addrs
.r500
, R300_VS_MAX_FC_OPS
* 2);
1139 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0
, R300_VS_MAX_FC_OPS
);
1140 OUT_CS_TABLE(code
->fc_op_addrs
.r300
, R300_VS_MAX_FC_OPS
);
1142 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
, R300_VS_MAX_FC_OPS
);
1143 OUT_CS_TABLE(code
->fc_loop_index
, R300_VS_MAX_FC_OPS
);
1148 void r300_emit_vs_constants(struct r300_context
* r300
,
1149 unsigned size
, void *state
)
1152 ((struct r300_vertex_shader
*)r300
->vs_state
.state
)->externals_count
;
1153 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
1154 struct r300_vertex_shader
*vs
= (struct r300_vertex_shader
*)r300
->vs_state
.state
;
1156 int imm_first
= vs
->externals_count
;
1157 int imm_end
= vs
->code
.constants
.Count
;
1158 int imm_count
= vs
->immediates_count
;
1162 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL
,
1163 R300_PVS_CONST_BASE_OFFSET(buf
->buffer_base
) |
1164 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end
- 1, 0)));
1165 if (vs
->externals_count
) {
1166 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1167 (r300
->screen
->caps
.is_r500
?
1168 R500_PVS_CONST_START
: R300_PVS_CONST_START
) + buf
->buffer_base
);
1169 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, count
* 4);
1170 if (buf
->remap_table
){
1171 for (i
= 0; i
< count
; i
++) {
1172 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
1173 OUT_CS_TABLE(data
, 4);
1176 OUT_CS_TABLE(buf
->ptr
, count
* 4);
1180 /* Emit immediates. */
1182 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1183 (r300
->screen
->caps
.is_r500
?
1184 R500_PVS_CONST_START
: R300_PVS_CONST_START
) +
1185 buf
->buffer_base
+ imm_first
);
1186 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, imm_count
* 4);
1187 for (i
= imm_first
; i
< imm_end
; i
++) {
1188 const float *data
= vs
->code
.constants
.Constants
[i
].u
.Immediate
;
1189 OUT_CS_TABLE(data
, 4);
1195 void r300_emit_viewport_state(struct r300_context
* r300
,
1196 unsigned size
, void* state
)
1198 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
1202 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
1203 OUT_CS_TABLE(&viewport
->xscale
, 6);
1204 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
1208 void r300_emit_hiz_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1210 struct pipe_framebuffer_state
*fb
=
1211 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1212 struct r300_resource
* tex
;
1215 tex
= r300_resource(fb
->zsbuf
->texture
);
1218 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ
, 2);
1220 OUT_CS(tex
->tex
.hiz_dwords
[fb
->zsbuf
->u
.tex
.level
]);
1221 OUT_CS(r300
->hiz_clear_value
);
1224 /* Mark the current zbuffer's hiz ram as in use. */
1225 r300
->hiz_in_use
= TRUE
;
1226 r300
->hiz_func
= HIZ_FUNC_NONE
;
1227 r300_mark_atom_dirty(r300
, &r300
->hyperz_state
);
1230 void r300_emit_zmask_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1232 struct pipe_framebuffer_state
*fb
=
1233 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1234 struct r300_resource
*tex
;
1237 tex
= r300_resource(fb
->zsbuf
->texture
);
1240 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK
, 2);
1242 OUT_CS(tex
->tex
.zmask_dwords
[fb
->zsbuf
->u
.tex
.level
]);
1246 /* Mark the current zbuffer's zmask as in use. */
1247 r300
->zmask_in_use
= TRUE
;
1248 r300_mark_atom_dirty(r300
, &r300
->hyperz_state
);
1251 void r300_emit_cmask_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1253 struct pipe_framebuffer_state
*fb
=
1254 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1255 struct r300_resource
*tex
;
1258 tex
= r300_resource(fb
->cbufs
[0]->texture
);
1261 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_CMASK
, 2);
1263 OUT_CS(tex
->tex
.cmask_dwords
);
1267 /* Mark the current zbuffer's zmask as in use. */
1268 r300
->cmask_in_use
= TRUE
;
1269 r300_mark_fb_state_dirty(r300
, R300_CHANGED_CMASK_ENABLE
);
1272 void r300_emit_ztop_state(struct r300_context
* r300
,
1273 unsigned size
, void* state
)
1275 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
1279 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
1283 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
1288 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
1292 boolean
r300_emit_buffer_validate(struct r300_context
*r300
,
1293 boolean do_validate_vertex_buffers
,
1294 struct pipe_resource
*index_buffer
)
1296 struct pipe_framebuffer_state
*fb
=
1297 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1298 struct r300_aa_state
*aa
= (struct r300_aa_state
*)r300
->aa_state
.state
;
1299 struct r300_textures_state
*texstate
=
1300 (struct r300_textures_state
*)r300
->textures_state
.state
;
1301 struct r300_resource
*tex
;
1303 boolean flushed
= FALSE
;
1306 if (r300
->fb_state
.dirty
) {
1307 /* Color buffers... */
1308 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1309 tex
= r300_resource(fb
->cbufs
[i
]->texture
);
1310 assert(tex
&& tex
->buf
&& "cbuf is marked, but NULL!");
1311 r300
->rws
->cs_add_reloc(r300
->cs
, tex
->cs_buf
,
1312 RADEON_USAGE_READWRITE
,
1313 r300_surface(fb
->cbufs
[i
])->domain
);
1315 /* ...depth buffer... */
1317 tex
= r300_resource(fb
->zsbuf
->texture
);
1318 assert(tex
&& tex
->buf
&& "zsbuf is marked, but NULL!");
1319 r300
->rws
->cs_add_reloc(r300
->cs
, tex
->cs_buf
,
1320 RADEON_USAGE_READWRITE
,
1321 r300_surface(fb
->zsbuf
)->domain
);
1324 /* The AA resolve buffer. */
1325 if (r300
->aa_state
.dirty
) {
1327 r300
->rws
->cs_add_reloc(r300
->cs
, aa
->dest
->cs_buf
,
1332 if (r300
->textures_state
.dirty
) {
1333 /* ...textures... */
1334 for (i
= 0; i
< texstate
->count
; i
++) {
1335 if (!(texstate
->tx_enable
& (1 << i
))) {
1339 tex
= r300_resource(texstate
->sampler_views
[i
]->base
.texture
);
1340 r300
->rws
->cs_add_reloc(r300
->cs
, tex
->cs_buf
, RADEON_USAGE_READ
,
1344 /* ...occlusion query buffer... */
1345 if (r300
->query_current
)
1346 r300
->rws
->cs_add_reloc(r300
->cs
, r300
->query_current
->cs_buf
,
1347 RADEON_USAGE_WRITE
, RADEON_DOMAIN_GTT
);
1348 /* ...vertex buffer for SWTCL path... */
1350 r300
->rws
->cs_add_reloc(r300
->cs
, r300
->vbo_cs
,
1351 RADEON_USAGE_READ
, RADEON_DOMAIN_GTT
);
1352 /* ...vertex buffers for HWTCL path... */
1353 if (do_validate_vertex_buffers
&& r300
->vertex_arrays_dirty
) {
1354 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
1355 struct pipe_vertex_buffer
*last
= r300
->vertex_buffer
+
1356 r300
->nr_vertex_buffers
;
1357 struct pipe_resource
*buf
;
1359 for (; vbuf
!= last
; vbuf
++) {
1364 r300
->rws
->cs_add_reloc(r300
->cs
, r300_resource(buf
)->cs_buf
,
1366 r300_resource(buf
)->domain
);
1369 /* ...and index buffer for HWTCL path. */
1371 r300
->rws
->cs_add_reloc(r300
->cs
, r300_resource(index_buffer
)->cs_buf
,
1373 r300_resource(index_buffer
)->domain
);
1375 /* Now do the validation (flush is called inside cs_validate on failure). */
1376 if (!r300
->rws
->cs_validate(r300
->cs
)) {
1377 /* Ooops, an infinite loop, give up. */
1388 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
1390 struct r300_atom
* atom
;
1391 unsigned dwords
= 0;
1393 foreach_dirty_atom(r300
, atom
) {
1395 dwords
+= atom
->size
;
1399 /* let's reserve some more, just in case */
1405 unsigned r300_get_num_cs_end_dwords(struct r300_context
*r300
)
1407 unsigned dwords
= 0;
1409 /* Emitted in flush. */
1410 dwords
+= 26; /* emit_query_end */
1411 dwords
+= r300
->hyperz_state
.size
+ 2; /* emit_hyperz_end + zcache flush */
1412 if (r300
->screen
->caps
.is_r500
)
1413 dwords
+= 2; /* emit_index_bias */
1414 if (r300
->screen
->info
.drm_minor
>= 6)
1415 dwords
+= 3; /* MSPOS */
1420 /* Emit all dirty state. */
1421 void r300_emit_dirty_state(struct r300_context
* r300
)
1423 struct r300_atom
*atom
;
1425 foreach_dirty_atom(r300
, atom
) {
1427 atom
->emit(r300
, atom
->size
, atom
->state
);
1428 atom
->dirty
= FALSE
;
1432 r300
->first_dirty
= NULL
;
1433 r300
->last_dirty
= NULL
;