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Merge remote branch 'origin/master' into lp-binning
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_state_inlines.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300, void* state)
39 {
40 struct r300_blend_state* blend = (struct r300_blend_state*)state;
41 struct pipe_framebuffer_state* fb =
42 (struct pipe_framebuffer_state*)r300->fb_state.state;
43 CS_LOCALS(r300);
44
45 BEGIN_CS(8);
46 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
47 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
48 if (fb->nr_cbufs) {
49 OUT_CS(blend->blend_control);
50 OUT_CS(blend->alpha_blend_control);
51 OUT_CS(blend->color_channel_mask);
52 } else {
53 OUT_CS(0);
54 OUT_CS(0);
55 OUT_CS(0);
56 /* XXX also disable fastfill here once it's supported */
57 }
58 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
59 END_CS;
60 }
61
62 void r300_emit_blend_color_state(struct r300_context* r300, void* state)
63 {
64 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
65 struct r300_screen* r300screen = r300_screen(r300->context.screen);
66 CS_LOCALS(r300);
67
68 if (r300screen->caps->is_r500) {
69 BEGIN_CS(3);
70 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
71 OUT_CS(bc->blend_color_red_alpha);
72 OUT_CS(bc->blend_color_green_blue);
73 END_CS;
74 } else {
75 BEGIN_CS(2);
76 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
77 END_CS;
78 }
79 }
80
81 void r300_emit_clip_state(struct r300_context* r300, void* state)
82 {
83 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
84 int i;
85 struct r300_screen* r300screen = r300_screen(r300->context.screen);
86 CS_LOCALS(r300);
87
88 if (r300screen->caps->has_tcl) {
89 BEGIN_CS(5 + (6 * 4));
90 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
91 (r300screen->caps->is_r500 ?
92 R500_PVS_UCP_START : R300_PVS_UCP_START));
93 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
94 for (i = 0; i < 6; i++) {
95 OUT_CS_32F(clip->ucp[i][0]);
96 OUT_CS_32F(clip->ucp[i][1]);
97 OUT_CS_32F(clip->ucp[i][2]);
98 OUT_CS_32F(clip->ucp[i][3]);
99 }
100 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
101 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
102 END_CS;
103 } else {
104 BEGIN_CS(2);
105 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
106 END_CS;
107 }
108
109 }
110
111 void r300_emit_dsa_state(struct r300_context* r300, void* state)
112 {
113 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
114 struct r300_screen* r300screen = r300_screen(r300->context.screen);
115 struct pipe_framebuffer_state* fb =
116 (struct pipe_framebuffer_state*)r300->fb_state.state;
117 CS_LOCALS(r300);
118
119 BEGIN_CS(r300screen->caps->is_r500 ? 8 : 6);
120 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
121
122 /* not needed since we use the 8bit alpha ref */
123 /*if (r300screen->caps->is_r500) {
124 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
125 }*/
126
127 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
128
129 if (fb->zsbuf) {
130 OUT_CS(dsa->z_buffer_control);
131 OUT_CS(dsa->z_stencil_control);
132 } else {
133 OUT_CS(0);
134 OUT_CS(0);
135 }
136
137 OUT_CS(dsa->stencil_ref_mask);
138
139 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
140 if (r300screen->caps->is_r500) {
141 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
142 }
143 END_CS;
144 }
145
146 static const float * get_shader_constant(
147 struct r300_context * r300,
148 struct rc_constant * constant,
149 struct r300_constant_buffer * externals)
150 {
151 struct r300_viewport_state* viewport =
152 (struct r300_viewport_state*)r300->viewport_state.state;
153 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
154 struct pipe_texture *tex;
155
156 switch(constant->Type) {
157 case RC_CONSTANT_EXTERNAL:
158 return externals->constants[constant->u.External];
159
160 case RC_CONSTANT_IMMEDIATE:
161 return constant->u.Immediate;
162
163 case RC_CONSTANT_STATE:
164 switch (constant->u.State[0]) {
165 /* Factor for converting rectangle coords to
166 * normalized coords. Should only show up on non-r500. */
167 case RC_STATE_R300_TEXRECT_FACTOR:
168 tex = &r300->textures[constant->u.State[1]]->tex;
169 vec[0] = 1.0 / tex->width0;
170 vec[1] = 1.0 / tex->height0;
171 break;
172
173 /* Texture compare-fail value. Shouldn't ever show up, but if
174 * it does, we'll be ready. */
175 case RC_STATE_SHADOW_AMBIENT:
176 vec[3] = 0;
177 break;
178
179 case RC_STATE_R300_VIEWPORT_SCALE:
180 if (r300->tcl_bypass) {
181 vec[0] = 1;
182 vec[1] = 1;
183 vec[2] = 1;
184 } else {
185 vec[0] = viewport->xscale;
186 vec[1] = viewport->yscale;
187 vec[2] = viewport->zscale;
188 }
189 break;
190
191 case RC_STATE_R300_VIEWPORT_OFFSET:
192 if (!r300->tcl_bypass) {
193 vec[0] = viewport->xoffset;
194 vec[1] = viewport->yoffset;
195 vec[2] = viewport->zoffset;
196 }
197 break;
198
199 default:
200 debug_printf("r300: Implementation error: "
201 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
202 }
203 break;
204
205 default:
206 debug_printf("r300: Implementation error: "
207 "Unhandled constant type %d\n", constant->Type);
208 }
209
210 /* This should either be (0, 0, 0, 1), which should be a relatively safe
211 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
212 * state factors. */
213 return vec;
214 }
215
216 /* Convert a normal single-precision float into the 7.16 format
217 * used by the R300 fragment shader.
218 */
219 static uint32_t pack_float24(float f)
220 {
221 union {
222 float fl;
223 uint32_t u;
224 } u;
225 float mantissa;
226 int exponent;
227 uint32_t float24 = 0;
228
229 if (f == 0.0)
230 return 0;
231
232 u.fl = f;
233
234 mantissa = frexpf(f, &exponent);
235
236 /* Handle -ve */
237 if (mantissa < 0) {
238 float24 |= (1 << 23);
239 mantissa = mantissa * -1.0;
240 }
241 /* Handle exponent, bias of 63 */
242 exponent += 62;
243 float24 |= (exponent << 16);
244 /* Kill 7 LSB of mantissa */
245 float24 |= (u.u & 0x7FFFFF) >> 7;
246
247 return float24;
248 }
249
250 void r300_emit_fragment_program_code(struct r300_context* r300,
251 struct rX00_fragment_program_code* generic_code)
252 {
253 struct r300_fragment_program_code * code = &generic_code->code.r300;
254 int i;
255 CS_LOCALS(r300);
256
257 BEGIN_CS(15 +
258 code->alu.length * 4 +
259 (code->tex.length ? (1 + code->tex.length) : 0));
260
261 OUT_CS_REG(R300_US_CONFIG, code->config);
262 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
263 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
264
265 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
266 for(i = 0; i < 4; ++i)
267 OUT_CS(code->code_addr[i]);
268
269 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
270 for (i = 0; i < code->alu.length; i++)
271 OUT_CS(code->alu.inst[i].rgb_inst);
272
273 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
274 for (i = 0; i < code->alu.length; i++)
275 OUT_CS(code->alu.inst[i].rgb_addr);
276
277 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
278 for (i = 0; i < code->alu.length; i++)
279 OUT_CS(code->alu.inst[i].alpha_inst);
280
281 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
282 for (i = 0; i < code->alu.length; i++)
283 OUT_CS(code->alu.inst[i].alpha_addr);
284
285 if (code->tex.length) {
286 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
287 for(i = 0; i < code->tex.length; ++i)
288 OUT_CS(code->tex.inst[i]);
289 }
290
291 END_CS;
292 }
293
294 void r300_emit_fs_constant_buffer(struct r300_context* r300,
295 struct rc_constant_list* constants)
296 {
297 int i;
298 CS_LOCALS(r300);
299
300 if (constants->Count == 0)
301 return;
302
303 BEGIN_CS(constants->Count * 4 + 1);
304 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
305 for(i = 0; i < constants->Count; ++i) {
306 const float * data = get_shader_constant(r300,
307 &constants->Constants[i],
308 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
309 OUT_CS(pack_float24(data[0]));
310 OUT_CS(pack_float24(data[1]));
311 OUT_CS(pack_float24(data[2]));
312 OUT_CS(pack_float24(data[3]));
313 }
314 END_CS;
315 }
316
317 static void r300_emit_fragment_depth_config(struct r300_context* r300,
318 struct r300_fragment_shader* fs)
319 {
320 CS_LOCALS(r300);
321
322 BEGIN_CS(4);
323 if (r300_fragment_shader_writes_depth(fs)) {
324 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
325 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
326 } else {
327 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
328 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
329 }
330 END_CS;
331 }
332
333 void r500_emit_fragment_program_code(struct r300_context* r300,
334 struct rX00_fragment_program_code* generic_code)
335 {
336 struct r500_fragment_program_code * code = &generic_code->code.r500;
337 int i;
338 CS_LOCALS(r300);
339
340 BEGIN_CS(13 +
341 ((code->inst_end + 1) * 6));
342 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
343 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
344 OUT_CS_REG(R500_US_CODE_RANGE,
345 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
346 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
347 OUT_CS_REG(R500_US_CODE_ADDR,
348 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
349
350 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
351 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
352 for (i = 0; i <= code->inst_end; i++) {
353 OUT_CS(code->inst[i].inst0);
354 OUT_CS(code->inst[i].inst1);
355 OUT_CS(code->inst[i].inst2);
356 OUT_CS(code->inst[i].inst3);
357 OUT_CS(code->inst[i].inst4);
358 OUT_CS(code->inst[i].inst5);
359 }
360
361 END_CS;
362 }
363
364 void r500_emit_fs_constant_buffer(struct r300_context* r300,
365 struct rc_constant_list* constants)
366 {
367 int i;
368 CS_LOCALS(r300);
369
370 if (constants->Count == 0)
371 return;
372
373 BEGIN_CS(constants->Count * 4 + 3);
374 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
375 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
376 for (i = 0; i < constants->Count; i++) {
377 const float * data = get_shader_constant(r300,
378 &constants->Constants[i],
379 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
380 OUT_CS_32F(data[0]);
381 OUT_CS_32F(data[1]);
382 OUT_CS_32F(data[2]);
383 OUT_CS_32F(data[3]);
384 }
385 END_CS;
386 }
387
388 void r300_emit_fb_state(struct r300_context* r300, void* state)
389 {
390 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
391 struct r300_texture* tex;
392 struct pipe_surface* surf;
393 int i;
394 CS_LOCALS(r300);
395
396 BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
397 (fb->zsbuf ? 10 : 0) + 6);
398
399 /* Flush and free renderbuffer caches. */
400 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
401 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
402 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
403 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
404 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
405 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
406
407 /* Set the number of colorbuffers. */
408 if (fb->nr_cbufs > 1) {
409 OUT_CS_REG(R300_RB3D_CCTL,
410 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
411 R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE |
412 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
413 } else {
414 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
415 }
416
417 /* Set up colorbuffers. */
418 for (i = 0; i < fb->nr_cbufs; i++) {
419 surf = fb->cbufs[i];
420 tex = (struct r300_texture*)surf->texture;
421 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
422
423 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
424 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
425
426 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
427 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
428 r300_translate_colorformat(tex->tex.format) |
429 R300_COLOR_TILE(tex->macrotile) |
430 R300_COLOR_MICROTILE(tex->microtile),
431 0, RADEON_GEM_DOMAIN_VRAM, 0);
432
433 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
434 r300_translate_out_fmt(surf->format));
435 }
436
437 /* Disable unused colorbuffers. */
438 for (; i < 4; i++) {
439 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
440 }
441
442 /* Set up a zbuffer. */
443 if (fb->zsbuf) {
444 surf = fb->zsbuf;
445 tex = (struct r300_texture*)surf->texture;
446 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
447
448 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
449 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
450
451 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
452
453 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
454 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
455 R300_DEPTHMACROTILE(tex->macrotile) |
456 R300_DEPTHMICROTILE(tex->microtile),
457 0, RADEON_GEM_DOMAIN_VRAM, 0);
458 }
459
460 END_CS;
461 }
462
463 static void r300_emit_query_start(struct r300_context *r300)
464 {
465 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
466 struct r300_query *query = r300->query_current;
467 CS_LOCALS(r300);
468
469 if (!query)
470 return;
471
472 BEGIN_CS(4);
473 if (caps->family == CHIP_FAMILY_RV530) {
474 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
475 } else {
476 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
477 }
478 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
479 END_CS;
480 query->begin_emitted = TRUE;
481 }
482
483
484 static void r300_emit_query_finish(struct r300_context *r300,
485 struct r300_query *query)
486 {
487 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
488 CS_LOCALS(r300);
489
490 assert(caps->num_frag_pipes);
491
492 BEGIN_CS(6 * caps->num_frag_pipes + 2);
493 /* I'm not so sure I like this switch, but it's hard to be elegant
494 * when there's so many special cases...
495 *
496 * So here's the basic idea. For each pipe, enable writes to it only,
497 * then put out the relocation for ZPASS_ADDR, taking into account a
498 * 4-byte offset for each pipe. RV380 and older are special; they have
499 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
500 * so there's a chipset cap for that. */
501 switch (caps->num_frag_pipes) {
502 case 4:
503 /* pipe 3 only */
504 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
505 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
506 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
507 0, RADEON_GEM_DOMAIN_GTT, 0);
508 case 3:
509 /* pipe 2 only */
510 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
511 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
512 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
513 0, RADEON_GEM_DOMAIN_GTT, 0);
514 case 2:
515 /* pipe 1 only */
516 /* As mentioned above, accomodate RV380 and older. */
517 OUT_CS_REG(R300_SU_REG_DEST,
518 1 << (caps->high_second_pipe ? 3 : 1));
519 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
520 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
521 0, RADEON_GEM_DOMAIN_GTT, 0);
522 case 1:
523 /* pipe 0 only */
524 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
525 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
526 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
527 0, RADEON_GEM_DOMAIN_GTT, 0);
528 break;
529 default:
530 debug_printf("r300: Implementation error: Chipset reports %d"
531 " pixel pipes!\n", caps->num_frag_pipes);
532 assert(0);
533 }
534
535 /* And, finally, reset it to normal... */
536 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
537 END_CS;
538 }
539
540 static void rv530_emit_query_single(struct r300_context *r300,
541 struct r300_query *query)
542 {
543 CS_LOCALS(r300);
544
545 BEGIN_CS(8);
546 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
547 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
548 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
549 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
550 END_CS;
551 }
552
553 static void rv530_emit_query_double(struct r300_context *r300,
554 struct r300_query *query)
555 {
556 CS_LOCALS(r300);
557
558 BEGIN_CS(14);
559 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
560 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
561 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
562 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
563 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
564 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
565 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
566 END_CS;
567 }
568
569 void r300_emit_query_end(struct r300_context* r300)
570 {
571 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
572 struct r300_query *query = r300->query_current;
573
574 if (!query)
575 return;
576
577 if (query->begin_emitted == FALSE)
578 return;
579
580 if (caps->family == CHIP_FAMILY_RV530) {
581 if (caps->num_z_pipes == 2)
582 rv530_emit_query_double(r300, query);
583 else
584 rv530_emit_query_single(r300, query);
585 } else
586 r300_emit_query_finish(r300, query);
587 }
588
589 void r300_emit_rs_state(struct r300_context* r300, void* state)
590 {
591 struct r300_rs_state* rs = (struct r300_rs_state*)state;
592 float scale, offset;
593 CS_LOCALS(r300);
594
595 BEGIN_CS(20 + (rs->polygon_offset_enable ? 5 : 0));
596 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
597
598 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
599
600 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
601 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
602 OUT_CS(rs->point_minmax);
603 OUT_CS(rs->line_control);
604
605 if (rs->polygon_offset_enable) {
606 scale = rs->depth_scale * 12;
607 offset = rs->depth_offset;
608
609 switch (r300->zbuffer_bpp) {
610 case 16:
611 offset *= 4;
612 break;
613 case 24:
614 offset *= 2;
615 break;
616 }
617
618 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
619 OUT_CS_32F(scale);
620 OUT_CS_32F(offset);
621 OUT_CS_32F(scale);
622 OUT_CS_32F(offset);
623 }
624
625 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
626 OUT_CS(rs->polygon_offset_enable);
627 OUT_CS(rs->cull_mode);
628 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
629 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
630 OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
631 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
632 END_CS;
633 }
634
635 void r300_emit_rs_block_state(struct r300_context* r300, void* state)
636 {
637 struct r300_rs_block* rs = (struct r300_rs_block*)state;
638 unsigned i;
639 struct r300_screen* r300screen = r300_screen(r300->context.screen);
640 CS_LOCALS(r300);
641
642 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
643
644 BEGIN_CS(21);
645 if (r300screen->caps->is_r500) {
646 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
647 } else {
648 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
649 }
650 for (i = 0; i < 8; i++) {
651 OUT_CS(rs->ip[i]);
652 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
653 }
654
655 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
656 OUT_CS(rs->count);
657 OUT_CS(rs->inst_count);
658
659 if (r300screen->caps->is_r500) {
660 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
661 } else {
662 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
663 }
664 for (i = 0; i < 8; i++) {
665 OUT_CS(rs->inst[i]);
666 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
667 }
668
669 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
670 rs->count, rs->inst_count);
671
672 END_CS;
673 }
674
675 void r300_emit_scissor_state(struct r300_context* r300, void* state)
676 {
677 unsigned minx, miny, maxx, maxy;
678 uint32_t top_left, bottom_right;
679 struct r300_screen* r300screen = r300_screen(r300->context.screen);
680 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
681 struct pipe_framebuffer_state* fb =
682 (struct pipe_framebuffer_state*)r300->fb_state.state;
683 CS_LOCALS(r300);
684
685 minx = miny = 0;
686 maxx = fb->width;
687 maxy = fb->height;
688
689 if (((struct r300_rs_state*)r300->rs_state.state)->rs.scissor) {
690 minx = MAX2(minx, scissor->minx);
691 miny = MAX2(miny, scissor->miny);
692 maxx = MIN2(maxx, scissor->maxx);
693 maxy = MIN2(maxy, scissor->maxy);
694 }
695
696 /* Special case for zero-area scissor.
697 *
698 * We can't allow the variables maxx and maxy to be zero because they are
699 * subtracted from later in the code, which would cause emitting ~0 and
700 * making the kernel checker angry.
701 *
702 * Let's consider we change maxx and maxy to 1, which is effectively
703 * a one-pixel area. We must then change minx and miny to a number which is
704 * greater than 1 to get the zero area back. */
705 if (!maxx || !maxy) {
706 minx = 2;
707 miny = 2;
708 maxx = 1;
709 maxy = 1;
710 }
711
712 if (r300screen->caps->is_r500) {
713 top_left =
714 (minx << R300_SCISSORS_X_SHIFT) |
715 (miny << R300_SCISSORS_Y_SHIFT);
716 bottom_right =
717 ((maxx - 1) << R300_SCISSORS_X_SHIFT) |
718 ((maxy - 1) << R300_SCISSORS_Y_SHIFT);
719 } else {
720 /* Offset of 1440 in non-R500 chipsets. */
721 top_left =
722 ((minx + 1440) << R300_SCISSORS_X_SHIFT) |
723 ((miny + 1440) << R300_SCISSORS_Y_SHIFT);
724 bottom_right =
725 (((maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
726 (((maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
727 }
728
729 BEGIN_CS(3);
730 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
731 OUT_CS(top_left);
732 OUT_CS(bottom_right);
733 END_CS;
734 }
735
736 void r300_emit_texture(struct r300_context* r300,
737 struct r300_sampler_state* sampler,
738 struct r300_texture* tex,
739 unsigned offset)
740 {
741 uint32_t filter0 = sampler->filter0;
742 uint32_t format0 = tex->state.format0;
743 unsigned min_level, max_level;
744 CS_LOCALS(r300);
745
746 /* to emulate 1D textures through 2D ones correctly */
747 if (tex->tex.target == PIPE_TEXTURE_1D) {
748 filter0 &= ~R300_TX_WRAP_T_MASK;
749 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
750 }
751
752 if (tex->is_npot) {
753 /* NPOT textures don't support mip filter, unfortunately.
754 * This prevents incorrect rendering. */
755 filter0 &= ~R300_TX_MIN_FILTER_MIP_MASK;
756 } else {
757 /* determine min/max levels */
758 /* the MAX_MIP level is the largest (finest) one */
759 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
760 min_level = MIN2(sampler->min_lod, max_level);
761 format0 |= R300_TX_NUM_LEVELS(max_level);
762 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
763 }
764
765 BEGIN_CS(16);
766 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
767 (offset << 28));
768 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
769 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
770
771 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
772 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
773 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
774 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
775 OUT_CS_RELOC(tex->buffer,
776 R300_TXO_MACRO_TILE(tex->macrotile) |
777 R300_TXO_MICRO_TILE(tex->microtile),
778 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
779 END_CS;
780 }
781
782 void r300_emit_aos(struct r300_context* r300, unsigned offset)
783 {
784 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
785 struct pipe_vertex_element *velem = r300->vertex_element;
786 int i;
787 unsigned size1, size2, aos_count = r300->vertex_element_count;
788 unsigned packet_size = (aos_count * 3 + 1) / 2;
789 CS_LOCALS(r300);
790
791 BEGIN_CS(2 + packet_size + aos_count * 2);
792 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
793 OUT_CS(aos_count);
794
795 for (i = 0; i < aos_count - 1; i += 2) {
796 vb1 = &vbuf[velem[i].vertex_buffer_index];
797 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
798 size1 = util_format_get_blocksize(velem[i].src_format);
799 size2 = util_format_get_blocksize(velem[i+1].src_format);
800
801 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
802 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
803 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
804 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
805 }
806
807 if (aos_count & 1) {
808 vb1 = &vbuf[velem[i].vertex_buffer_index];
809 size1 = util_format_get_blocksize(velem[i].src_format);
810
811 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
812 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
813 }
814
815 for (i = 0; i < aos_count; i++) {
816 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
817 RADEON_GEM_DOMAIN_GTT, 0, 0);
818 }
819 END_CS;
820 }
821
822 void r300_emit_vertex_format_state(struct r300_context* r300, void* state)
823 {
824 struct r300_vertex_info* vertex_info = (struct r300_vertex_info*)state;
825 unsigned i;
826 CS_LOCALS(r300);
827
828 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
829
830 BEGIN_CS(26);
831 OUT_CS_REG(R300_VAP_VTX_SIZE, vertex_info->vinfo.size);
832
833 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
834 OUT_CS(vertex_info->vinfo.hwfmt[0]);
835 OUT_CS(vertex_info->vinfo.hwfmt[1]);
836 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
837 OUT_CS(vertex_info->vinfo.hwfmt[2]);
838 OUT_CS(vertex_info->vinfo.hwfmt[3]);
839 for (i = 0; i < 4; i++) {
840 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
841 vertex_info->vinfo.hwfmt[i]);
842 }
843
844 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
845 for (i = 0; i < 8; i++) {
846 OUT_CS(vertex_info->vap_prog_stream_cntl[i]);
847 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
848 vertex_info->vap_prog_stream_cntl[i]);
849 }
850 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
851 for (i = 0; i < 8; i++) {
852 OUT_CS(vertex_info->vap_prog_stream_cntl_ext[i]);
853 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
854 vertex_info->vap_prog_stream_cntl_ext[i]);
855 }
856 END_CS;
857 }
858
859
860 void r300_emit_vertex_program_code(struct r300_context* r300,
861 struct r300_vertex_program_code* code)
862 {
863 int i;
864 struct r300_screen* r300screen = r300_screen(r300->context.screen);
865 unsigned instruction_count = code->length / 4;
866
867 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
868 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
869 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
870 int temp_count = MAX2(code->num_temporaries, 1);
871 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
872 vtx_mem_size / output_count, 10);
873 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
874
875 CS_LOCALS(r300);
876
877 if (!r300screen->caps->has_tcl) {
878 debug_printf("r300: Implementation error: emit_vertex_shader called,"
879 " but has_tcl is FALSE!\n");
880 return;
881 }
882
883 BEGIN_CS(9 + code->length);
884 /* R300_VAP_PVS_CODE_CNTL_0
885 * R300_VAP_PVS_CONST_CNTL
886 * R300_VAP_PVS_CODE_CNTL_1
887 * See the r5xx docs for instructions on how to use these. */
888 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
889 OUT_CS(R300_PVS_FIRST_INST(0) |
890 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
891 R300_PVS_LAST_INST(instruction_count - 1));
892 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
893 OUT_CS(instruction_count - 1);
894
895 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
896 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
897 for (i = 0; i < code->length; i++)
898 OUT_CS(code->body.d[i]);
899
900 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
901 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
902 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
903 R300_PVS_VF_MAX_VTX_NUM(12) |
904 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
905 END_CS;
906 }
907
908 void r300_emit_vertex_shader(struct r300_context* r300,
909 struct r300_vertex_shader* vs)
910 {
911 r300_emit_vertex_program_code(r300, &vs->code);
912 }
913
914 void r300_emit_vs_constant_buffer(struct r300_context* r300,
915 struct rc_constant_list* constants)
916 {
917 int i;
918 struct r300_screen* r300screen = r300_screen(r300->context.screen);
919 CS_LOCALS(r300);
920
921 if (!r300screen->caps->has_tcl) {
922 debug_printf("r300: Implementation error: emit_vertex_shader called,"
923 " but has_tcl is FALSE!\n");
924 return;
925 }
926
927 if (constants->Count == 0)
928 return;
929
930 BEGIN_CS(constants->Count * 4 + 3);
931 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
932 (r300screen->caps->is_r500 ?
933 R500_PVS_CONST_START : R300_PVS_CONST_START));
934 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
935 for (i = 0; i < constants->Count; i++) {
936 const float * data = get_shader_constant(r300,
937 &constants->Constants[i],
938 &r300->shader_constants[PIPE_SHADER_VERTEX]);
939 OUT_CS_32F(data[0]);
940 OUT_CS_32F(data[1]);
941 OUT_CS_32F(data[2]);
942 OUT_CS_32F(data[3]);
943 }
944 END_CS;
945 }
946
947 void r300_emit_viewport_state(struct r300_context* r300, void* state)
948 {
949 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
950 CS_LOCALS(r300);
951
952 if (r300->tcl_bypass) {
953 BEGIN_CS(2);
954 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
955 END_CS;
956 } else {
957 BEGIN_CS(9);
958 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
959 OUT_CS_32F(viewport->xscale);
960 OUT_CS_32F(viewport->xoffset);
961 OUT_CS_32F(viewport->yscale);
962 OUT_CS_32F(viewport->yoffset);
963 OUT_CS_32F(viewport->zscale);
964 OUT_CS_32F(viewport->zoffset);
965 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
966 END_CS;
967 }
968 }
969
970 void r300_emit_texture_count(struct r300_context* r300)
971 {
972 uint32_t tx_enable = 0;
973 int i;
974 CS_LOCALS(r300);
975
976 /* Notice that texture_count and sampler_count are just sizes
977 * of the respective arrays. We still have to check for the individual
978 * elements. */
979 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
980 if (r300->textures[i]) {
981 tx_enable |= 1 << i;
982 }
983 }
984
985 BEGIN_CS(2);
986 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
987 END_CS;
988
989 }
990
991 void r300_emit_ztop_state(struct r300_context* r300, void* state)
992 {
993 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
994 CS_LOCALS(r300);
995
996 BEGIN_CS(2);
997 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
998 END_CS;
999 }
1000
1001 void r300_flush_textures(struct r300_context* r300)
1002 {
1003 CS_LOCALS(r300);
1004
1005 BEGIN_CS(2);
1006 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1007 END_CS;
1008 }
1009
1010 static void r300_flush_pvs(struct r300_context* r300)
1011 {
1012 CS_LOCALS(r300);
1013
1014 BEGIN_CS(2);
1015 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
1016 END_CS;
1017 }
1018
1019 void r300_emit_buffer_validate(struct r300_context *r300)
1020 {
1021 struct pipe_framebuffer_state* fb =
1022 (struct pipe_framebuffer_state*)r300->fb_state.state;
1023 struct r300_texture* tex;
1024 unsigned i;
1025 boolean invalid = FALSE;
1026
1027 /* Clean out BOs. */
1028 r300->winsys->reset_bos(r300->winsys);
1029
1030 validate:
1031 /* Color buffers... */
1032 for (i = 0; i < fb->nr_cbufs; i++) {
1033 tex = (struct r300_texture*)fb->cbufs[i]->texture;
1034 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1035 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1036 0, RADEON_GEM_DOMAIN_VRAM)) {
1037 r300->context.flush(&r300->context, 0, NULL);
1038 goto validate;
1039 }
1040 }
1041 /* ...depth buffer... */
1042 if (fb->zsbuf) {
1043 tex = (struct r300_texture*)fb->zsbuf->texture;
1044 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1045 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1046 0, RADEON_GEM_DOMAIN_VRAM)) {
1047 r300->context.flush(&r300->context, 0, NULL);
1048 goto validate;
1049 }
1050 }
1051 /* ...textures... */
1052 for (i = 0; i < r300->texture_count; i++) {
1053 tex = r300->textures[i];
1054 if (!tex)
1055 continue;
1056 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1057 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1058 r300->context.flush(&r300->context, 0, NULL);
1059 goto validate;
1060 }
1061 }
1062 /* ...occlusion query buffer... */
1063 if (r300->dirty_state & R300_NEW_QUERY) {
1064 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1065 0, RADEON_GEM_DOMAIN_GTT)) {
1066 r300->context.flush(&r300->context, 0, NULL);
1067 goto validate;
1068 }
1069 }
1070 /* ...and vertex buffer. */
1071 if (r300->vbo) {
1072 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1073 RADEON_GEM_DOMAIN_GTT, 0)) {
1074 r300->context.flush(&r300->context, 0, NULL);
1075 goto validate;
1076 }
1077 } else {
1078 /* debug_printf("No VBO while emitting dirty state!\n"); */
1079 }
1080 if (!r300->winsys->validate(r300->winsys)) {
1081 r300->context.flush(&r300->context, 0, NULL);
1082 if (invalid) {
1083 /* Well, hell. */
1084 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1085 exit(1);
1086 }
1087 invalid = TRUE;
1088 goto validate;
1089 }
1090 }
1091
1092 /* Emit all dirty state. */
1093 void r300_emit_dirty_state(struct r300_context* r300)
1094 {
1095 struct r300_screen* r300screen = r300_screen(r300->context.screen);
1096 struct r300_atom* atom;
1097 unsigned i, dwords = 1024;
1098 int dirty_tex = 0;
1099
1100 /* Check the required number of dwords against the space remaining in the
1101 * current CS object. If we need more, then flush. */
1102
1103 foreach(atom, &r300->atom_list) {
1104 if (atom->dirty || atom->always_dirty) {
1105 dwords += atom->size;
1106 }
1107 }
1108
1109 /* Make sure we have at least 2*1024 spare dwords. */
1110 /* XXX It would be nice to know the number of dwords we really need to
1111 * XXX emit. */
1112 while (!r300->winsys->check_cs(r300->winsys, dwords)) {
1113 r300->context.flush(&r300->context, 0, NULL);
1114 }
1115
1116 if (r300->dirty_state & R300_NEW_QUERY) {
1117 r300_emit_query_start(r300);
1118 r300->dirty_state &= ~R300_NEW_QUERY;
1119 }
1120
1121 foreach(atom, &r300->atom_list) {
1122 if (atom->dirty || atom->always_dirty) {
1123 atom->emit(r300, atom->state);
1124 atom->dirty = FALSE;
1125 }
1126 }
1127
1128 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1129 r300_emit_fragment_depth_config(r300, r300->fs);
1130 if (r300screen->caps->is_r500) {
1131 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1132 } else {
1133 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1134 }
1135 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1136 }
1137
1138 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1139 if (r300screen->caps->is_r500) {
1140 r500_emit_fs_constant_buffer(r300,
1141 &r300->fs->shader->code.constants);
1142 } else {
1143 r300_emit_fs_constant_buffer(r300,
1144 &r300->fs->shader->code.constants);
1145 }
1146 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1147 }
1148
1149 /* Samplers and textures are tracked separately but emitted together. */
1150 if (r300->dirty_state &
1151 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1152 r300_emit_texture_count(r300);
1153
1154 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1155 if (r300->dirty_state &
1156 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1157 if (r300->textures[i])
1158 r300_emit_texture(r300,
1159 r300->sampler_states[i],
1160 r300->textures[i],
1161 i);
1162 r300->dirty_state &=
1163 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1164 dirty_tex++;
1165 }
1166 }
1167 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1168 }
1169
1170 if (dirty_tex) {
1171 r300_flush_textures(r300);
1172 }
1173
1174 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1175 r300_flush_pvs(r300);
1176 }
1177
1178 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1179 r300_emit_vertex_shader(r300, r300->vs);
1180 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1181 }
1182
1183 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1184 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1185 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1186 }
1187
1188 /* XXX
1189 assert(r300->dirty_state == 0);
1190 */
1191
1192 /* Finally, emit the VBO. */
1193 /* r300_emit_vertex_buffer(r300); */
1194
1195 r300->dirty_hw++;
1196 }