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r300g: put validating buffers after flushing
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_vs.h"
36
37 void r300_emit_blend_state(struct r300_context* r300,
38 unsigned size, void* state)
39 {
40 struct r300_blend_state* blend = (struct r300_blend_state*)state;
41 struct pipe_framebuffer_state* fb =
42 (struct pipe_framebuffer_state*)r300->fb_state.state;
43 CS_LOCALS(r300);
44
45 BEGIN_CS(size);
46 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
47 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
48 if (fb->nr_cbufs) {
49 OUT_CS(blend->blend_control);
50 OUT_CS(blend->alpha_blend_control);
51 OUT_CS(blend->color_channel_mask);
52 } else {
53 OUT_CS(0);
54 OUT_CS(0);
55 OUT_CS(0);
56 /* XXX also disable fastfill here once it's supported */
57 }
58 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
59 END_CS;
60 }
61
62 void r300_emit_blend_color_state(struct r300_context* r300,
63 unsigned size, void* state)
64 {
65 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
66 struct r300_screen* r300screen = r300_screen(r300->context.screen);
67 CS_LOCALS(r300);
68
69 if (r300screen->caps->is_r500) {
70 BEGIN_CS(size);
71 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
72 OUT_CS(bc->blend_color_red_alpha);
73 OUT_CS(bc->blend_color_green_blue);
74 END_CS;
75 } else {
76 BEGIN_CS(size);
77 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
78 END_CS;
79 }
80 }
81
82 void r300_emit_clip_state(struct r300_context* r300,
83 unsigned size, void* state)
84 {
85 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
86 int i;
87 struct r300_screen* r300screen = r300_screen(r300->context.screen);
88 CS_LOCALS(r300);
89
90 if (r300screen->caps->has_tcl) {
91 BEGIN_CS(size);
92 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
93 (r300screen->caps->is_r500 ?
94 R500_PVS_UCP_START : R300_PVS_UCP_START));
95 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
96 for (i = 0; i < 6; i++) {
97 OUT_CS_32F(clip->ucp[i][0]);
98 OUT_CS_32F(clip->ucp[i][1]);
99 OUT_CS_32F(clip->ucp[i][2]);
100 OUT_CS_32F(clip->ucp[i][3]);
101 }
102 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
103 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
104 END_CS;
105 } else {
106 BEGIN_CS(size);
107 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
108 END_CS;
109 }
110
111 }
112
113 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
114 {
115 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
116 struct r300_screen* r300screen = r300_screen(r300->context.screen);
117 struct pipe_framebuffer_state* fb =
118 (struct pipe_framebuffer_state*)r300->fb_state.state;
119 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
120 CS_LOCALS(r300);
121
122 BEGIN_CS(size);
123 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
124 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
125
126 if (fb->zsbuf) {
127 OUT_CS(dsa->z_buffer_control);
128 OUT_CS(dsa->z_stencil_control);
129 } else {
130 OUT_CS(0);
131 OUT_CS(0);
132 }
133
134 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
135
136 if (r300screen->caps->is_r500) {
137 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
138 }
139 END_CS;
140 }
141
142 static const float * get_shader_constant(
143 struct r300_context * r300,
144 struct rc_constant * constant,
145 struct r300_constant_buffer * externals)
146 {
147 struct r300_viewport_state* viewport =
148 (struct r300_viewport_state*)r300->viewport_state.state;
149 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
150 struct pipe_texture *tex;
151
152 switch(constant->Type) {
153 case RC_CONSTANT_EXTERNAL:
154 return externals->constants[constant->u.External];
155
156 case RC_CONSTANT_IMMEDIATE:
157 return constant->u.Immediate;
158
159 case RC_CONSTANT_STATE:
160 switch (constant->u.State[0]) {
161 /* Factor for converting rectangle coords to
162 * normalized coords. Should only show up on non-r500. */
163 case RC_STATE_R300_TEXRECT_FACTOR:
164 tex = &r300->textures[constant->u.State[1]]->tex;
165 vec[0] = 1.0 / tex->width0;
166 vec[1] = 1.0 / tex->height0;
167 break;
168
169 /* Texture compare-fail value. Shouldn't ever show up, but if
170 * it does, we'll be ready. */
171 case RC_STATE_SHADOW_AMBIENT:
172 vec[3] = 0;
173 break;
174
175 case RC_STATE_R300_VIEWPORT_SCALE:
176 if (r300->tcl_bypass) {
177 vec[0] = 1;
178 vec[1] = 1;
179 vec[2] = 1;
180 } else {
181 vec[0] = viewport->xscale;
182 vec[1] = viewport->yscale;
183 vec[2] = viewport->zscale;
184 }
185 break;
186
187 case RC_STATE_R300_VIEWPORT_OFFSET:
188 if (!r300->tcl_bypass) {
189 vec[0] = viewport->xoffset;
190 vec[1] = viewport->yoffset;
191 vec[2] = viewport->zoffset;
192 }
193 break;
194
195 default:
196 debug_printf("r300: Implementation error: "
197 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
198 }
199 break;
200
201 default:
202 debug_printf("r300: Implementation error: "
203 "Unhandled constant type %d\n", constant->Type);
204 }
205
206 /* This should either be (0, 0, 0, 1), which should be a relatively safe
207 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
208 * state factors. */
209 return vec;
210 }
211
212 /* Convert a normal single-precision float into the 7.16 format
213 * used by the R300 fragment shader.
214 */
215 static uint32_t pack_float24(float f)
216 {
217 union {
218 float fl;
219 uint32_t u;
220 } u;
221 float mantissa;
222 int exponent;
223 uint32_t float24 = 0;
224
225 if (f == 0.0)
226 return 0;
227
228 u.fl = f;
229
230 mantissa = frexpf(f, &exponent);
231
232 /* Handle -ve */
233 if (mantissa < 0) {
234 float24 |= (1 << 23);
235 mantissa = mantissa * -1.0;
236 }
237 /* Handle exponent, bias of 63 */
238 exponent += 62;
239 float24 |= (exponent << 16);
240 /* Kill 7 LSB of mantissa */
241 float24 |= (u.u & 0x7FFFFF) >> 7;
242
243 return float24;
244 }
245
246 void r300_emit_fragment_program_code(struct r300_context* r300,
247 struct rX00_fragment_program_code* generic_code)
248 {
249 struct r300_fragment_program_code * code = &generic_code->code.r300;
250 int i;
251 CS_LOCALS(r300);
252
253 BEGIN_CS(15 +
254 code->alu.length * 4 +
255 (code->tex.length ? (1 + code->tex.length) : 0));
256
257 OUT_CS_REG(R300_US_CONFIG, code->config);
258 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
259 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
260
261 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
262 for(i = 0; i < 4; ++i)
263 OUT_CS(code->code_addr[i]);
264
265 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
266 for (i = 0; i < code->alu.length; i++)
267 OUT_CS(code->alu.inst[i].rgb_inst);
268
269 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
270 for (i = 0; i < code->alu.length; i++)
271 OUT_CS(code->alu.inst[i].rgb_addr);
272
273 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
274 for (i = 0; i < code->alu.length; i++)
275 OUT_CS(code->alu.inst[i].alpha_inst);
276
277 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
278 for (i = 0; i < code->alu.length; i++)
279 OUT_CS(code->alu.inst[i].alpha_addr);
280
281 if (code->tex.length) {
282 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
283 for(i = 0; i < code->tex.length; ++i)
284 OUT_CS(code->tex.inst[i]);
285 }
286
287 END_CS;
288 }
289
290 void r300_emit_fs_constant_buffer(struct r300_context* r300,
291 struct rc_constant_list* constants)
292 {
293 int i;
294 CS_LOCALS(r300);
295
296 if (constants->Count == 0)
297 return;
298
299 BEGIN_CS(constants->Count * 4 + 1);
300 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
301 for(i = 0; i < constants->Count; ++i) {
302 const float * data = get_shader_constant(r300,
303 &constants->Constants[i],
304 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
305 OUT_CS(pack_float24(data[0]));
306 OUT_CS(pack_float24(data[1]));
307 OUT_CS(pack_float24(data[2]));
308 OUT_CS(pack_float24(data[3]));
309 }
310 END_CS;
311 }
312
313 static void r300_emit_fragment_depth_config(struct r300_context* r300,
314 struct r300_fragment_shader* fs)
315 {
316 CS_LOCALS(r300);
317
318 BEGIN_CS(4);
319 if (r300_fragment_shader_writes_depth(fs)) {
320 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
321 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
322 } else {
323 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
324 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
325 }
326 END_CS;
327 }
328
329 void r500_emit_fragment_program_code(struct r300_context* r300,
330 struct rX00_fragment_program_code* generic_code)
331 {
332 struct r500_fragment_program_code * code = &generic_code->code.r500;
333 int i;
334 CS_LOCALS(r300);
335
336 BEGIN_CS(13 +
337 ((code->inst_end + 1) * 6));
338 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
339 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
340 OUT_CS_REG(R500_US_CODE_RANGE,
341 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
342 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
343 OUT_CS_REG(R500_US_CODE_ADDR,
344 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
345
346 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
347 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
348 for (i = 0; i <= code->inst_end; i++) {
349 OUT_CS(code->inst[i].inst0);
350 OUT_CS(code->inst[i].inst1);
351 OUT_CS(code->inst[i].inst2);
352 OUT_CS(code->inst[i].inst3);
353 OUT_CS(code->inst[i].inst4);
354 OUT_CS(code->inst[i].inst5);
355 }
356
357 END_CS;
358 }
359
360 void r500_emit_fs_constant_buffer(struct r300_context* r300,
361 struct rc_constant_list* constants)
362 {
363 int i;
364 CS_LOCALS(r300);
365
366 if (constants->Count == 0)
367 return;
368
369 BEGIN_CS(constants->Count * 4 + 3);
370 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
371 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
372 for (i = 0; i < constants->Count; i++) {
373 const float * data = get_shader_constant(r300,
374 &constants->Constants[i],
375 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
376 OUT_CS_32F(data[0]);
377 OUT_CS_32F(data[1]);
378 OUT_CS_32F(data[2]);
379 OUT_CS_32F(data[3]);
380 }
381 END_CS;
382 }
383
384 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
385 {
386 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
387 struct r300_screen* r300screen = r300_screen(r300->context.screen);
388 struct r300_texture* tex;
389 struct pipe_surface* surf;
390 int i;
391 CS_LOCALS(r300);
392
393 BEGIN_CS(size);
394
395 /* Flush and free renderbuffer caches. */
396 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
397 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
398 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
399 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
400 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
401 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
402
403 /* Set the number of colorbuffers. */
404 if (fb->nr_cbufs > 1) {
405 if (r300screen->caps->is_r500) {
406 OUT_CS_REG(R300_RB3D_CCTL,
407 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
408 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
409 } else {
410 OUT_CS_REG(R300_RB3D_CCTL,
411 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
412 }
413 } else {
414 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
415 }
416
417 /* Set up colorbuffers. */
418 for (i = 0; i < fb->nr_cbufs; i++) {
419 surf = fb->cbufs[i];
420 tex = (struct r300_texture*)surf->texture;
421 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
422
423 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
424 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
425
426 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
427 OUT_CS_RELOC(tex->buffer, tex->fb_state.colorpitch[surf->level],
428 0, RADEON_GEM_DOMAIN_VRAM, 0);
429
430 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
431 }
432 for (; i < 4; i++) {
433 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
434 }
435
436 /* Set up a zbuffer. */
437 if (fb->zsbuf) {
438 surf = fb->zsbuf;
439 tex = (struct r300_texture*)surf->texture;
440 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
441
442 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
443 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
444
445 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
446
447 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
448 OUT_CS_RELOC(tex->buffer, tex->fb_state.depthpitch[surf->level],
449 0, RADEON_GEM_DOMAIN_VRAM, 0);
450 }
451
452 OUT_CS_REG(R300_GA_POINT_MINMAX,
453 (MAX2(fb->width, fb->height) * 6) << R300_GA_POINT_MINMAX_MAX_SHIFT);
454 END_CS;
455 }
456
457 static void r300_emit_query_start(struct r300_context *r300)
458 {
459 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
460 struct r300_query *query = r300->query_current;
461 CS_LOCALS(r300);
462
463 if (!query)
464 return;
465
466 BEGIN_CS(4);
467 if (caps->family == CHIP_FAMILY_RV530) {
468 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
469 } else {
470 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
471 }
472 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
473 END_CS;
474 query->begin_emitted = TRUE;
475 }
476
477
478 static void r300_emit_query_finish(struct r300_context *r300,
479 struct r300_query *query)
480 {
481 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
482 CS_LOCALS(r300);
483
484 assert(caps->num_frag_pipes);
485
486 BEGIN_CS(6 * caps->num_frag_pipes + 2);
487 /* I'm not so sure I like this switch, but it's hard to be elegant
488 * when there's so many special cases...
489 *
490 * So here's the basic idea. For each pipe, enable writes to it only,
491 * then put out the relocation for ZPASS_ADDR, taking into account a
492 * 4-byte offset for each pipe. RV380 and older are special; they have
493 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
494 * so there's a chipset cap for that. */
495 switch (caps->num_frag_pipes) {
496 case 4:
497 /* pipe 3 only */
498 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
499 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
500 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
501 0, RADEON_GEM_DOMAIN_GTT, 0);
502 case 3:
503 /* pipe 2 only */
504 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
505 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
506 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
507 0, RADEON_GEM_DOMAIN_GTT, 0);
508 case 2:
509 /* pipe 1 only */
510 /* As mentioned above, accomodate RV380 and older. */
511 OUT_CS_REG(R300_SU_REG_DEST,
512 1 << (caps->high_second_pipe ? 3 : 1));
513 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
514 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
515 0, RADEON_GEM_DOMAIN_GTT, 0);
516 case 1:
517 /* pipe 0 only */
518 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
519 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
520 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
521 0, RADEON_GEM_DOMAIN_GTT, 0);
522 break;
523 default:
524 debug_printf("r300: Implementation error: Chipset reports %d"
525 " pixel pipes!\n", caps->num_frag_pipes);
526 assert(0);
527 }
528
529 /* And, finally, reset it to normal... */
530 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
531 END_CS;
532 }
533
534 static void rv530_emit_query_single(struct r300_context *r300,
535 struct r300_query *query)
536 {
537 CS_LOCALS(r300);
538
539 BEGIN_CS(8);
540 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
541 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
542 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
543 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
544 END_CS;
545 }
546
547 static void rv530_emit_query_double(struct r300_context *r300,
548 struct r300_query *query)
549 {
550 CS_LOCALS(r300);
551
552 BEGIN_CS(14);
553 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
554 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
555 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
556 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
557 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
558 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
559 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
560 END_CS;
561 }
562
563 void r300_emit_query_end(struct r300_context* r300)
564 {
565 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
566 struct r300_query *query = r300->query_current;
567
568 if (!query)
569 return;
570
571 if (query->begin_emitted == FALSE)
572 return;
573
574 if (caps->family == CHIP_FAMILY_RV530) {
575 if (caps->num_z_pipes == 2)
576 rv530_emit_query_double(r300, query);
577 else
578 rv530_emit_query_single(r300, query);
579 } else
580 r300_emit_query_finish(r300, query);
581 }
582
583 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
584 {
585 struct r300_rs_state* rs = (struct r300_rs_state*)state;
586 float scale, offset;
587 CS_LOCALS(r300);
588
589 BEGIN_CS(size);
590 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
591
592 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
593
594 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
595 OUT_CS_REG(R300_GA_LINE_CNTL, rs->line_control);
596
597 if (rs->polygon_offset_enable) {
598 scale = rs->depth_scale * 12;
599 offset = rs->depth_offset;
600
601 switch (r300->zbuffer_bpp) {
602 case 16:
603 offset *= 4;
604 break;
605 case 24:
606 offset *= 2;
607 break;
608 }
609
610 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
611 OUT_CS_32F(scale);
612 OUT_CS_32F(offset);
613 OUT_CS_32F(scale);
614 OUT_CS_32F(offset);
615 }
616
617 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
618 OUT_CS(rs->polygon_offset_enable);
619 OUT_CS(rs->cull_mode);
620 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
621 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
622 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
623 END_CS;
624 }
625
626 void r300_emit_rs_block_state(struct r300_context* r300,
627 unsigned size, void* state)
628 {
629 struct r300_rs_block* rs = (struct r300_rs_block*)state;
630 unsigned i;
631 struct r300_screen* r300screen = r300_screen(r300->context.screen);
632 /* It's the same for both INST and IP tables */
633 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
634 CS_LOCALS(r300);
635
636 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
637
638 BEGIN_CS(size);
639 if (r300screen->caps->is_r500) {
640 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
641 } else {
642 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
643 }
644 for (i = 0; i < count; i++) {
645 OUT_CS(rs->ip[i]);
646 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
647 }
648
649 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
650 OUT_CS(rs->count);
651 OUT_CS(rs->inst_count);
652
653 if (r300screen->caps->is_r500) {
654 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
655 } else {
656 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
657 }
658 for (i = 0; i < count; i++) {
659 OUT_CS(rs->inst[i]);
660 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
661 }
662
663 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
664 rs->count, rs->inst_count);
665
666 END_CS;
667 }
668
669 void r300_emit_scissor_state(struct r300_context* r300,
670 unsigned size, void* state)
671 {
672 unsigned minx, miny, maxx, maxy;
673 uint32_t top_left, bottom_right;
674 struct r300_screen* r300screen = r300_screen(r300->context.screen);
675 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
676 struct pipe_framebuffer_state* fb =
677 (struct pipe_framebuffer_state*)r300->fb_state.state;
678 CS_LOCALS(r300);
679
680 minx = miny = 0;
681 maxx = fb->width;
682 maxy = fb->height;
683
684 if (((struct r300_rs_state*)r300->rs_state.state)->rs.scissor) {
685 minx = MAX2(minx, scissor->minx);
686 miny = MAX2(miny, scissor->miny);
687 maxx = MIN2(maxx, scissor->maxx);
688 maxy = MIN2(maxy, scissor->maxy);
689 }
690
691 /* Special case for zero-area scissor.
692 *
693 * We can't allow the variables maxx and maxy to be zero because they are
694 * subtracted from later in the code, which would cause emitting ~0 and
695 * making the kernel checker angry.
696 *
697 * Let's consider we change maxx and maxy to 1, which is effectively
698 * a one-pixel area. We must then change minx and miny to a number which is
699 * greater than 1 to get the zero area back. */
700 if (!maxx || !maxy) {
701 minx = 2;
702 miny = 2;
703 maxx = 1;
704 maxy = 1;
705 }
706
707 if (r300screen->caps->is_r500) {
708 top_left =
709 (minx << R300_SCISSORS_X_SHIFT) |
710 (miny << R300_SCISSORS_Y_SHIFT);
711 bottom_right =
712 ((maxx - 1) << R300_SCISSORS_X_SHIFT) |
713 ((maxy - 1) << R300_SCISSORS_Y_SHIFT);
714 } else {
715 /* Offset of 1440 in non-R500 chipsets. */
716 top_left =
717 ((minx + 1440) << R300_SCISSORS_X_SHIFT) |
718 ((miny + 1440) << R300_SCISSORS_Y_SHIFT);
719 bottom_right =
720 (((maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
721 (((maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
722 }
723
724 BEGIN_CS(size);
725 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
726 OUT_CS(top_left);
727 OUT_CS(bottom_right);
728 END_CS;
729 }
730
731 void r300_emit_texture(struct r300_context* r300,
732 struct r300_sampler_state* sampler,
733 struct r300_texture* tex,
734 unsigned offset)
735 {
736 uint32_t filter0 = sampler->filter0;
737 uint32_t format0 = tex->state.format0;
738 unsigned min_level, max_level;
739 CS_LOCALS(r300);
740
741 /* to emulate 1D textures through 2D ones correctly */
742 if (tex->tex.target == PIPE_TEXTURE_1D) {
743 filter0 &= ~R300_TX_WRAP_T_MASK;
744 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
745 }
746
747 if (tex->is_npot) {
748 /* NPOT textures don't support mip filter, unfortunately.
749 * This prevents incorrect rendering. */
750 filter0 &= ~R300_TX_MIN_FILTER_MIP_MASK;
751 } else {
752 /* determine min/max levels */
753 /* the MAX_MIP level is the largest (finest) one */
754 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
755 min_level = MIN2(sampler->min_lod, max_level);
756 format0 |= R300_TX_NUM_LEVELS(max_level);
757 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
758 }
759
760 BEGIN_CS(16);
761 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
762 (offset << 28));
763 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
764 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
765
766 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
767 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
768 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
769 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
770 OUT_CS_RELOC(tex->buffer,
771 R300_TXO_MACRO_TILE(tex->macrotile) |
772 R300_TXO_MICRO_TILE(tex->microtile),
773 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
774 END_CS;
775 }
776
777 void r300_emit_aos(struct r300_context* r300, unsigned offset)
778 {
779 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
780 struct pipe_vertex_element *velem = r300->vertex_element;
781 int i;
782 unsigned size1, size2, aos_count = r300->vertex_element_count;
783 unsigned packet_size = (aos_count * 3 + 1) / 2;
784 CS_LOCALS(r300);
785
786 BEGIN_CS(2 + packet_size + aos_count * 2);
787 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
788 OUT_CS(aos_count);
789
790 for (i = 0; i < aos_count - 1; i += 2) {
791 vb1 = &vbuf[velem[i].vertex_buffer_index];
792 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
793 size1 = util_format_get_blocksize(velem[i].src_format);
794 size2 = util_format_get_blocksize(velem[i+1].src_format);
795
796 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
797 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
798 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
799 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
800 }
801
802 if (aos_count & 1) {
803 vb1 = &vbuf[velem[i].vertex_buffer_index];
804 size1 = util_format_get_blocksize(velem[i].src_format);
805
806 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
807 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
808 }
809
810 for (i = 0; i < aos_count; i++) {
811 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
812 RADEON_GEM_DOMAIN_GTT, 0, 0);
813 }
814 END_CS;
815 }
816
817 void r300_emit_vertex_format_state(struct r300_context* r300,
818 unsigned size, void* state)
819 {
820 struct r300_vertex_info* vertex_info = (struct r300_vertex_info*)state;
821 unsigned i;
822 CS_LOCALS(r300);
823
824 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
825
826 BEGIN_CS(size);
827 OUT_CS_REG(R300_VAP_VTX_SIZE, vertex_info->vinfo.size);
828
829 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
830 OUT_CS(vertex_info->vinfo.hwfmt[0]);
831 OUT_CS(vertex_info->vinfo.hwfmt[1]);
832 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
833 OUT_CS(vertex_info->vinfo.hwfmt[2]);
834 OUT_CS(vertex_info->vinfo.hwfmt[3]);
835 for (i = 0; i < 4; i++) {
836 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
837 vertex_info->vinfo.hwfmt[i]);
838 }
839
840 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
841 for (i = 0; i < 8; i++) {
842 OUT_CS(vertex_info->vap_prog_stream_cntl[i]);
843 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
844 vertex_info->vap_prog_stream_cntl[i]);
845 }
846 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
847 for (i = 0; i < 8; i++) {
848 OUT_CS(vertex_info->vap_prog_stream_cntl_ext[i]);
849 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
850 vertex_info->vap_prog_stream_cntl_ext[i]);
851 }
852 END_CS;
853 }
854
855 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
856 {
857 CS_LOCALS(r300);
858
859 BEGIN_CS(size);
860 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
861 END_CS;
862 }
863
864 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
865 {
866 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
867 struct r300_vertex_program_code* code = &vs->code;
868 struct r300_screen* r300screen = r300_screen(r300->context.screen);
869 unsigned instruction_count = code->length / 4;
870 unsigned i;
871
872 unsigned vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
873 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
874 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
875 unsigned temp_count = MAX2(code->num_temporaries, 1);
876
877 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
878 vtx_mem_size / output_count, 10);
879 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
880
881 CS_LOCALS(r300);
882
883 if (!r300screen->caps->has_tcl) {
884 debug_printf("r300: Implementation error: emit_vertex_shader called,"
885 " but has_tcl is FALSE!\n");
886 return;
887 }
888
889 BEGIN_CS(size);
890 /* R300_VAP_PVS_CODE_CNTL_0
891 * R300_VAP_PVS_CONST_CNTL
892 * R300_VAP_PVS_CODE_CNTL_1
893 * See the r5xx docs for instructions on how to use these. */
894 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
895 OUT_CS(R300_PVS_FIRST_INST(0) |
896 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
897 R300_PVS_LAST_INST(instruction_count - 1));
898 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
899 OUT_CS(instruction_count - 1);
900
901 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
902 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
903 for (i = 0; i < code->length; i++) {
904 OUT_CS(code->body.d[i]);
905 }
906
907 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
908 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
909 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
910 R300_PVS_VF_MAX_VTX_NUM(12) |
911 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
912 END_CS;
913 }
914
915 void r300_emit_vs_constant_buffer(struct r300_context* r300,
916 struct rc_constant_list* constants)
917 {
918 int i;
919 struct r300_screen* r300screen = r300_screen(r300->context.screen);
920 CS_LOCALS(r300);
921
922 if (!r300screen->caps->has_tcl) {
923 debug_printf("r300: Implementation error: emit_vertex_shader called,"
924 " but has_tcl is FALSE!\n");
925 return;
926 }
927
928 if (constants->Count == 0)
929 return;
930
931 BEGIN_CS(constants->Count * 4 + 3);
932 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
933 (r300screen->caps->is_r500 ?
934 R500_PVS_CONST_START : R300_PVS_CONST_START));
935 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
936 for (i = 0; i < constants->Count; i++) {
937 const float * data = get_shader_constant(r300,
938 &constants->Constants[i],
939 &r300->shader_constants[PIPE_SHADER_VERTEX]);
940 OUT_CS_32F(data[0]);
941 OUT_CS_32F(data[1]);
942 OUT_CS_32F(data[2]);
943 OUT_CS_32F(data[3]);
944 }
945 END_CS;
946 }
947
948 void r300_emit_viewport_state(struct r300_context* r300,
949 unsigned size, void* state)
950 {
951 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
952 CS_LOCALS(r300);
953
954 if (r300->tcl_bypass) {
955 BEGIN_CS(2); /* XXX tcl_bypass will be removed in gallium anyway */
956 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
957 END_CS;
958 } else {
959 BEGIN_CS(size);
960 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
961 OUT_CS_32F(viewport->xscale);
962 OUT_CS_32F(viewport->xoffset);
963 OUT_CS_32F(viewport->yscale);
964 OUT_CS_32F(viewport->yoffset);
965 OUT_CS_32F(viewport->zscale);
966 OUT_CS_32F(viewport->zoffset);
967 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
968 END_CS;
969 }
970 }
971
972 void r300_emit_texture_count(struct r300_context* r300)
973 {
974 uint32_t tx_enable = 0;
975 int i;
976 CS_LOCALS(r300);
977
978 /* Notice that texture_count and sampler_count are just sizes
979 * of the respective arrays. We still have to check for the individual
980 * elements. */
981 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
982 if (r300->textures[i]) {
983 tx_enable |= 1 << i;
984 }
985 }
986
987 BEGIN_CS(2);
988 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
989 END_CS;
990
991 }
992
993 void r300_emit_ztop_state(struct r300_context* r300,
994 unsigned size, void* state)
995 {
996 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
997 CS_LOCALS(r300);
998
999 BEGIN_CS(size);
1000 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1001 END_CS;
1002 }
1003
1004 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1005 {
1006 CS_LOCALS(r300);
1007
1008 BEGIN_CS(size);
1009 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1010 END_CS;
1011 }
1012
1013 void r300_emit_buffer_validate(struct r300_context *r300,
1014 boolean do_validate_vertex_buffers,
1015 struct pipe_buffer *index_buffer)
1016 {
1017 struct pipe_framebuffer_state* fb =
1018 (struct pipe_framebuffer_state*)r300->fb_state.state;
1019 struct r300_texture* tex;
1020 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1021 struct pipe_vertex_element *velem = r300->vertex_element;
1022 struct pipe_buffer *pbuf;
1023 unsigned i;
1024 boolean invalid = FALSE;
1025
1026 /* Clean out BOs. */
1027 r300->winsys->reset_bos(r300->winsys);
1028
1029 validate:
1030 /* Color buffers... */
1031 for (i = 0; i < fb->nr_cbufs; i++) {
1032 tex = (struct r300_texture*)fb->cbufs[i]->texture;
1033 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1034 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1035 0, RADEON_GEM_DOMAIN_VRAM)) {
1036 r300->context.flush(&r300->context, 0, NULL);
1037 goto validate;
1038 }
1039 }
1040 /* ...depth buffer... */
1041 if (fb->zsbuf) {
1042 tex = (struct r300_texture*)fb->zsbuf->texture;
1043 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1044 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1045 0, RADEON_GEM_DOMAIN_VRAM)) {
1046 r300->context.flush(&r300->context, 0, NULL);
1047 goto validate;
1048 }
1049 }
1050 /* ...textures... */
1051 for (i = 0; i < r300->texture_count; i++) {
1052 tex = r300->textures[i];
1053 if (!tex)
1054 continue;
1055 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1056 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1057 r300->context.flush(&r300->context, 0, NULL);
1058 goto validate;
1059 }
1060 }
1061 /* ...occlusion query buffer... */
1062 if (r300->dirty_state & R300_NEW_QUERY) {
1063 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1064 0, RADEON_GEM_DOMAIN_GTT)) {
1065 r300->context.flush(&r300->context, 0, NULL);
1066 goto validate;
1067 }
1068 }
1069 /* ...vertex buffer for SWTCL path... */
1070 if (r300->vbo) {
1071 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1072 RADEON_GEM_DOMAIN_GTT, 0)) {
1073 r300->context.flush(&r300->context, 0, NULL);
1074 goto validate;
1075 }
1076 }
1077 /* ...vertex buffers for HWTCL path... */
1078 if (do_validate_vertex_buffers) {
1079 for (i = 0; i < r300->vertex_element_count; i++) {
1080 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1081
1082 if (!r300->winsys->add_buffer(r300->winsys, pbuf,
1083 RADEON_GEM_DOMAIN_GTT, 0)) {
1084 r300->context.flush(&r300->context, 0, NULL);
1085 goto validate;
1086 }
1087 }
1088 }
1089 /* ...and index buffer for HWTCL path. */
1090 if (index_buffer) {
1091 if (!r300->winsys->add_buffer(r300->winsys, index_buffer,
1092 RADEON_GEM_DOMAIN_GTT, 0)) {
1093 r300->context.flush(&r300->context, 0, NULL);
1094 goto validate;
1095 }
1096 }
1097
1098 if (!r300->winsys->validate(r300->winsys)) {
1099 r300->context.flush(&r300->context, 0, NULL);
1100 if (invalid) {
1101 /* Well, hell. */
1102 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1103 exit(1);
1104 }
1105 invalid = TRUE;
1106 goto validate;
1107 }
1108 }
1109
1110 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1111 {
1112 struct r300_atom* atom;
1113 unsigned dwords = 0;
1114
1115 foreach(atom, &r300->atom_list) {
1116 if (atom->dirty || atom->always_dirty) {
1117 dwords += atom->size;
1118 }
1119 }
1120
1121 /* XXX This is the compensation for the non-atomized states. */
1122 dwords += 1024;
1123
1124 return dwords;
1125 }
1126
1127 /* Emit all dirty state. */
1128 void r300_emit_dirty_state(struct r300_context* r300)
1129 {
1130 struct r300_screen* r300screen = r300_screen(r300->context.screen);
1131 struct r300_atom* atom;
1132 unsigned i;
1133
1134 if (r300->dirty_state & R300_NEW_QUERY) {
1135 r300_emit_query_start(r300);
1136 r300->dirty_state &= ~R300_NEW_QUERY;
1137 }
1138
1139 foreach(atom, &r300->atom_list) {
1140 if (atom->dirty || atom->always_dirty) {
1141 atom->emit(r300, atom->size, atom->state);
1142 atom->dirty = FALSE;
1143 }
1144 }
1145
1146 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1147 r300_emit_fragment_depth_config(r300, r300->fs);
1148 if (r300screen->caps->is_r500) {
1149 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1150 } else {
1151 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1152 }
1153 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1154 }
1155
1156 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1157 if (r300screen->caps->is_r500) {
1158 r500_emit_fs_constant_buffer(r300,
1159 &r300->fs->shader->code.constants);
1160 } else {
1161 r300_emit_fs_constant_buffer(r300,
1162 &r300->fs->shader->code.constants);
1163 }
1164 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1165 }
1166
1167 /* Samplers and textures are tracked separately but emitted together. */
1168 if (r300->dirty_state &
1169 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1170 r300_emit_texture_count(r300);
1171
1172 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1173 if (r300->dirty_state &
1174 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1175 if (r300->textures[i]) {
1176 r300_emit_texture(r300,
1177 r300->sampler_states[i],
1178 r300->textures[i],
1179 i);
1180 }
1181 r300->dirty_state &=
1182 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1183 }
1184 }
1185 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1186 }
1187
1188 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1189 struct r300_vertex_shader* vs = r300->vs_state.state;
1190 r300_emit_vs_constant_buffer(r300, &vs->code.constants);
1191 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1192 }
1193
1194 /* XXX
1195 assert(r300->dirty_state == 0);
1196 */
1197
1198 /* Finally, emit the VBO. */
1199 /* r300_emit_vertex_buffer(r300); */
1200
1201 r300->dirty_hw++;
1202 }