2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
30 #include "r300_context.h"
33 #include "r300_emit.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
39 void r300_emit_blend_state(struct r300_context
* r300
,
40 unsigned size
, void* state
)
42 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
43 struct pipe_framebuffer_state
* fb
=
44 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
48 WRITE_CS_TABLE(blend
->cb
, size
);
50 WRITE_CS_TABLE(blend
->cb_no_readwrite
, size
);
54 void r300_emit_blend_color_state(struct r300_context
* r300
,
55 unsigned size
, void* state
)
57 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
60 WRITE_CS_TABLE(bc
->cb
, size
);
63 void r300_emit_clip_state(struct r300_context
* r300
,
64 unsigned size
, void* state
)
66 struct r300_clip_state
* clip
= (struct r300_clip_state
*)state
;
69 WRITE_CS_TABLE(clip
->cb
, size
);
72 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
74 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
75 struct pipe_framebuffer_state
* fb
=
76 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
80 WRITE_CS_TABLE(&dsa
->cb_begin
, size
);
82 WRITE_CS_TABLE(dsa
->cb_no_readwrite
, size
);
86 static void get_rc_constant_state(
88 struct r300_context
* r300
,
89 struct rc_constant
* constant
)
91 struct r300_textures_state
* texstate
= r300
->textures_state
.state
;
92 struct r300_texture
*tex
;
94 assert(constant
->Type
== RC_CONSTANT_STATE
);
96 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
97 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
100 switch (constant
->u
.State
[0]) {
101 /* Factor for converting rectangle coords to
102 * normalized coords. Should only show up on non-r500. */
103 case RC_STATE_R300_TEXRECT_FACTOR
:
104 tex
= r300_texture(texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
);
105 vec
[0] = 1.0 / tex
->desc
.width0
;
106 vec
[1] = 1.0 / tex
->desc
.height0
;
111 case RC_STATE_R300_TEXSCALE_FACTOR
:
112 tex
= r300_texture(texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
);
113 /* Add a small number to the texture size to work around rounding errors in hw. */
114 vec
[0] = tex
->desc
.b
.b
.width0
/ (tex
->desc
.width0
+ 0.001f
);
115 vec
[1] = tex
->desc
.b
.b
.height0
/ (tex
->desc
.height0
+ 0.001f
);
116 vec
[2] = tex
->desc
.b
.b
.depth0
/ (tex
->desc
.depth0
+ 0.001f
);
120 case RC_STATE_R300_VIEWPORT_SCALE
:
121 vec
[0] = r300
->viewport
.scale
[0];
122 vec
[1] = r300
->viewport
.scale
[1];
123 vec
[2] = r300
->viewport
.scale
[2];
127 case RC_STATE_R300_VIEWPORT_OFFSET
:
128 vec
[0] = r300
->viewport
.translate
[0];
129 vec
[1] = r300
->viewport
.translate
[1];
130 vec
[2] = r300
->viewport
.translate
[2];
135 fprintf(stderr
, "r300: Implementation error: "
136 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
144 /* Convert a normal single-precision float into the 7.16 format
145 * used by the R300 fragment shader.
147 uint32_t pack_float24(float f
)
155 uint32_t float24
= 0;
162 mantissa
= frexpf(f
, &exponent
);
166 float24
|= (1 << 23);
167 mantissa
= mantissa
* -1.0;
169 /* Handle exponent, bias of 63 */
171 float24
|= (exponent
<< 16);
172 /* Kill 7 LSB of mantissa */
173 float24
|= (u
.u
& 0x7FFFFF) >> 7;
178 void r300_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
180 struct r300_fragment_shader
*fs
= r300_fs(r300
);
183 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
186 void r300_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
188 struct r300_fragment_shader
*fs
= r300_fs(r300
);
189 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
190 unsigned count
= fs
->shader
->externals_count
;
198 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, count
* 4);
199 if (buf
->remap_table
){
200 for (i
= 0; i
< count
; i
++) {
201 float *data
= (float*)&buf
->ptr
[buf
->remap_table
[i
]*4];
202 for (j
= 0; j
< 4; j
++)
203 OUT_CS(pack_float24(data
[j
]));
206 for (i
= 0; i
< count
; i
++)
207 for (j
= 0; j
< 4; j
++)
208 OUT_CS(pack_float24(*(float*)&buf
->ptr
[i
*4+j
]));
214 void r300_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
216 struct r300_fragment_shader
*fs
= r300_fs(r300
);
217 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
219 unsigned count
= fs
->shader
->rc_state_count
;
220 unsigned first
= fs
->shader
->externals_count
;
221 unsigned end
= constants
->Count
;
229 for(i
= first
; i
< end
; ++i
) {
230 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
233 get_rc_constant_state(data
, r300
, &constants
->Constants
[i
]);
235 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
236 for (j
= 0; j
< 4; j
++)
237 OUT_CS(pack_float24(data
[j
]));
243 void r500_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
245 struct r300_fragment_shader
*fs
= r300_fs(r300
);
248 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
251 void r500_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
253 struct r300_fragment_shader
*fs
= r300_fs(r300
);
254 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
255 unsigned count
= fs
->shader
->externals_count
;
262 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
263 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, count
* 4);
264 if (buf
->remap_table
){
265 for (unsigned i
= 0; i
< count
; i
++) {
266 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
267 OUT_CS_TABLE(data
, 4);
270 OUT_CS_TABLE(buf
->ptr
, count
* 4);
275 void r500_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
277 struct r300_fragment_shader
*fs
= r300_fs(r300
);
278 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
280 unsigned count
= fs
->shader
->rc_state_count
;
281 unsigned first
= fs
->shader
->externals_count
;
282 unsigned end
= constants
->Count
;
289 for(i
= first
; i
< end
; ++i
) {
290 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
293 get_rc_constant_state(data
, r300
, &constants
->Constants
[i
]);
295 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
296 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
297 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
298 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
299 OUT_CS_TABLE(data
, 4);
305 void r300_emit_gpu_flush(struct r300_context
*r300
, unsigned size
, void *state
)
307 struct r300_gpu_flush
*gpuflush
= (struct r300_gpu_flush
*)state
;
308 struct pipe_framebuffer_state
* fb
=
309 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
310 uint32_t height
= fb
->height
;
311 uint32_t width
= fb
->width
;
314 if (r300
->cbzb_clear
) {
315 struct r300_surface
*surf
= r300_surface(fb
->cbufs
[0]);
317 height
= surf
->cbzb_height
;
318 width
= surf
->cbzb_width
;
321 DBG(r300
, DBG_SCISSOR
,
322 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
323 width
, height
, r300
->cbzb_clear
? "YES" : "NO");
328 * By writing to the SC registers, SC & US assert idle. */
329 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
330 if (r300
->screen
->caps
.is_r500
) {
332 OUT_CS(((width
- 1) << R300_SCISSORS_X_SHIFT
) |
333 ((height
- 1) << R300_SCISSORS_Y_SHIFT
));
335 OUT_CS((1440 << R300_SCISSORS_X_SHIFT
) |
336 (1440 << R300_SCISSORS_Y_SHIFT
));
337 OUT_CS(((width
+ 1440-1) << R300_SCISSORS_X_SHIFT
) |
338 ((height
+ 1440-1) << R300_SCISSORS_Y_SHIFT
));
341 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
342 OUT_CS_TABLE(gpuflush
->cb_flush_clean
, 6);
346 void r300_emit_aa_state(struct r300_context
*r300
, unsigned size
, void *state
)
348 struct r300_aa_state
*aa
= (struct r300_aa_state
*)state
;
352 OUT_CS_REG(R300_GB_AA_CONFIG
, aa
->aa_config
);
355 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET
, 1);
356 OUT_CS_RELOC(aa
->dest
->cs_buffer
, aa
->dest
->offset
, 0, aa
->dest
->domain
);
358 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_PITCH
, 1);
359 OUT_CS_RELOC(aa
->dest
->cs_buffer
, aa
->dest
->pitch
, 0, aa
->dest
->domain
);
362 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL
, aa
->aaresolve_ctl
);
366 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
368 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
369 struct r300_surface
* surf
;
371 boolean can_hyperz
= r300
->rws
->get_value(r300
->rws
, R300_CAN_HYPERZ
);
376 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
377 * what we usually want. */
378 if (r300
->screen
->caps
.is_r500
) {
379 OUT_CS_REG(R300_RB3D_CCTL
,
380 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
);
382 OUT_CS_REG(R300_RB3D_CCTL
, 0);
385 /* Set up colorbuffers. */
386 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
387 surf
= r300_surface(fb
->cbufs
[i
]);
389 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
+ (4 * i
), 1);
390 OUT_CS_RELOC(surf
->cs_buffer
, surf
->offset
, 0, surf
->domain
);
392 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0
+ (4 * i
), 1);
393 OUT_CS_RELOC(surf
->cs_buffer
, surf
->pitch
, 0, surf
->domain
);
396 /* Set up the ZB part of the CBZB clear. */
397 if (r300
->cbzb_clear
) {
398 surf
= r300_surface(fb
->cbufs
[0]);
400 OUT_CS_REG(R300_ZB_FORMAT
, surf
->cbzb_format
);
402 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
403 OUT_CS_RELOC(surf
->cs_buffer
, surf
->cbzb_midpoint_offset
, 0, surf
->domain
);
405 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
406 OUT_CS_RELOC(surf
->cs_buffer
, surf
->cbzb_pitch
, 0, surf
->domain
);
409 "CBZB clearing cbuf %08x %08x\n", surf
->cbzb_format
,
412 /* Set up a zbuffer. */
413 else if (fb
->zsbuf
) {
414 surf
= r300_surface(fb
->zsbuf
);
416 OUT_CS_REG(R300_ZB_FORMAT
, surf
->format
);
418 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
419 OUT_CS_RELOC(surf
->cs_buffer
, surf
->offset
, 0, surf
->domain
);
421 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
422 OUT_CS_RELOC(surf
->cs_buffer
, surf
->pitch
, 0, surf
->domain
);
426 struct r300_texture
*tex
;
427 int level
= surf
->base
.u
.tex
.level
;
428 tex
= r300_texture(surf
->base
.texture
);
430 surf_pitch
= surf
->pitch
& R300_DEPTHPITCH_MASK
;
432 if (r300
->screen
->caps
.hiz_ram
) {
433 if (tex
->hiz_mem
[level
]) {
434 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, tex
->hiz_mem
[level
]->ofs
<< 2);
435 OUT_CS_REG(R300_ZB_HIZ_PITCH
, surf_pitch
);
437 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, 0);
438 OUT_CS_REG(R300_ZB_HIZ_PITCH
, 0);
441 /* Z Mask RAM. (compressed zbuffer) */
442 if (tex
->zmask_mem
[level
]) {
443 OUT_CS_REG(R300_ZB_ZMASK_OFFSET
, tex
->zmask_mem
[level
]->ofs
<< 2);
444 OUT_CS_REG(R300_ZB_ZMASK_PITCH
, surf_pitch
);
446 OUT_CS_REG(R300_ZB_ZMASK_OFFSET
, 0);
447 OUT_CS_REG(R300_ZB_ZMASK_PITCH
, 0);
455 void r300_emit_hyperz_state(struct r300_context
*r300
,
456 unsigned size
, void *state
)
458 struct r300_hyperz_state
*z
= state
;
461 WRITE_CS_TABLE(&z
->cb_flush_begin
, size
);
463 WRITE_CS_TABLE(&z
->cb_begin
, size
- 2);
466 void r300_emit_hyperz_end(struct r300_context
*r300
)
468 struct r300_hyperz_state z
=
469 *(struct r300_hyperz_state
*)r300
->hyperz_state
.state
;
473 z
.zb_depthclearvalue
= 0;
474 z
.sc_hyperz
= R300_SC_HYPERZ_ADJ_2
;
475 z
.gb_z_peq_config
= 0;
477 r300_emit_hyperz_state(r300
, r300
->hyperz_state
.size
, &z
);
480 void r300_emit_fb_state_pipelined(struct r300_context
*r300
,
481 unsigned size
, void *state
)
483 struct pipe_framebuffer_state
* fb
=
484 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
490 /* Colorbuffer format in the US block.
491 * (must be written after unpipelined regs) */
492 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0
, 4);
493 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
494 OUT_CS(r300_surface(fb
->cbufs
[i
])->format
);
497 OUT_CS(R300_US_OUT_FMT_UNUSED
);
500 /* Multisampling. Depends on framebuffer sample count.
501 * These are pipelined regs and as such cannot be moved
502 * to the AA state. */
503 if (r300
->rws
->get_value(r300
->rws
, R300_VID_DRM_2_3_0
)) {
504 unsigned mspos0
= 0x66666666;
505 unsigned mspos1
= 0x6666666;
507 if (fb
->nr_cbufs
&& fb
->cbufs
[0]->texture
->nr_samples
> 1) {
508 /* Subsample placement. These may not be optimal. */
509 switch (fb
->cbufs
[0]->texture
->nr_samples
) {
527 debug_printf("r300: Bad number of multisamples!\n");
531 OUT_CS_REG_SEQ(R300_GB_MSPOS0
, 2);
538 void r300_emit_query_start(struct r300_context
*r300
, unsigned size
, void*state
)
540 struct r300_query
*query
= r300
->query_current
;
547 if (r300
->screen
->caps
.family
== CHIP_FAMILY_RV530
) {
548 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
550 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
552 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
554 query
->begin_emitted
= TRUE
;
555 query
->flushed
= FALSE
;
558 static void r300_emit_query_end_frag_pipes(struct r300_context
*r300
,
559 struct r300_query
*query
)
561 struct r300_capabilities
* caps
= &r300
->screen
->caps
;
562 struct r300_winsys_cs_buffer
*buf
= r300
->query_current
->cs_buffer
;
565 assert(caps
->num_frag_pipes
);
567 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
568 /* I'm not so sure I like this switch, but it's hard to be elegant
569 * when there's so many special cases...
571 * So here's the basic idea. For each pipe, enable writes to it only,
572 * then put out the relocation for ZPASS_ADDR, taking into account a
573 * 4-byte offset for each pipe. RV380 and older are special; they have
574 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
575 * so there's a chipset cap for that. */
576 switch (caps
->num_frag_pipes
) {
579 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
580 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
581 OUT_CS_RELOC(buf
, (query
->num_results
+ 3) * 4,
585 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
586 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
587 OUT_CS_RELOC(buf
, (query
->num_results
+ 2) * 4,
591 /* As mentioned above, accomodate RV380 and older. */
592 OUT_CS_REG(R300_SU_REG_DEST
,
593 1 << (caps
->high_second_pipe
? 3 : 1));
594 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
595 OUT_CS_RELOC(buf
, (query
->num_results
+ 1) * 4,
599 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
600 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
601 OUT_CS_RELOC(buf
, (query
->num_results
+ 0) * 4,
605 fprintf(stderr
, "r300: Implementation error: Chipset reports %d"
606 " pixel pipes!\n", caps
->num_frag_pipes
);
610 /* And, finally, reset it to normal... */
611 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
615 static void rv530_emit_query_end_single_z(struct r300_context
*r300
,
616 struct r300_query
*query
)
618 struct r300_winsys_cs_buffer
*buf
= r300
->query_current
->cs_buffer
;
622 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
623 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
624 OUT_CS_RELOC(buf
, query
->num_results
* 4, 0, query
->domain
);
625 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
629 static void rv530_emit_query_end_double_z(struct r300_context
*r300
,
630 struct r300_query
*query
)
632 struct r300_winsys_cs_buffer
*buf
= r300
->query_current
->cs_buffer
;
636 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
637 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
638 OUT_CS_RELOC(buf
, (query
->num_results
+ 0) * 4, 0, query
->domain
);
639 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
640 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
641 OUT_CS_RELOC(buf
, (query
->num_results
+ 1) * 4, 0, query
->domain
);
642 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
646 void r300_emit_query_end(struct r300_context
* r300
)
648 struct r300_capabilities
*caps
= &r300
->screen
->caps
;
649 struct r300_query
*query
= r300
->query_current
;
654 if (query
->begin_emitted
== FALSE
)
657 if (caps
->family
== CHIP_FAMILY_RV530
) {
658 if (caps
->num_z_pipes
== 2)
659 rv530_emit_query_end_double_z(r300
, query
);
661 rv530_emit_query_end_single_z(r300
, query
);
663 r300_emit_query_end_frag_pipes(r300
, query
);
665 query
->begin_emitted
= FALSE
;
666 query
->num_results
+= query
->num_pipes
;
668 /* XXX grab all the results and reset the counter. */
669 if (query
->num_results
>= query
->buffer_size
/ 4 - 4) {
670 query
->num_results
= (query
->buffer_size
/ 4) / 2;
671 fprintf(stderr
, "r300: Rewinding OQBO...\n");
675 void r300_emit_invariant_state(struct r300_context
*r300
,
676 unsigned size
, void *state
)
679 WRITE_CS_TABLE(state
, size
);
682 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
684 struct r300_rs_state
* rs
= state
;
688 OUT_CS_TABLE(rs
->cb_main
, RS_STATE_MAIN_SIZE
);
689 if (rs
->polygon_offset_enable
) {
690 if (r300
->zbuffer_bpp
== 16) {
691 OUT_CS_TABLE(rs
->cb_poly_offset_zb16
, 5);
693 OUT_CS_TABLE(rs
->cb_poly_offset_zb24
, 5);
699 void r300_emit_rs_block_state(struct r300_context
* r300
,
700 unsigned size
, void* state
)
702 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
704 /* It's the same for both INST and IP tables */
705 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
708 if (DBG_ON(r300
, DBG_RS_BLOCK
)) {
709 r500_dump_rs_block(rs
);
711 fprintf(stderr
, "r300: RS emit:\n");
713 for (i
= 0; i
< count
; i
++)
714 fprintf(stderr
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
716 for (i
= 0; i
< count
; i
++)
717 fprintf(stderr
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
719 fprintf(stderr
, " : count: 0x%08x inst_count: 0x%08x\n",
720 rs
->count
, rs
->inst_count
);
724 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
725 OUT_CS(rs
->vap_vtx_state_cntl
);
726 OUT_CS(rs
->vap_vsm_vtx_assm
);
727 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
728 OUT_CS(rs
->vap_out_vtx_fmt
[0]);
729 OUT_CS(rs
->vap_out_vtx_fmt
[1]);
730 OUT_CS_REG_SEQ(R300_GB_ENABLE
, 1);
731 OUT_CS(rs
->gb_enable
);
733 if (r300
->screen
->caps
.is_r500
) {
734 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
736 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
738 OUT_CS_TABLE(rs
->ip
, count
);
740 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
742 OUT_CS(rs
->inst_count
);
744 if (r300
->screen
->caps
.is_r500
) {
745 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
747 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
749 OUT_CS_TABLE(rs
->inst
, count
);
753 void r300_emit_scissor_state(struct r300_context
* r300
,
754 unsigned size
, void* state
)
756 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
760 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0
, 2);
761 if (r300
->screen
->caps
.is_r500
) {
762 OUT_CS((scissor
->minx
<< R300_CLIPRECT_X_SHIFT
) |
763 (scissor
->miny
<< R300_CLIPRECT_Y_SHIFT
));
764 OUT_CS(((scissor
->maxx
- 1) << R300_CLIPRECT_X_SHIFT
) |
765 ((scissor
->maxy
- 1) << R300_CLIPRECT_Y_SHIFT
));
767 OUT_CS(((scissor
->minx
+ 1440) << R300_CLIPRECT_X_SHIFT
) |
768 ((scissor
->miny
+ 1440) << R300_CLIPRECT_Y_SHIFT
));
769 OUT_CS(((scissor
->maxx
+ 1440-1) << R300_CLIPRECT_X_SHIFT
) |
770 ((scissor
->maxy
+ 1440-1) << R300_CLIPRECT_Y_SHIFT
));
775 void r300_emit_textures_state(struct r300_context
*r300
,
776 unsigned size
, void *state
)
778 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
779 struct r300_texture_sampler_state
*texstate
;
780 struct r300_texture
*tex
;
785 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
787 for (i
= 0; i
< allstate
->count
; i
++) {
788 if ((1 << i
) & allstate
->tx_enable
) {
789 texstate
= &allstate
->regs
[i
];
790 tex
= r300_texture(allstate
->sampler_views
[i
]->base
.texture
);
792 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter0
);
793 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter1
);
794 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
795 texstate
->border_color
);
797 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
.format0
);
798 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
.format1
);
799 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
.format2
);
801 OUT_CS_REG_SEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
802 OUT_CS_TEX_RELOC(tex
, texstate
->format
.tile_config
, tex
->domain
,
809 static void r300_update_aos_cb(struct r300_context
*r300
, unsigned packet_size
)
811 struct pipe_vertex_buffer
*vb1
, *vb2
, *vbuf
= r300
->vertex_buffer
;
812 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
813 unsigned *hw_format_size
= r300
->velems
->hw_format_size
;
814 unsigned size1
, size2
, aos_count
= r300
->velems
->count
;
818 BEGIN_CB(r300
->aos_cb
, packet_size
);
819 for (i
= 0; i
< aos_count
- 1; i
+= 2) {
820 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
821 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
822 size1
= hw_format_size
[i
];
823 size2
= hw_format_size
[i
+1];
825 OUT_CB(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
826 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
827 OUT_CB(vb1
->buffer_offset
+ velem
[i
].src_offset
);
828 OUT_CB(vb2
->buffer_offset
+ velem
[i
+1].src_offset
);
832 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
833 size1
= hw_format_size
[i
];
835 OUT_CB(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
836 OUT_CB(vb1
->buffer_offset
+ velem
[i
].src_offset
);
840 r300
->aos_dirty
= FALSE
;
843 void r300_emit_aos(struct r300_context
* r300
, int offset
, boolean indexed
)
845 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
846 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
847 struct r300_buffer
*buf
;
849 unsigned aos_count
= r300
->velems
->count
;
850 unsigned packet_size
= (aos_count
* 3 + 1) / 2;
853 BEGIN_CS(2 + packet_size
+ aos_count
* 2);
854 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
855 OUT_CS(aos_count
| (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
858 if (r300
->aos_dirty
) {
859 r300_update_aos_cb(r300
, packet_size
);
861 OUT_CS_TABLE(r300
->aos_cb
, packet_size
);
863 struct pipe_vertex_buffer
*vb1
, *vb2
;
864 unsigned *hw_format_size
= r300
->velems
->hw_format_size
;
865 unsigned size1
, size2
;
867 for (i
= 0; i
< aos_count
- 1; i
+= 2) {
868 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
869 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
870 size1
= hw_format_size
[i
];
871 size2
= hw_format_size
[i
+1];
873 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
874 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
875 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
876 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
880 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
881 size1
= hw_format_size
[i
];
883 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
884 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
888 for (i
= 0; i
< aos_count
; i
++) {
889 buf
= r300_buffer(vbuf
[velem
[i
].vertex_buffer_index
].buffer
);
890 OUT_CS_BUF_RELOC_NO_OFFSET(&buf
->b
.b
, buf
->domain
, 0);
895 void r300_emit_aos_swtcl(struct r300_context
*r300
, boolean indexed
)
899 DBG(r300
, DBG_SWTCL
, "r300: Preparing vertex buffer %p for render, "
900 "vertex size %d\n", r300
->vbo
,
901 r300
->vertex_info
.size
);
902 /* Set the pointer to our vertex buffer. The emitted values are this:
903 * PACKET3 [3D_LOAD_VBPNTR]
905 * FORMAT [size | stride << 8]
906 * OFFSET [offset into BO]
907 * VBPNTR [relocated BO]
910 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
911 OUT_CS(1 | (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
912 OUT_CS(r300
->vertex_info
.size
|
913 (r300
->vertex_info
.size
<< 8));
914 OUT_CS(r300
->draw_vbo_offset
);
915 OUT_CS_BUF_RELOC(r300
->vbo
, 0, r300_buffer(r300
->vbo
)->domain
, 0);
919 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
920 unsigned size
, void* state
)
922 struct r300_vertex_stream_state
*streams
=
923 (struct r300_vertex_stream_state
*)state
;
927 if (DBG_ON(r300
, DBG_PSC
)) {
928 fprintf(stderr
, "r300: PSC emit:\n");
930 for (i
= 0; i
< streams
->count
; i
++) {
931 fprintf(stderr
, " : prog_stream_cntl%d: 0x%08x\n", i
,
932 streams
->vap_prog_stream_cntl
[i
]);
935 for (i
= 0; i
< streams
->count
; i
++) {
936 fprintf(stderr
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
937 streams
->vap_prog_stream_cntl_ext
[i
]);
942 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
943 OUT_CS_TABLE(streams
->vap_prog_stream_cntl
, streams
->count
);
944 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
945 OUT_CS_TABLE(streams
->vap_prog_stream_cntl_ext
, streams
->count
);
949 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
954 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
958 void r300_emit_vap_invariant_state(struct r300_context
*r300
,
959 unsigned size
, void *state
)
962 WRITE_CS_TABLE(state
, size
);
965 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
967 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
968 struct r300_vertex_program_code
* code
= &vs
->code
;
969 struct r300_screen
* r300screen
= r300
->screen
;
970 unsigned instruction_count
= code
->length
/ 4;
972 unsigned vtx_mem_size
= r300screen
->caps
.is_r500
? 128 : 72;
973 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
974 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
975 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
977 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
978 vtx_mem_size
/ output_count
, 10);
979 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 5);
985 /* R300_VAP_PVS_CODE_CNTL_0
986 * R300_VAP_PVS_CONST_CNTL
987 * R300_VAP_PVS_CODE_CNTL_1
988 * See the r5xx docs for instructions on how to use these. */
989 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0
, R300_PVS_FIRST_INST(0) |
990 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
991 R300_PVS_LAST_INST(instruction_count
- 1));
992 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1
, instruction_count
- 1);
994 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
995 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
996 OUT_CS_TABLE(code
->body
.d
, code
->length
);
998 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
999 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
1000 R300_PVS_NUM_FPUS(r300screen
->caps
.num_vert_fpus
) |
1001 R300_PVS_VF_MAX_VTX_NUM(12) |
1002 (r300screen
->caps
.is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
1004 /* Emit flow control instructions. */
1005 if (code
->num_fc_ops
) {
1007 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC
, code
->fc_ops
);
1008 if (r300screen
->caps
.is_r500
) {
1009 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0
, code
->num_fc_ops
* 2);
1010 OUT_CS_TABLE(code
->fc_op_addrs
.r500
, code
->num_fc_ops
* 2);
1012 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0
, code
->num_fc_ops
);
1013 OUT_CS_TABLE(code
->fc_op_addrs
.r300
, code
->num_fc_ops
);
1015 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
, code
->num_fc_ops
);
1016 OUT_CS_TABLE(code
->fc_loop_index
, code
->num_fc_ops
);
1022 void r300_emit_vs_constants(struct r300_context
* r300
,
1023 unsigned size
, void *state
)
1026 ((struct r300_vertex_shader
*)r300
->vs_state
.state
)->externals_count
;
1027 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
1028 struct r300_vertex_shader
*vs
= (struct r300_vertex_shader
*)r300
->vs_state
.state
;
1030 int imm_first
= vs
->externals_count
;
1031 int imm_end
= vs
->code
.constants
.Count
;
1032 int imm_count
= vs
->immediates_count
;
1036 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL
,
1037 R300_PVS_CONST_BASE_OFFSET(buf
->buffer_base
) |
1038 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end
- 1, 0)));
1039 if (vs
->externals_count
) {
1040 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1041 (r300
->screen
->caps
.is_r500
?
1042 R500_PVS_CONST_START
: R300_PVS_CONST_START
) + buf
->buffer_base
);
1043 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, count
* 4);
1044 if (buf
->remap_table
){
1045 for (i
= 0; i
< count
; i
++) {
1046 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
1047 OUT_CS_TABLE(data
, 4);
1050 OUT_CS_TABLE(buf
->ptr
, count
* 4);
1054 /* Emit immediates. */
1056 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1057 (r300
->screen
->caps
.is_r500
?
1058 R500_PVS_CONST_START
: R300_PVS_CONST_START
) +
1059 buf
->buffer_base
+ imm_first
);
1060 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, imm_count
* 4);
1061 for (i
= imm_first
; i
< imm_end
; i
++) {
1062 const float *data
= vs
->code
.constants
.Constants
[i
].u
.Immediate
;
1063 OUT_CS_TABLE(data
, 4);
1069 void r300_emit_viewport_state(struct r300_context
* r300
,
1070 unsigned size
, void* state
)
1072 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
1076 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
1077 OUT_CS_TABLE(&viewport
->xscale
, 6);
1078 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
1082 static void r300_emit_hiz_line_clear(struct r300_context
*r300
, int start
, uint16_t count
, uint32_t val
)
1086 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ
, 2);
1093 static void r300_emit_zmask_line_clear(struct r300_context
*r300
, int start
, uint16_t count
, uint32_t val
)
1097 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK
, 2);
1104 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1106 void r300_emit_hiz_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1108 struct pipe_framebuffer_state
*fb
=
1109 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1110 struct r300_hyperz_state
*z
=
1111 (struct r300_hyperz_state
*)r300
->hyperz_state
.state
;
1112 struct r300_screen
* r300screen
= r300
->screen
;
1113 uint32_t stride
, offset
= 0, height
, offset_shift
;
1114 struct r300_texture
* tex
;
1117 tex
= r300_texture(fb
->zsbuf
->texture
);
1119 offset
= tex
->hiz_mem
[fb
->zsbuf
->u
.tex
.level
]->ofs
;
1120 stride
= tex
->desc
.stride_in_pixels
[fb
->zsbuf
->u
.tex
.level
];
1122 /* convert from pixels to 4x4 blocks */
1123 stride
= ALIGN_DIVUP(stride
, 4);
1125 stride
= ALIGN_DIVUP(stride
, r300screen
->caps
.num_frag_pipes
);
1126 /* there are 4 blocks per dwords */
1127 stride
= ALIGN_DIVUP(stride
, 4);
1129 height
= ALIGN_DIVUP(fb
->zsbuf
->height
, 4);
1132 offset_shift
+= (r300screen
->caps
.num_frag_pipes
/ 2);
1134 for (i
= 0; i
< height
; i
++) {
1135 offset
= i
* stride
;
1136 offset
<<= offset_shift
;
1137 r300_emit_hiz_line_clear(r300
, offset
, stride
, 0xffffffff);
1139 z
->current_func
= -1;
1141 /* Mark the current zbuffer's hiz ram as in use. */
1142 tex
->hiz_in_use
[fb
->zsbuf
->u
.tex
.level
] = TRUE
;
1145 void r300_emit_zmask_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1147 struct pipe_framebuffer_state
*fb
=
1148 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1149 struct r300_screen
* r300screen
= r300
->screen
;
1150 uint32_t stride
, offset
= 0;
1151 struct r300_texture
* tex
;
1153 int mult
, offset_shift
;
1155 tex
= r300_texture(fb
->zsbuf
->texture
);
1156 stride
= tex
->desc
.stride_in_pixels
[fb
->zsbuf
->u
.tex
.level
];
1158 offset
= tex
->zmask_mem
[fb
->zsbuf
->u
.tex
.level
]->ofs
;
1160 if (r300
->z_compression
== RV350_Z_COMPRESS_88
)
1165 height
= ALIGN_DIVUP(fb
->zsbuf
->height
, mult
);
1168 offset_shift
+= (r300screen
->caps
.num_frag_pipes
/ 2);
1169 stride
= ALIGN_DIVUP(stride
, r300screen
->caps
.num_frag_pipes
);
1171 /* okay have width in pixels - divide by block width */
1172 stride
= ALIGN_DIVUP(stride
, mult
);
1173 /* have width in blocks - divide by number of fragment pipes screen width */
1174 /* 16 blocks per dword */
1175 stride
= ALIGN_DIVUP(stride
, 16);
1177 for (i
= 0; i
< height
; i
++) {
1178 offset
= i
* stride
;
1179 offset
<<= offset_shift
;
1180 r300_emit_zmask_line_clear(r300
, offset
, stride
, 0x0);//0xffffffff);
1183 /* Mark the current zbuffer's zmask as in use. */
1184 tex
->zmask_in_use
[fb
->zsbuf
->u
.tex
.level
] = TRUE
;
1187 void r300_emit_ztop_state(struct r300_context
* r300
,
1188 unsigned size
, void* state
)
1190 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
1194 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
1198 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
1203 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
1207 boolean
r300_emit_buffer_validate(struct r300_context
*r300
,
1208 boolean do_validate_vertex_buffers
,
1209 struct pipe_resource
*index_buffer
)
1211 struct pipe_framebuffer_state
* fb
=
1212 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1213 struct r300_textures_state
*texstate
=
1214 (struct r300_textures_state
*)r300
->textures_state
.state
;
1215 struct r300_texture
* tex
;
1216 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
1217 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
1218 struct pipe_resource
*pbuf
;
1221 /* Clean out BOs. */
1222 r300
->rws
->cs_reset_buffers(r300
->cs
);
1224 /* Color buffers... */
1225 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1226 tex
= r300_texture(fb
->cbufs
[i
]->texture
);
1227 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
1228 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->cs_buffer
, 0,
1229 r300_surface(fb
->cbufs
[i
])->domain
);
1231 /* ...depth buffer... */
1233 tex
= r300_texture(fb
->zsbuf
->texture
);
1234 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
1235 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->cs_buffer
, 0,
1236 r300_surface(fb
->zsbuf
)->domain
);
1238 /* ...textures... */
1239 for (i
= 0; i
< texstate
->count
; i
++) {
1240 if (!(texstate
->tx_enable
& (1 << i
))) {
1244 tex
= r300_texture(texstate
->sampler_views
[i
]->base
.texture
);
1245 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->cs_buffer
, tex
->domain
, 0);
1247 /* ...occlusion query buffer... */
1248 if (r300
->query_current
)
1249 r300
->rws
->cs_add_buffer(r300
->cs
, r300
->query_current
->cs_buffer
,
1250 0, r300
->query_current
->domain
);
1251 /* ...vertex buffer for SWTCL path... */
1253 r300
->rws
->cs_add_buffer(r300
->cs
, r300_buffer(r300
->vbo
)->cs_buf
,
1254 r300_buffer(r300
->vbo
)->domain
, 0);
1255 /* ...vertex buffers for HWTCL path... */
1256 if (do_validate_vertex_buffers
) {
1257 for (i
= 0; i
< r300
->velems
->count
; i
++) {
1258 pbuf
= vbuf
[velem
[i
].vertex_buffer_index
].buffer
;
1262 r300
->rws
->cs_add_buffer(r300
->cs
, r300_buffer(pbuf
)->cs_buf
,
1263 r300_buffer(pbuf
)->domain
, 0);
1266 /* ...and index buffer for HWTCL path. */
1268 r300
->rws
->cs_add_buffer(r300
->cs
, r300_buffer(index_buffer
)->cs_buf
,
1269 r300_buffer(index_buffer
)->domain
, 0);
1271 if (!r300
->rws
->cs_validate(r300
->cs
)) {
1278 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
1280 struct r300_atom
* atom
;
1281 unsigned dwords
= 0;
1283 foreach_dirty_atom(r300
, atom
) {
1285 dwords
+= atom
->size
;
1289 /* let's reserve some more, just in case */
1295 unsigned r300_get_num_cs_end_dwords(struct r300_context
*r300
)
1297 unsigned dwords
= 0;
1299 /* Emitted in flush. */
1300 dwords
+= 26; /* emit_query_end */
1301 dwords
+= r300
->hyperz_state
.size
+ 2; /* emit_hyperz_end + zcache flush */
1302 if (r300
->screen
->caps
.index_bias_supported
)
1308 /* Emit all dirty state. */
1309 void r300_emit_dirty_state(struct r300_context
* r300
)
1311 struct r300_atom
*atom
;
1313 foreach_dirty_atom(r300
, atom
) {
1315 atom
->emit(r300
, atom
->size
, atom
->state
);
1316 atom
->dirty
= FALSE
;
1320 r300
->first_dirty
= NULL
;
1321 r300
->last_dirty
= NULL
;