2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23 /* r300_emit: Functions for emitting state. */
25 #include "r300_emit.h"
28 #include "r300_state_derived.h"
31 void r300_emit_blend_state(struct r300_context
* r300
,
32 struct r300_blend_state
* blend
)
36 OUT_CS_REG_SEQ(R300_RB3D_CBLEND
, 2);
37 OUT_CS(blend
->blend_control
);
38 OUT_CS(blend
->alpha_blend_control
);
39 OUT_CS_REG(R300_RB3D_ROPCNTL
, blend
->rop
);
40 OUT_CS_REG(R300_RB3D_DITHER_CTL
, blend
->dither
);
44 void r300_emit_blend_color_state(struct r300_context
* r300
,
45 struct r300_blend_color_state
* bc
)
47 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
50 if (r300screen
->caps
->is_r500
) {
52 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR
, 2);
53 OUT_CS(bc
->blend_color_red_alpha
);
54 OUT_CS(bc
->blend_color_green_blue
);
58 OUT_CS_REG(R300_RB3D_BLEND_COLOR
, bc
->blend_color
);
63 void r300_emit_clip_state(struct r300_context
* r300
,
64 struct pipe_clip_state
* clip
)
67 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
70 if (r300screen
->caps
->has_tcl
) {
71 BEGIN_CS(5 + (6 * 4));
72 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
73 (r300screen
->caps
->is_r500
?
74 R500_PVS_UCP_START
: R300_PVS_UCP_START
));
75 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, 6 * 4);
76 for (i
= 0; i
< 6; i
++) {
77 OUT_CS_32F(clip
->ucp
[i
][0]);
78 OUT_CS_32F(clip
->ucp
[i
][1]);
79 OUT_CS_32F(clip
->ucp
[i
][2]);
80 OUT_CS_32F(clip
->ucp
[i
][3]);
82 OUT_CS_REG(R300_VAP_CLIP_CNTL
, ((1 << clip
->nr
) - 1) |
83 R300_PS_UCP_MODE_CLIP_AS_TRIFAN
);
87 OUT_CS_REG(R300_VAP_CLIP_CNTL
, R300_CLIP_DISABLE
);
93 void r300_emit_dsa_state(struct r300_context
* r300
,
94 struct r300_dsa_state
* dsa
)
96 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
99 BEGIN_CS(r300screen
->caps
->is_r500
? 8 : 8);
100 OUT_CS_REG(R300_FG_ALPHA_FUNC
, dsa
->alpha_function
);
101 /* XXX figure out the r300 counterpart for this */
102 if (r300screen
->caps
->is_r500
) {
103 /* OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference); */
105 OUT_CS_REG_SEQ(R300_ZB_CNTL
, 3);
106 OUT_CS(dsa
->z_buffer_control
);
107 OUT_CS(dsa
->z_stencil_control
);
108 OUT_CS(dsa
->stencil_ref_mask
);
109 OUT_CS_REG(R300_ZB_ZTOP
, r300
->ztop_state
.z_buffer_top
);
110 if (r300screen
->caps
->is_r500
) {
111 /* OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); */
116 static const float * get_shader_constant(
117 struct r300_context
* r300
,
118 struct rc_constant
* constant
,
119 struct r300_constant_buffer
* externals
)
121 static const float zero
[4] = { 0.0, 0.0, 0.0, 0.0 };
122 switch(constant
->Type
) {
123 case RC_CONSTANT_EXTERNAL
:
124 return externals
->constants
[constant
->u
.External
];
126 case RC_CONSTANT_IMMEDIATE
:
127 return constant
->u
.Immediate
;
130 debug_printf("r300: Implementation error: Unhandled constant type %i\n",
136 /* Convert a normal single-precision float into the 7.16 format
137 * used by the R300 fragment shader.
139 static uint32_t pack_float24(float f
)
147 uint32_t float24
= 0;
154 mantissa
= frexpf(f
, &exponent
);
158 float24
|= (1 << 23);
159 mantissa
= mantissa
* -1.0;
161 /* Handle exponent, bias of 63 */
163 float24
|= (exponent
<< 16);
164 /* Kill 7 LSB of mantissa */
165 float24
|= (u
.u
& 0x7FFFFF) >> 7;
170 void r300_emit_fragment_program_code(struct r300_context
* r300
,
171 struct rX00_fragment_program_code
* generic_code
,
172 struct r300_constant_buffer
* externals
)
174 struct r300_fragment_program_code
* code
= &generic_code
->code
.r300
;
175 struct rc_constant_list
* constants
= &generic_code
->constants
;
180 code
->alu
.length
* 4 +
181 (code
->tex
.length
? (1 + code
->tex
.length
) : 0) +
182 (constants
->Count
? (1 + constants
->Count
* 4) : 0));
184 OUT_CS_REG(R300_US_CONFIG
, code
->config
);
185 OUT_CS_REG(R300_US_PIXSIZE
, code
->pixsize
);
186 OUT_CS_REG(R300_US_CODE_OFFSET
, code
->code_offset
);
188 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0
, 4);
189 for(i
= 0; i
< 4; ++i
)
190 OUT_CS(code
->code_addr
[i
]);
192 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0
, code
->alu
.length
);
193 for (i
= 0; i
< code
->alu
.length
; i
++)
194 OUT_CS(code
->alu
.inst
[i
].rgb_inst
);
196 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0
, code
->alu
.length
);
197 for (i
= 0; i
< code
->alu
.length
; i
++)
198 OUT_CS(code
->alu
.inst
[i
].rgb_addr
);
200 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0
, code
->alu
.length
);
201 for (i
= 0; i
< code
->alu
.length
; i
++)
202 OUT_CS(code
->alu
.inst
[i
].alpha_inst
);
204 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0
, code
->alu
.length
);
205 for (i
= 0; i
< code
->alu
.length
; i
++)
206 OUT_CS(code
->alu
.inst
[i
].alpha_addr
);
208 if (code
->tex
.length
) {
209 OUT_CS_REG_SEQ(R300_US_TEX_INST_0
, code
->tex
.length
);
210 for(i
= 0; i
< code
->tex
.length
; ++i
)
211 OUT_CS(code
->tex
.inst
[i
]);
214 if (constants
->Count
) {
215 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, constants
->Count
* 4);
216 for(i
= 0; i
< constants
->Count
; ++i
) {
217 const float * data
= get_shader_constant(r300
, &constants
->Constants
[i
], externals
);
218 OUT_CS(pack_float24(data
[0]));
219 OUT_CS(pack_float24(data
[1]));
220 OUT_CS(pack_float24(data
[2]));
221 OUT_CS(pack_float24(data
[3]));
228 void r500_emit_fragment_program_code(struct r300_context
* r300
,
229 struct rX00_fragment_program_code
* generic_code
,
230 struct r300_constant_buffer
* externals
)
232 struct r500_fragment_program_code
* code
= &generic_code
->code
.r500
;
233 struct rc_constant_list
* constants
= &generic_code
->constants
;
238 ((code
->inst_end
+ 1) * 6) +
239 (constants
->Count
? (3 + (constants
->Count
* 4)) : 0));
240 OUT_CS_REG(R500_US_CONFIG
, 0);
241 OUT_CS_REG(R500_US_PIXSIZE
, code
->max_temp_idx
);
242 OUT_CS_REG(R500_US_CODE_RANGE
,
243 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code
->inst_end
));
244 OUT_CS_REG(R500_US_CODE_OFFSET
, 0);
245 OUT_CS_REG(R500_US_CODE_ADDR
,
246 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code
->inst_end
));
248 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_INSTR
);
249 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, (code
->inst_end
+ 1) * 6);
250 for (i
= 0; i
<= code
->inst_end
; i
++) {
251 OUT_CS(code
->inst
[i
].inst0
);
252 OUT_CS(code
->inst
[i
].inst1
);
253 OUT_CS(code
->inst
[i
].inst2
);
254 OUT_CS(code
->inst
[i
].inst3
);
255 OUT_CS(code
->inst
[i
].inst4
);
256 OUT_CS(code
->inst
[i
].inst5
);
259 if (constants
->Count
) {
260 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
261 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, constants
->Count
* 4);
262 for (i
= 0; i
< constants
->Count
; i
++) {
263 const float * data
= get_shader_constant(r300
, &constants
->Constants
[i
], externals
);
274 void r300_emit_fb_state(struct r300_context
* r300
,
275 struct pipe_framebuffer_state
* fb
)
277 struct r300_texture
* tex
;
282 BEGIN_CS((10 * fb
->nr_cbufs
) + (fb
->zsbuf
? 10 : 0) + 4);
283 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
284 tex
= (struct r300_texture
*)fb
->cbufs
[i
]->texture
;
285 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
286 pixpitch
= r300_texture_get_stride(tex
, 0) / tex
->tex
.block
.size
;
288 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
+ (4 * i
), 1);
289 OUT_CS_RELOC(tex
->buffer
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
291 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0
+ (4 * i
), 1);
292 OUT_CS_RELOC(tex
->buffer
, pixpitch
|
293 r300_translate_colorformat(tex
->tex
.format
), 0,
294 RADEON_GEM_DOMAIN_VRAM
, 0);
296 OUT_CS_REG(R300_US_OUT_FMT_0
+ (4 * i
),
297 r300_translate_out_fmt(fb
->cbufs
[i
]->format
));
301 tex
= (struct r300_texture
*)fb
->zsbuf
->texture
;
302 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
303 pixpitch
= r300_texture_get_stride(tex
, 0) / tex
->tex
.block
.size
;
305 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
306 OUT_CS_RELOC(tex
->buffer
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
308 OUT_CS_REG(R300_ZB_FORMAT
, r300_translate_zsformat(tex
->tex
.format
));
310 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
311 OUT_CS_RELOC(tex
->buffer
, pixpitch
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
314 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT
,
315 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS
|
316 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
317 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
,
318 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
319 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);
323 void r300_emit_query_start(struct r300_context
*r300
)
326 struct r300_capabilities
*caps
= r300_screen(r300
->context
.screen
)->caps
;
327 struct r300_query
*query
= r300
->query_current
;
333 /* XXX This will almost certainly not return good results
334 * for overlapping queries. */
336 if (caps
->family
== CHIP_FAMILY_RV530
) {
337 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
339 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
341 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
343 query
->begin_emitted
= TRUE
;
347 static void r300_emit_query_finish(struct r300_context
*r300
,
348 struct r300_query
*query
)
350 struct r300_capabilities
* caps
= r300_screen(r300
->context
.screen
)->caps
;
353 assert(caps
->num_frag_pipes
);
355 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
356 /* I'm not so sure I like this switch, but it's hard to be elegant
357 * when there's so many special cases...
359 * So here's the basic idea. For each pipe, enable writes to it only,
360 * then put out the relocation for ZPASS_ADDR, taking into account a
361 * 4-byte offset for each pipe. RV380 and older are special; they have
362 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
363 * so there's a chipset cap for that. */
364 switch (caps
->num_frag_pipes
) {
367 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
368 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
369 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 3),
370 0, RADEON_GEM_DOMAIN_GTT
, 0);
373 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
374 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
375 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 2),
376 0, RADEON_GEM_DOMAIN_GTT
, 0);
379 /* As mentioned above, accomodate RV380 and older. */
380 OUT_CS_REG(R300_SU_REG_DEST
,
381 1 << (caps
->high_second_pipe
? 3 : 1));
382 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
383 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 1),
384 0, RADEON_GEM_DOMAIN_GTT
, 0);
387 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
388 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
389 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 0),
390 0, RADEON_GEM_DOMAIN_GTT
, 0);
393 debug_printf("r300: Implementation error: Chipset reports %d"
394 " pixel pipes!\n", caps
->num_frag_pipes
);
398 /* And, finally, reset it to normal... */
399 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
404 static void rv530_emit_query_single(struct r300_context
*r300
,
405 struct r300_query
*query
)
410 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
411 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
412 OUT_CS_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
413 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
417 static void rv530_emit_query_double(struct r300_context
*r300
,
418 struct r300_query
*query
)
423 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
424 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
425 OUT_CS_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
426 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
427 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
428 OUT_CS_RELOC(r300
->oqbo
, query
->offset
+ sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
429 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
433 void r300_emit_query_end(struct r300_context
* r300
)
435 struct r300_capabilities
*caps
= r300_screen(r300
->context
.screen
)->caps
;
436 struct r300_query
*query
= r300
->query_current
;
441 if (query
->begin_emitted
== FALSE
)
444 if (caps
->family
== CHIP_FAMILY_RV530
) {
445 if (caps
->num_z_pipes
== 2)
446 rv530_emit_query_double(r300
, query
);
448 rv530_emit_query_single(r300
, query
);
450 r300_emit_query_finish(r300
, query
);
453 void r300_emit_rs_state(struct r300_context
* r300
, struct r300_rs_state
* rs
)
458 OUT_CS_REG(R300_VAP_CNTL_STATUS
, rs
->vap_control_status
);
459 OUT_CS_REG(R300_GA_POINT_SIZE
, rs
->point_size
);
460 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX
, 2);
461 OUT_CS(rs
->point_minmax
);
462 OUT_CS(rs
->line_control
);
463 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE
, 6);
464 OUT_CS(rs
->depth_scale_front
);
465 OUT_CS(rs
->depth_offset_front
);
466 OUT_CS(rs
->depth_scale_back
);
467 OUT_CS(rs
->depth_offset_back
);
468 OUT_CS(rs
->polygon_offset_enable
);
469 OUT_CS(rs
->cull_mode
);
470 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG
, rs
->line_stipple_config
);
471 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE
, rs
->line_stipple_value
);
472 OUT_CS_REG(R300_GA_COLOR_CONTROL
, rs
->color_control
);
476 void r300_emit_rs_block_state(struct r300_context
* r300
,
477 struct r300_rs_block
* rs
)
480 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
484 if (r300screen
->caps
->is_r500
) {
485 OUT_CS_REG_SEQ(R500_RS_IP_0
, 8);
487 OUT_CS_REG_SEQ(R300_RS_IP_0
, 8);
489 for (i
= 0; i
< 8; i
++) {
491 /* debug_printf("ip %d: 0x%08x\n", i, rs->ip[i]); */
494 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
496 OUT_CS(rs
->inst_count
);
498 if (r300screen
->caps
->is_r500
) {
499 OUT_CS_REG_SEQ(R500_RS_INST_0
, 8);
501 OUT_CS_REG_SEQ(R300_RS_INST_0
, 8);
503 for (i
= 0; i
< 8; i
++) {
505 /* debug_printf("inst %d: 0x%08x\n", i, rs->inst[i]); */
508 /* debug_printf("count: 0x%08x inst_count: 0x%08x\n", rs->count,
509 * rs->inst_count); */
514 void r300_emit_scissor_state(struct r300_context
* r300
,
515 struct r300_scissor_state
* scissor
)
520 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
521 OUT_CS(scissor
->scissor_top_left
);
522 OUT_CS(scissor
->scissor_bottom_right
);
526 void r300_emit_texture(struct r300_context
* r300
,
527 struct r300_sampler_state
* sampler
,
528 struct r300_texture
* tex
,
534 OUT_CS_REG(R300_TX_FILTER0_0
+ (offset
* 4), sampler
->filter0
|
536 OUT_CS_REG(R300_TX_FILTER1_0
+ (offset
* 4), sampler
->filter1
);
537 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (offset
* 4), sampler
->border_color
);
539 OUT_CS_REG(R300_TX_FORMAT0_0
+ (offset
* 4), tex
->state
.format0
);
540 OUT_CS_REG(R300_TX_FORMAT1_0
+ (offset
* 4), tex
->state
.format1
);
541 OUT_CS_REG(R300_TX_FORMAT2_0
+ (offset
* 4), tex
->state
.format2
);
542 OUT_CS_REG_SEQ(R300_TX_OFFSET_0
+ (offset
* 4), 1);
543 OUT_CS_RELOC(tex
->buffer
, 0,
544 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0, 0);
548 void r300_emit_vertex_buffer(struct r300_context
* r300
)
552 DBG(r300
, DBG_DRAW
, "r300: Preparing vertex buffer %p for render, "
553 "vertex size %d\n", r300
->vbo
,
554 r300
->vertex_info
->vinfo
.size
);
555 /* Set the pointer to our vertex buffer. The emitted values are this:
556 * PACKET3 [3D_LOAD_VBPNTR]
558 * FORMAT [size | stride << 8]
559 * OFFSET [offset into BO]
560 * VBPNTR [relocated BO]
563 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
565 OUT_CS(r300
->vertex_info
->vinfo
.size
|
566 (r300
->vertex_info
->vinfo
.size
<< 8));
567 OUT_CS(r300
->vbo_offset
);
568 OUT_CS_RELOC(r300
->vbo
, 0, RADEON_GEM_DOMAIN_GTT
, 0, 0);
572 void r300_emit_vertex_format_state(struct r300_context
* r300
)
578 OUT_CS_REG(R300_VAP_VTX_SIZE
, r300
->vertex_info
->vinfo
.size
);
580 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
581 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[0]);
582 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[1]);
583 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
584 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[2]);
585 OUT_CS(r300
->vertex_info
->vinfo
.hwfmt
[3]);
586 /* for (i = 0; i < 4; i++) {
587 * debug_printf("hwfmt%d: 0x%08x\n", i,
588 * r300->vertex_info->vinfo.hwfmt[i]);
591 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, 8);
592 for (i
= 0; i
< 8; i
++) {
593 OUT_CS(r300
->vertex_info
->vap_prog_stream_cntl
[i
]);
594 /* debug_printf("prog_stream_cntl%d: 0x%08x\n", i,
595 * r300->vertex_info->vap_prog_stream_cntl[i]); */
597 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, 8);
598 for (i
= 0; i
< 8; i
++) {
599 OUT_CS(r300
->vertex_info
->vap_prog_stream_cntl_ext
[i
]);
600 /* debug_printf("prog_stream_cntl_ext%d: 0x%08x\n", i,
601 * r300->vertex_info->vap_prog_stream_cntl_ext[i]); */
606 void r300_emit_vertex_program_code(struct r300_context
* r300
,
607 struct r300_vertex_program_code
* code
,
608 struct r300_constant_buffer
* constants
)
611 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
612 unsigned instruction_count
= code
->length
/ 4;
615 if (!r300screen
->caps
->has_tcl
) {
616 debug_printf("r300: Implementation error: emit_vertex_shader called,"
617 " but has_tcl is FALSE!\n");
621 if (code
->constants
.Count
) {
622 BEGIN_CS(14 + code
->length
+ (code
->constants
.Count
* 4));
624 BEGIN_CS(11 + code
->length
);
627 /* R300_VAP_PVS_CODE_CNTL_0
628 * R300_VAP_PVS_CONST_CNTL
629 * R300_VAP_PVS_CODE_CNTL_1
630 * See the r5xx docs for instructions on how to use these.
631 * XXX these could be optimized to select better values... */
632 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0
, 3);
633 OUT_CS(R300_PVS_FIRST_INST(0) |
634 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
635 R300_PVS_LAST_INST(instruction_count
- 1));
636 OUT_CS(R300_PVS_MAX_CONST_ADDR(code
->constants
.Count
- 1));
637 OUT_CS(instruction_count
- 1);
639 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
640 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
641 for (i
= 0; i
< code
->length
; i
++)
642 OUT_CS(code
->body
.d
[i
]);
644 if (code
->constants
.Count
) {
645 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
646 (r300screen
->caps
->is_r500
?
647 R500_PVS_CONST_START
: R300_PVS_CONST_START
));
648 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->constants
.Count
* 4);
649 for (i
= 0; i
< code
->constants
.Count
; i
++) {
650 const float * data
= get_shader_constant(r300
, &code
->constants
.Constants
[i
], constants
);
658 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(10) |
659 R300_PVS_NUM_CNTLRS(5) |
660 R300_PVS_NUM_FPUS(r300screen
->caps
->num_vert_fpus
) |
661 R300_PVS_VF_MAX_VTX_NUM(12));
662 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
666 void r300_emit_vertex_shader(struct r300_context
* r300
,
667 struct r300_vertex_shader
* vs
)
669 r300_emit_vertex_program_code(r300
, &vs
->code
, &r300
->shader_constants
[PIPE_SHADER_VERTEX
]);
672 void r300_emit_viewport_state(struct r300_context
* r300
,
673 struct r300_viewport_state
* viewport
)
678 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
679 OUT_CS_32F(viewport
->xscale
);
680 OUT_CS_32F(viewport
->xoffset
);
681 OUT_CS_32F(viewport
->yscale
);
682 OUT_CS_32F(viewport
->yoffset
);
683 OUT_CS_32F(viewport
->zscale
);
684 OUT_CS_32F(viewport
->zoffset
);
686 if (r300
->rs_state
->enable_vte
) {
687 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
689 OUT_CS_REG(R300_VAP_VTE_CNTL
, 0);
694 void r300_flush_textures(struct r300_context
* r300
)
699 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
700 OUT_CS_REG(R300_TX_ENABLE
, (1 << r300
->texture_count
) - 1);
704 /* Emit all dirty state. */
705 void r300_emit_dirty_state(struct r300_context
* r300
)
707 struct r300_screen
* r300screen
= r300_screen(r300
->context
.screen
);
708 struct r300_texture
* tex
;
709 int i
, dirty_tex
= 0;
710 boolean invalid
= FALSE
;
712 if (!(r300
->dirty_state
)) {
716 r300_update_derived_state(r300
);
719 r300
->winsys
->reset_bos(r300
->winsys
);
723 /* Color buffers... */
724 for (i
= 0; i
< r300
->framebuffer_state
.nr_cbufs
; i
++) {
725 tex
= (struct r300_texture
*)r300
->framebuffer_state
.cbufs
[i
]->texture
;
726 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
727 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
728 0, RADEON_GEM_DOMAIN_VRAM
)) {
729 r300
->context
.flush(&r300
->context
, 0, NULL
);
733 /* ...depth buffer... */
734 if (r300
->framebuffer_state
.zsbuf
) {
735 tex
= (struct r300_texture
*)r300
->framebuffer_state
.zsbuf
->texture
;
736 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
737 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
738 0, RADEON_GEM_DOMAIN_VRAM
)) {
739 r300
->context
.flush(&r300
->context
, 0, NULL
);
744 for (i
= 0; i
< r300
->texture_count
; i
++) {
745 tex
= r300
->textures
[i
];
748 if (!r300
->winsys
->add_buffer(r300
->winsys
, tex
->buffer
,
749 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0)) {
750 r300
->context
.flush(&r300
->context
, 0, NULL
);
754 /* ...occlusion query buffer... */
755 if (!r300
->winsys
->add_buffer(r300
->winsys
, r300
->oqbo
,
756 0, RADEON_GEM_DOMAIN_GTT
)) {
757 r300
->context
.flush(&r300
->context
, 0, NULL
);
760 /* ...and vertex buffer. */
762 if (!r300
->winsys
->add_buffer(r300
->winsys
, r300
->vbo
,
763 RADEON_GEM_DOMAIN_GTT
, 0)) {
764 r300
->context
.flush(&r300
->context
, 0, NULL
);
768 debug_printf("No VBO while emitting dirty state!\n");
770 if (!r300
->winsys
->validate(r300
->winsys
)) {
771 r300
->context
.flush(&r300
->context
, 0, NULL
);
774 debug_printf("r300: Stuck in validation loop, gonna quit now.");
781 if (r300
->dirty_state
& R300_NEW_QUERY
) {
782 r300_emit_query_start(r300
);
783 r300
->dirty_state
&= ~R300_NEW_QUERY
;
786 if (r300
->dirty_state
& R300_NEW_BLEND
) {
787 r300_emit_blend_state(r300
, r300
->blend_state
);
788 r300
->dirty_state
&= ~R300_NEW_BLEND
;
791 if (r300
->dirty_state
& R300_NEW_BLEND_COLOR
) {
792 r300_emit_blend_color_state(r300
, r300
->blend_color_state
);
793 r300
->dirty_state
&= ~R300_NEW_BLEND_COLOR
;
796 if (r300
->dirty_state
& R300_NEW_CLIP
) {
797 r300_emit_clip_state(r300
, &r300
->clip_state
);
798 r300
->dirty_state
&= ~R300_NEW_CLIP
;
801 if (r300
->dirty_state
& R300_NEW_DSA
) {
802 r300_emit_dsa_state(r300
, r300
->dsa_state
);
803 r300
->dirty_state
&= ~R300_NEW_DSA
;
806 if (r300
->dirty_state
& R300_NEW_FRAGMENT_SHADER
) {
807 if (r300screen
->caps
->is_r500
) {
808 r500_emit_fragment_program_code(r300
, &r300
->fs
->code
, &r300
->shader_constants
[PIPE_SHADER_FRAGMENT
]);
810 r300_emit_fragment_program_code(r300
, &r300
->fs
->code
, &r300
->shader_constants
[PIPE_SHADER_FRAGMENT
]);
812 r300
->dirty_state
&= ~R300_NEW_FRAGMENT_SHADER
;
815 if (r300
->dirty_state
& R300_NEW_FRAMEBUFFERS
) {
816 r300_emit_fb_state(r300
, &r300
->framebuffer_state
);
817 r300
->dirty_state
&= ~R300_NEW_FRAMEBUFFERS
;
820 if (r300
->dirty_state
& R300_NEW_RASTERIZER
) {
821 r300_emit_rs_state(r300
, r300
->rs_state
);
822 r300
->dirty_state
&= ~R300_NEW_RASTERIZER
;
825 if (r300
->dirty_state
& R300_NEW_RS_BLOCK
) {
826 r300_emit_rs_block_state(r300
, r300
->rs_block
);
827 r300
->dirty_state
&= ~R300_NEW_RS_BLOCK
;
830 if (r300
->dirty_state
& R300_NEW_SCISSOR
) {
831 r300_emit_scissor_state(r300
, r300
->scissor_state
);
832 r300
->dirty_state
&= ~R300_NEW_SCISSOR
;
835 /* Samplers and textures are tracked separately but emitted together. */
836 if (r300
->dirty_state
&
837 (R300_ANY_NEW_SAMPLERS
| R300_ANY_NEW_TEXTURES
)) {
838 for (i
= 0; i
< MIN2(r300
->sampler_count
, r300
->texture_count
); i
++) {
839 if (r300
->dirty_state
&
840 ((R300_NEW_SAMPLER
<< i
) | (R300_NEW_TEXTURE
<< i
))) {
841 if (r300
->textures
[i
])
842 r300_emit_texture(r300
,
843 r300
->sampler_states
[i
],
847 ~((R300_NEW_SAMPLER
<< i
) | (R300_NEW_TEXTURE
<< i
));
851 r300
->dirty_state
&= ~(R300_ANY_NEW_SAMPLERS
| R300_ANY_NEW_TEXTURES
);
854 if (r300
->dirty_state
& R300_NEW_VIEWPORT
) {
855 r300_emit_viewport_state(r300
, r300
->viewport_state
);
856 r300
->dirty_state
&= ~R300_NEW_VIEWPORT
;
860 r300_flush_textures(r300
);
863 if (r300
->dirty_state
& R300_NEW_VERTEX_FORMAT
) {
864 r300_emit_vertex_format_state(r300
);
865 r300
->dirty_state
&= ~R300_NEW_VERTEX_FORMAT
;
868 if (r300
->dirty_state
& R300_NEW_VERTEX_SHADER
) {
869 r300_emit_vertex_shader(r300
, r300
->vs
);
870 r300
->dirty_state
&= ~R300_NEW_VERTEX_SHADER
;
874 assert(r300->dirty_state == 0);
877 /* Finally, emit the VBO. */
878 r300_emit_vertex_buffer(r300
);