r300g: consolidate common render code into one function
[mesa.git] / src / gallium / drivers / r300 / r300_render.c
1 /*
2 * Copyright 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 /* r300_render: Vertex and index buffer primitive emission. Contains both
24 * HW TCL fastpath rendering, and SW TCL Draw-assisted rendering. */
25
26 #include "draw/draw_context.h"
27 #include "draw/draw_vbuf.h"
28
29 #include "util/u_inlines.h"
30
31 #include "util/u_format.h"
32 #include "util/u_memory.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35
36 #include "r300_cs.h"
37 #include "r300_context.h"
38 #include "r300_screen_buffer.h"
39 #include "r300_emit.h"
40 #include "r300_reg.h"
41 #include "r300_render.h"
42 #include "r300_state_derived.h"
43
44 static uint32_t r300_translate_primitive(unsigned prim)
45 {
46 switch (prim) {
47 case PIPE_PRIM_POINTS:
48 return R300_VAP_VF_CNTL__PRIM_POINTS;
49 case PIPE_PRIM_LINES:
50 return R300_VAP_VF_CNTL__PRIM_LINES;
51 case PIPE_PRIM_LINE_LOOP:
52 return R300_VAP_VF_CNTL__PRIM_LINE_LOOP;
53 case PIPE_PRIM_LINE_STRIP:
54 return R300_VAP_VF_CNTL__PRIM_LINE_STRIP;
55 case PIPE_PRIM_TRIANGLES:
56 return R300_VAP_VF_CNTL__PRIM_TRIANGLES;
57 case PIPE_PRIM_TRIANGLE_STRIP:
58 return R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP;
59 case PIPE_PRIM_TRIANGLE_FAN:
60 return R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN;
61 case PIPE_PRIM_QUADS:
62 return R300_VAP_VF_CNTL__PRIM_QUADS;
63 case PIPE_PRIM_QUAD_STRIP:
64 return R300_VAP_VF_CNTL__PRIM_QUAD_STRIP;
65 case PIPE_PRIM_POLYGON:
66 return R300_VAP_VF_CNTL__PRIM_POLYGON;
67 default:
68 return 0;
69 }
70 }
71
72 static uint32_t r300_provoking_vertex_fixes(struct r300_context *r300,
73 unsigned mode)
74 {
75 struct r300_rs_state* rs = (struct r300_rs_state*)r300->rs_state.state;
76 uint32_t color_control = rs->color_control;
77
78 /* By default (see r300_state.c:r300_create_rs_state) color_control is
79 * initialized to provoking the first vertex.
80 *
81 * Triangle fans must be reduced to the second vertex, not the first, in
82 * Gallium flatshade-first mode, as per the GL spec.
83 * (http://www.opengl.org/registry/specs/ARB/provoking_vertex.txt)
84 *
85 * Quads never provoke correctly in flatshade-first mode. The first
86 * vertex is never considered as provoking, so only the second, third,
87 * and fourth vertices can be selected, and both "third" and "last" modes
88 * select the fourth vertex. This is probably due to D3D lacking quads.
89 *
90 * Similarly, polygons reduce to the first, not the last, vertex, when in
91 * "last" mode, and all other modes start from the second vertex.
92 *
93 * ~ C.
94 */
95
96 if (rs->rs.flatshade_first) {
97 switch (mode) {
98 case PIPE_PRIM_TRIANGLE_FAN:
99 color_control |= R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_SECOND;
100 break;
101 case PIPE_PRIM_QUADS:
102 case PIPE_PRIM_QUAD_STRIP:
103 case PIPE_PRIM_POLYGON:
104 color_control |= R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST;
105 break;
106 default:
107 color_control |= R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_FIRST;
108 break;
109 }
110 } else {
111 color_control |= R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST;
112 }
113
114 return color_control;
115 }
116
117 static void r500_emit_index_offset(struct r300_context *r300, int index_bias)
118 {
119 CS_LOCALS(r300);
120
121 if (r300->screen->caps.is_r500 &&
122 r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
123 BEGIN_CS(2);
124 OUT_CS_REG(R500_VAP_INDEX_OFFSET,
125 (index_bias & 0xFFFFFF) | (index_bias < 0 ? 1<<24 : 0));
126 END_CS;
127 } else {
128 if (index_bias) {
129 fprintf(stderr, "r300: Non-zero index bias is unsupported "
130 "on this hardware.\n");
131 assert(0);
132 }
133 }
134 }
135
136 enum r300_prepare_flags {
137 PREP_FIRST_DRAW = (1 << 0),
138 PREP_VALIDATE_VBOS = (1 << 1),
139 PREP_EMIT_AOS = (1 << 2),
140 PREP_INDEXED = (1 << 3)
141 };
142
143 /* Check if the requested number of dwords is available in the CS and
144 * if not, flush. Then validate buffers and emit dirty state.
145 * Return TRUE if flush occured. */
146 static void r300_prepare_for_rendering(struct r300_context *r300,
147 enum r300_prepare_flags flags,
148 struct pipe_resource *index_buffer,
149 unsigned cs_dwords,
150 unsigned aos_offset,
151 int index_bias)
152 {
153 boolean flushed = FALSE;
154 boolean first_draw = flags & PREP_FIRST_DRAW;
155 boolean emit_aos = flags & PREP_EMIT_AOS;
156
157 /* Stencil ref fallback. */
158 if (r300->stencil_ref_bf_fallback) {
159 cs_dwords = cs_dwords * 2 + 10;
160 }
161
162 /* Add dirty state, index offset, and AOS. */
163 if (first_draw) {
164 cs_dwords += r300_get_num_dirty_dwords(r300);
165
166 if (r300->screen->caps.is_r500)
167 cs_dwords += 2; /* emit_index_offset */
168
169 if (emit_aos)
170 cs_dwords += 55; /* emit_aos */
171 }
172
173 /* Emitted in flush. */
174 cs_dwords += 26; /* emit_query_end */
175
176 /* Reserve requested CS space. */
177 if (!r300->rws->check_cs(r300->rws, cs_dwords)) {
178 r300->context.flush(&r300->context, 0, NULL);
179 flushed = TRUE;
180 }
181
182 /* Validate buffers and emit dirty state if needed. */
183 if (first_draw || flushed) {
184 r300_emit_buffer_validate(r300, flags & PREP_VALIDATE_VBOS, index_buffer);
185 r300_emit_dirty_state(r300);
186 r500_emit_index_offset(r300, index_bias);
187 if (emit_aos)
188 r300_emit_aos(r300, aos_offset, flags & PREP_INDEXED);
189 }
190 }
191
192 static boolean immd_is_good_idea(struct r300_context *r300,
193 unsigned count)
194 {
195 struct pipe_vertex_element* velem;
196 struct pipe_vertex_buffer* vbuf;
197 boolean checked[PIPE_MAX_ATTRIBS] = {0};
198 unsigned vertex_element_count = r300->velems->count;
199 unsigned i, vbi;
200
201 if (count > 10 || DBG_ON(r300, DBG_NO_IMMD)) {
202 return FALSE;
203 }
204
205 /* We shouldn't map buffers referenced by CS, busy buffers,
206 * and ones placed in VRAM. */
207 /* XXX Check for VRAM buffers. */
208 for (i = 0; i < vertex_element_count; i++) {
209 velem = &r300->velems->velem[i];
210 vbi = velem->vertex_buffer_index;
211
212 if (!checked[vbi]) {
213 vbuf = &r300->vertex_buffer[vbi];
214
215 if (r300_buffer_is_referenced(&r300->context,
216 vbuf->buffer,
217 R300_REF_CS | R300_REF_HW)) {
218 /* It's a very bad idea to map it... */
219 return FALSE;
220 }
221 checked[vbi] = TRUE;
222 }
223 }
224 return TRUE;
225 }
226
227 /*****************************************************************************
228 * The emission of draw packets for r500. Older GPUs may use these functions *
229 * after resolving fallback issues (e.g. stencil ref two-sided). *
230 ****************************************************************************/
231
232 void r500_emit_draw_arrays_immediate(struct r300_context *r300,
233 unsigned mode,
234 unsigned start,
235 unsigned count)
236 {
237 struct pipe_vertex_element* velem;
238 struct pipe_vertex_buffer* vbuf;
239 unsigned vertex_element_count = r300->velems->count;
240 unsigned i, v, vbi, dw, elem_offset, dwords;
241
242 /* Size of the vertex, in dwords. */
243 unsigned vertex_size = 0;
244
245 /* Offsets of the attribute, in dwords, from the start of the vertex. */
246 unsigned offset[PIPE_MAX_ATTRIBS];
247
248 /* Size of the vertex element, in dwords. */
249 unsigned size[PIPE_MAX_ATTRIBS];
250
251 /* Stride to the same attrib in the next vertex in the vertex buffer,
252 * in dwords. */
253 unsigned stride[PIPE_MAX_ATTRIBS] = {0};
254
255 /* Mapped vertex buffers. */
256 uint32_t* map[PIPE_MAX_ATTRIBS] = {0};
257 struct pipe_transfer* transfer[PIPE_MAX_ATTRIBS] = {NULL};
258
259 CS_LOCALS(r300);
260
261 /* Calculate the vertex size, offsets, strides etc. and map the buffers. */
262 for (i = 0; i < vertex_element_count; i++) {
263 velem = &r300->velems->velem[i];
264 offset[i] = velem->src_offset / 4;
265 size[i] = util_format_get_blocksize(velem->src_format) / 4;
266 vertex_size += size[i];
267 vbi = velem->vertex_buffer_index;
268
269 /* Map the buffer. */
270 if (!map[vbi]) {
271 vbuf = &r300->vertex_buffer[vbi];
272 map[vbi] = (uint32_t*)pipe_buffer_map(&r300->context,
273 vbuf->buffer,
274 PIPE_TRANSFER_READ,
275 &transfer[vbi]);
276 map[vbi] += vbuf->buffer_offset / 4;
277 stride[vbi] = vbuf->stride / 4;
278 }
279 }
280
281 dwords = 9 + count * vertex_size;
282
283 r300_prepare_for_rendering(r300, PREP_FIRST_DRAW, NULL, dwords, 0, 0);
284
285 BEGIN_CS(dwords);
286 OUT_CS_REG(R300_GA_COLOR_CONTROL,
287 r300_provoking_vertex_fixes(r300, mode));
288 OUT_CS_REG(R300_VAP_VTX_SIZE, vertex_size);
289 OUT_CS_REG_SEQ(R300_VAP_VF_MAX_VTX_INDX, 2);
290 OUT_CS(count - 1);
291 OUT_CS(0);
292 OUT_CS_PKT3(R300_PACKET3_3D_DRAW_IMMD_2, count * vertex_size);
293 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED | (count << 16) |
294 r300_translate_primitive(mode));
295
296 /* Emit vertices. */
297 for (v = 0; v < count; v++) {
298 for (i = 0; i < vertex_element_count; i++) {
299 velem = &r300->velems->velem[i];
300 vbi = velem->vertex_buffer_index;
301 elem_offset = offset[i] + stride[vbi] * (v + start);
302
303 for (dw = 0; dw < size[i]; dw++) {
304 OUT_CS(map[vbi][elem_offset + dw]);
305 }
306 }
307 }
308 END_CS;
309
310 /* Unmap buffers. */
311 for (i = 0; i < vertex_element_count; i++) {
312 vbi = r300->velems->velem[i].vertex_buffer_index;
313
314 if (map[vbi]) {
315 vbuf = &r300->vertex_buffer[vbi];
316 pipe_buffer_unmap(&r300->context, vbuf->buffer, transfer[vbi]);
317 map[vbi] = NULL;
318 }
319 }
320 }
321
322 void r500_emit_draw_arrays(struct r300_context *r300,
323 unsigned mode,
324 unsigned count)
325 {
326 boolean alt_num_verts = count > 65535;
327 CS_LOCALS(r300);
328
329 if (count >= (1 << 24)) {
330 fprintf(stderr, "r300: Got a huge number of vertices: %i, "
331 "refusing to render.\n", count);
332 return;
333 }
334
335 BEGIN_CS(7 + (alt_num_verts ? 2 : 0));
336 if (alt_num_verts) {
337 OUT_CS_REG(R500_VAP_ALT_NUM_VERTICES, count);
338 }
339 OUT_CS_REG(R300_GA_COLOR_CONTROL,
340 r300_provoking_vertex_fixes(r300, mode));
341 OUT_CS_REG_SEQ(R300_VAP_VF_MAX_VTX_INDX, 2);
342 OUT_CS(count - 1);
343 OUT_CS(0);
344 OUT_CS_PKT3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
345 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (count << 16) |
346 r300_translate_primitive(mode) |
347 (alt_num_verts ? R500_VAP_VF_CNTL__USE_ALT_NUM_VERTS : 0));
348 END_CS;
349 }
350
351 void r500_emit_draw_elements(struct r300_context *r300,
352 struct pipe_resource* indexBuffer,
353 unsigned indexSize,
354 unsigned minIndex,
355 unsigned maxIndex,
356 unsigned mode,
357 unsigned start,
358 unsigned count)
359 {
360 uint32_t count_dwords;
361 uint32_t offset_dwords = indexSize * start / sizeof(uint32_t);
362 boolean alt_num_verts = count > 65535;
363 CS_LOCALS(r300);
364
365 if (count >= (1 << 24)) {
366 fprintf(stderr, "r300: Got a huge number of vertices: %i, "
367 "refusing to render.\n", count);
368 return;
369 }
370
371 maxIndex = MIN2(maxIndex, r300->vertex_buffer_max_index);
372
373 DBG(r300, DBG_DRAW, "r300: Indexbuf of %u indices, min %u max %u\n",
374 count, minIndex, maxIndex);
375
376 BEGIN_CS(13 + (alt_num_verts ? 2 : 0));
377 if (alt_num_verts) {
378 OUT_CS_REG(R500_VAP_ALT_NUM_VERTICES, count);
379 }
380 OUT_CS_REG(R300_GA_COLOR_CONTROL,
381 r300_provoking_vertex_fixes(r300, mode));
382 OUT_CS_REG_SEQ(R300_VAP_VF_MAX_VTX_INDX, 2);
383 OUT_CS(maxIndex);
384 OUT_CS(minIndex);
385 OUT_CS_PKT3(R300_PACKET3_3D_DRAW_INDX_2, 0);
386 if (indexSize == 4) {
387 count_dwords = count;
388 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | (count << 16) |
389 R300_VAP_VF_CNTL__INDEX_SIZE_32bit |
390 r300_translate_primitive(mode) |
391 (alt_num_verts ? R500_VAP_VF_CNTL__USE_ALT_NUM_VERTS : 0));
392 } else {
393 count_dwords = (count + 1) / 2;
394 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | (count << 16) |
395 r300_translate_primitive(mode) |
396 (alt_num_verts ? R500_VAP_VF_CNTL__USE_ALT_NUM_VERTS : 0));
397 }
398
399 /* INDX_BUFFER is a truly special packet3.
400 * Unlike most other packet3, where the offset is after the count,
401 * the order is reversed, so the relocation ends up carrying the
402 * size of the indexbuf instead of the offset.
403 */
404 OUT_CS_PKT3(R300_PACKET3_INDX_BUFFER, 2);
405 OUT_CS(R300_INDX_BUFFER_ONE_REG_WR | (R300_VAP_PORT_IDX0 >> 2) |
406 (0 << R300_INDX_BUFFER_SKIP_SHIFT));
407 OUT_CS(offset_dwords << 2);
408 OUT_CS_BUF_RELOC(indexBuffer, count_dwords,
409 RADEON_GEM_DOMAIN_GTT, 0, 0);
410
411 END_CS;
412 }
413
414 /*****************************************************************************
415 * The emission of draw packets for r300 which take care of the two-sided *
416 * stencil ref fallback and call r500's functions. *
417 ****************************************************************************/
418
419 /* Set drawing for front faces. */
420 static void r300_begin_stencil_ref_fallback(struct r300_context *r300)
421 {
422 struct r300_rs_state *rs = (struct r300_rs_state*)r300->rs_state.state;
423 CS_LOCALS(r300);
424
425 BEGIN_CS(2);
426 OUT_CS_REG(R300_SU_CULL_MODE, rs->cull_mode | R300_CULL_BACK);
427 END_CS;
428 }
429
430 /* Set drawing for back faces. */
431 static void r300_switch_stencil_ref_side(struct r300_context *r300)
432 {
433 struct r300_rs_state *rs = (struct r300_rs_state*)r300->rs_state.state;
434 struct r300_dsa_state *dsa = (struct r300_dsa_state*)r300->dsa_state.state;
435 CS_LOCALS(r300);
436
437 BEGIN_CS(4);
438 OUT_CS_REG(R300_SU_CULL_MODE, rs->cull_mode | R300_CULL_FRONT);
439 OUT_CS_REG(R300_ZB_STENCILREFMASK,
440 dsa->stencil_ref_bf | r300->stencil_ref.ref_value[1]);
441 END_CS;
442 }
443
444 /* Restore the original state. */
445 static void r300_end_stencil_ref_fallback(struct r300_context *r300)
446 {
447 struct r300_rs_state *rs = (struct r300_rs_state*)r300->rs_state.state;
448 struct r300_dsa_state *dsa = (struct r300_dsa_state*)r300->dsa_state.state;
449 CS_LOCALS(r300);
450
451 BEGIN_CS(4);
452 OUT_CS_REG(R300_SU_CULL_MODE, rs->cull_mode);
453 OUT_CS_REG(R300_ZB_STENCILREFMASK,
454 dsa->stencil_ref_mask | r300->stencil_ref.ref_value[0]);
455 END_CS;
456 }
457
458 void r300_emit_draw_arrays_immediate(struct r300_context *r300,
459 unsigned mode,
460 unsigned start,
461 unsigned count)
462 {
463 if (!r300->stencil_ref_bf_fallback) {
464 r500_emit_draw_arrays_immediate(r300, mode, start, count);
465 } else {
466 r300_begin_stencil_ref_fallback(r300);
467 r500_emit_draw_arrays_immediate(r300, mode, start, count);
468 r300_switch_stencil_ref_side(r300);
469 r500_emit_draw_arrays_immediate(r300, mode, start, count);
470 r300_end_stencil_ref_fallback(r300);
471 }
472 }
473
474 void r300_emit_draw_arrays(struct r300_context *r300,
475 unsigned mode,
476 unsigned count)
477 {
478 if (!r300->stencil_ref_bf_fallback) {
479 r500_emit_draw_arrays(r300, mode, count);
480 } else {
481 r300_begin_stencil_ref_fallback(r300);
482 r500_emit_draw_arrays(r300, mode, count);
483 r300_switch_stencil_ref_side(r300);
484 r500_emit_draw_arrays(r300, mode, count);
485 r300_end_stencil_ref_fallback(r300);
486 }
487 }
488
489 void r300_emit_draw_elements(struct r300_context *r300,
490 struct pipe_resource* indexBuffer,
491 unsigned indexSize,
492 unsigned minIndex,
493 unsigned maxIndex,
494 unsigned mode,
495 unsigned start,
496 unsigned count)
497 {
498 if (!r300->stencil_ref_bf_fallback) {
499 r500_emit_draw_elements(r300, indexBuffer, indexSize,
500 minIndex, maxIndex, mode, start, count);
501 } else {
502 r300_begin_stencil_ref_fallback(r300);
503 r500_emit_draw_elements(r300, indexBuffer, indexSize,
504 minIndex, maxIndex, mode, start, count);
505 r300_switch_stencil_ref_side(r300);
506 r500_emit_draw_elements(r300, indexBuffer, indexSize,
507 minIndex, maxIndex, mode, start, count);
508 r300_end_stencil_ref_fallback(r300);
509 }
510 }
511
512 static void r300_shorten_ubyte_elts(struct r300_context* r300,
513 struct pipe_resource** elts,
514 unsigned start,
515 unsigned count)
516 {
517 struct pipe_context* context = &r300->context;
518 struct pipe_screen* screen = r300->context.screen;
519 struct pipe_resource* new_elts;
520 unsigned char *in_map;
521 unsigned short *out_map;
522 struct pipe_transfer *src_transfer, *dst_transfer;
523 unsigned i;
524
525 new_elts = pipe_buffer_create(screen,
526 PIPE_BIND_INDEX_BUFFER,
527 2 * count);
528
529 in_map = pipe_buffer_map(context, *elts, PIPE_TRANSFER_READ, &src_transfer);
530 out_map = pipe_buffer_map(context, new_elts, PIPE_TRANSFER_WRITE, &dst_transfer);
531
532 in_map += start;
533
534 for (i = 0; i < count; i++) {
535 *out_map = (unsigned short)*in_map;
536 in_map++;
537 out_map++;
538 }
539
540 pipe_buffer_unmap(context, *elts, src_transfer);
541 pipe_buffer_unmap(context, new_elts, dst_transfer);
542
543 *elts = new_elts;
544 }
545
546 static void r300_align_ushort_elts(struct r300_context *r300,
547 struct pipe_resource **elts,
548 unsigned start, unsigned count)
549 {
550 struct pipe_context* context = &r300->context;
551 struct pipe_transfer *in_transfer = NULL;
552 struct pipe_transfer *out_transfer = NULL;
553 struct pipe_resource* new_elts;
554 unsigned short *in_map;
555 unsigned short *out_map;
556
557 new_elts = pipe_buffer_create(context->screen,
558 PIPE_BIND_INDEX_BUFFER,
559 2 * count);
560
561 in_map = pipe_buffer_map(context, *elts,
562 PIPE_TRANSFER_READ, &in_transfer);
563 out_map = pipe_buffer_map(context, new_elts,
564 PIPE_TRANSFER_WRITE, &out_transfer);
565
566 memcpy(out_map, in_map+start, 2 * count);
567
568 pipe_buffer_unmap(context, *elts, in_transfer);
569 pipe_buffer_unmap(context, new_elts, out_transfer);
570
571 *elts = new_elts;
572 }
573
574 /* This is the fast-path drawing & emission for HW TCL. */
575 void r300_draw_range_elements(struct pipe_context* pipe,
576 struct pipe_resource* indexBuffer,
577 unsigned indexSize,
578 int indexBias,
579 unsigned minIndex,
580 unsigned maxIndex,
581 unsigned mode,
582 unsigned start,
583 unsigned count)
584 {
585 struct r300_context* r300 = r300_context(pipe);
586 struct pipe_resource* orgIndexBuffer = indexBuffer;
587 boolean alt_num_verts = r300->screen->caps.is_r500 &&
588 count > 65536 &&
589 r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0);
590 unsigned short_count;
591
592 if (r300->skip_rendering) {
593 return;
594 }
595
596 if (!u_trim_pipe_prim(mode, &count)) {
597 return;
598 }
599
600 if (indexSize == 1) {
601 r300_shorten_ubyte_elts(r300, &indexBuffer, start, count);
602 indexSize = 2;
603 start = 0;
604 } else if (indexSize == 2 && start % 2 != 0) {
605 r300_align_ushort_elts(r300, &indexBuffer, start, count);
606 start = 0;
607 }
608
609 r300_update_derived_state(r300);
610 r300_upload_index_buffer(r300, &indexBuffer, indexSize, start, count);
611
612 /* 15 dwords for emit_draw_elements */
613 r300_prepare_for_rendering(r300,
614 PREP_FIRST_DRAW | PREP_VALIDATE_VBOS | PREP_EMIT_AOS | PREP_INDEXED,
615 indexBuffer, 15, 0, indexBias);
616
617 u_upload_flush(r300->upload_vb);
618 u_upload_flush(r300->upload_ib);
619 if (alt_num_verts || count <= 65535) {
620 r300->emit_draw_elements(r300, indexBuffer, indexSize,
621 minIndex, maxIndex, mode, start, count);
622 } else {
623 do {
624 short_count = MIN2(count, 65534);
625 r300->emit_draw_elements(r300, indexBuffer, indexSize,
626 minIndex, maxIndex,
627 mode, start, short_count);
628
629 start += short_count;
630 count -= short_count;
631
632 /* 15 dwords for emit_draw_elements */
633 if (count) {
634 r300_prepare_for_rendering(r300,
635 PREP_VALIDATE_VBOS | PREP_EMIT_AOS | PREP_INDEXED,
636 indexBuffer, 15, 0, indexBias);
637 }
638 } while (count);
639 }
640
641 if (indexBuffer != orgIndexBuffer) {
642 pipe_resource_reference( &indexBuffer, NULL );
643 }
644 }
645
646 /* Simple helpers for context setup. Should probably be moved to util. */
647 void r300_draw_elements(struct pipe_context* pipe,
648 struct pipe_resource* indexBuffer,
649 unsigned indexSize, int indexBias, unsigned mode,
650 unsigned start, unsigned count)
651 {
652 struct r300_context *r300 = r300_context(pipe);
653
654 pipe->draw_range_elements(pipe, indexBuffer, indexSize, indexBias,
655 0, r300->vertex_buffer_max_index,
656 mode, start, count);
657 }
658
659 void r300_draw_arrays(struct pipe_context* pipe, unsigned mode,
660 unsigned start, unsigned count)
661 {
662 struct r300_context* r300 = r300_context(pipe);
663 boolean alt_num_verts = r300->screen->caps.is_r500 &&
664 count > 65536 &&
665 r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0);
666 unsigned short_count;
667
668 if (r300->skip_rendering) {
669 return;
670 }
671
672 if (!u_trim_pipe_prim(mode, &count)) {
673 return;
674 }
675
676 r300_update_derived_state(r300);
677
678 if (immd_is_good_idea(r300, count)) {
679 r300->emit_draw_arrays_immediate(r300, mode, start, count);
680 } else {
681 /* 9 spare dwords for emit_draw_arrays. */
682 r300_prepare_for_rendering(r300, PREP_FIRST_DRAW | PREP_VALIDATE_VBOS | PREP_EMIT_AOS,
683 NULL, 9, start, 0);
684
685 if (alt_num_verts || count <= 65535) {
686 r300->emit_draw_arrays(r300, mode, count);
687 } else {
688 do {
689 short_count = MIN2(count, 65535);
690 r300->emit_draw_arrays(r300, mode, short_count);
691
692 start += short_count;
693 count -= short_count;
694
695 /* 9 spare dwords for emit_draw_arrays. */
696 if (count) {
697 r300_prepare_for_rendering(r300,
698 PREP_VALIDATE_VBOS | PREP_EMIT_AOS, NULL, 9,
699 start, 0);
700 }
701 } while (count);
702 }
703 u_upload_flush(r300->upload_vb);
704 }
705 }
706
707 /****************************************************************************
708 * The rest of this file is for SW TCL rendering only. Please be polite and *
709 * keep these functions separated so that they are easier to locate. ~C. *
710 ***************************************************************************/
711
712 /* SW TCL arrays, using Draw. */
713 void r300_swtcl_draw_arrays(struct pipe_context* pipe,
714 unsigned mode,
715 unsigned start,
716 unsigned count)
717 {
718 struct r300_context* r300 = r300_context(pipe);
719 struct pipe_transfer *vb_transfer[PIPE_MAX_ATTRIBS];
720 int i;
721
722 if (r300->skip_rendering) {
723 return;
724 }
725
726 if (!u_trim_pipe_prim(mode, &count)) {
727 return;
728 }
729
730 for (i = 0; i < r300->vertex_buffer_count; i++) {
731 void* buf = pipe_buffer_map(pipe,
732 r300->vertex_buffer[i].buffer,
733 PIPE_TRANSFER_READ,
734 &vb_transfer[i]);
735 draw_set_mapped_vertex_buffer(r300->draw, i, buf);
736 }
737
738 draw_set_mapped_element_buffer(r300->draw, 0, 0, NULL);
739
740 draw_arrays(r300->draw, mode, start, count);
741
742 for (i = 0; i < r300->vertex_buffer_count; i++) {
743 pipe_buffer_unmap(pipe, r300->vertex_buffer[i].buffer,
744 vb_transfer[i]);
745 draw_set_mapped_vertex_buffer(r300->draw, i, NULL);
746 }
747 }
748
749 /* SW TCL elements, using Draw. */
750 void r300_swtcl_draw_range_elements(struct pipe_context* pipe,
751 struct pipe_resource* indexBuffer,
752 unsigned indexSize,
753 int indexBias,
754 unsigned minIndex,
755 unsigned maxIndex,
756 unsigned mode,
757 unsigned start,
758 unsigned count)
759 {
760 struct r300_context* r300 = r300_context(pipe);
761 struct pipe_transfer *vb_transfer[PIPE_MAX_ATTRIBS];
762 struct pipe_transfer *ib_transfer;
763 int i;
764 void* indices;
765
766 if (r300->skip_rendering) {
767 return;
768 }
769
770 if (!u_trim_pipe_prim(mode, &count)) {
771 return;
772 }
773
774 for (i = 0; i < r300->vertex_buffer_count; i++) {
775 void* buf = pipe_buffer_map(pipe,
776 r300->vertex_buffer[i].buffer,
777 PIPE_TRANSFER_READ,
778 &vb_transfer[i]);
779 draw_set_mapped_vertex_buffer(r300->draw, i, buf);
780 }
781
782 indices = pipe_buffer_map(pipe, indexBuffer,
783 PIPE_TRANSFER_READ, &ib_transfer);
784 draw_set_mapped_element_buffer_range(r300->draw, indexSize, indexBias,
785 minIndex, maxIndex, indices);
786
787 draw_arrays(r300->draw, mode, start, count);
788
789 for (i = 0; i < r300->vertex_buffer_count; i++) {
790 pipe_buffer_unmap(pipe, r300->vertex_buffer[i].buffer,
791 vb_transfer[i]);
792 draw_set_mapped_vertex_buffer(r300->draw, i, NULL);
793 }
794
795 pipe_buffer_unmap(pipe, indexBuffer,
796 ib_transfer);
797 draw_set_mapped_element_buffer_range(r300->draw, 0, 0,
798 start, start + count - 1,
799 NULL);
800 }
801
802 /* Object for rendering using Draw. */
803 struct r300_render {
804 /* Parent class */
805 struct vbuf_render base;
806
807 /* Pipe context */
808 struct r300_context* r300;
809
810 /* Vertex information */
811 size_t vertex_size;
812 unsigned prim;
813 unsigned hwprim;
814
815 /* VBO */
816 struct pipe_resource* vbo;
817 size_t vbo_size;
818 size_t vbo_offset;
819 size_t vbo_max_used;
820 void * vbo_ptr;
821
822 struct pipe_transfer *vbo_transfer;
823 };
824
825 static INLINE struct r300_render*
826 r300_render(struct vbuf_render* render)
827 {
828 return (struct r300_render*)render;
829 }
830
831 static const struct vertex_info*
832 r300_render_get_vertex_info(struct vbuf_render* render)
833 {
834 struct r300_render* r300render = r300_render(render);
835 struct r300_context* r300 = r300render->r300;
836
837 r300_update_derived_state(r300);
838
839 return &r300->vertex_info;
840 }
841
842 static boolean r300_render_allocate_vertices(struct vbuf_render* render,
843 ushort vertex_size,
844 ushort count)
845 {
846 struct r300_render* r300render = r300_render(render);
847 struct r300_context* r300 = r300render->r300;
848 struct pipe_screen* screen = r300->context.screen;
849 size_t size = (size_t)vertex_size * (size_t)count;
850
851 if (size + r300render->vbo_offset > r300render->vbo_size)
852 {
853 pipe_resource_reference(&r300->vbo, NULL);
854 r300render->vbo = pipe_buffer_create(screen,
855 PIPE_BIND_VERTEX_BUFFER,
856 R300_MAX_DRAW_VBO_SIZE);
857 r300render->vbo_offset = 0;
858 r300render->vbo_size = R300_MAX_DRAW_VBO_SIZE;
859 }
860
861 r300render->vertex_size = vertex_size;
862 r300->vbo = r300render->vbo;
863 r300->vbo_offset = r300render->vbo_offset;
864
865 return (r300render->vbo) ? TRUE : FALSE;
866 }
867
868 static void* r300_render_map_vertices(struct vbuf_render* render)
869 {
870 struct r300_render* r300render = r300_render(render);
871
872 r300render->vbo_ptr = pipe_buffer_map(&r300render->r300->context,
873 r300render->vbo,
874 PIPE_TRANSFER_WRITE,
875 &r300render->vbo_transfer);
876
877 return ((uint8_t*)r300render->vbo_ptr + r300render->vbo_offset);
878 }
879
880 static void r300_render_unmap_vertices(struct vbuf_render* render,
881 ushort min,
882 ushort max)
883 {
884 struct r300_render* r300render = r300_render(render);
885 struct pipe_context* context = &r300render->r300->context;
886 CS_LOCALS(r300render->r300);
887 BEGIN_CS(2);
888 OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, max);
889 END_CS;
890
891 r300render->vbo_max_used = MAX2(r300render->vbo_max_used,
892 r300render->vertex_size * (max + 1));
893 pipe_buffer_unmap(context, r300render->vbo, r300render->vbo_transfer);
894 }
895
896 static void r300_render_release_vertices(struct vbuf_render* render)
897 {
898 struct r300_render* r300render = r300_render(render);
899
900 r300render->vbo_offset += r300render->vbo_max_used;
901 r300render->vbo_max_used = 0;
902 }
903
904 static boolean r300_render_set_primitive(struct vbuf_render* render,
905 unsigned prim)
906 {
907 struct r300_render* r300render = r300_render(render);
908
909 r300render->prim = prim;
910 r300render->hwprim = r300_translate_primitive(prim);
911
912 return TRUE;
913 }
914
915 static void r500_render_draw_arrays(struct vbuf_render* render,
916 unsigned start,
917 unsigned count)
918 {
919 struct r300_render* r300render = r300_render(render);
920 struct r300_context* r300 = r300render->r300;
921
922 CS_LOCALS(r300);
923
924 r300_prepare_for_rendering(r300, PREP_FIRST_DRAW, NULL, 2, 0, 0);
925
926 DBG(r300, DBG_DRAW, "r300: Doing vbuf render, count %d\n", count);
927
928 BEGIN_CS(2);
929 OUT_CS_PKT3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
930 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (count << 16) |
931 r300render->hwprim);
932 END_CS;
933 }
934
935 static void r500_render_draw_elements(struct vbuf_render* render,
936 const ushort* indices,
937 uint count)
938 {
939 struct r300_render* r300render = r300_render(render);
940 struct r300_context* r300 = r300render->r300;
941 int i;
942 unsigned dwords = 2 + (count+1)/2;
943
944 CS_LOCALS(r300);
945
946 r300_prepare_for_rendering(r300, PREP_FIRST_DRAW, NULL, dwords, 0, 0);
947
948 BEGIN_CS(dwords);
949 OUT_CS_PKT3(R300_PACKET3_3D_DRAW_INDX_2, (count+1)/2);
950 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | (count << 16) |
951 r300render->hwprim);
952 for (i = 0; i < count-1; i += 2) {
953 OUT_CS(indices[i+1] << 16 | indices[i]);
954 }
955 if (count % 2) {
956 OUT_CS(indices[count-1]);
957 }
958 END_CS;
959 }
960
961 static void r300_render_draw_arrays(struct vbuf_render* render,
962 unsigned start,
963 unsigned count)
964 {
965 struct r300_context* r300 = r300_render(render)->r300;
966
967 if (!r300->stencil_ref_bf_fallback) {
968 r500_render_draw_arrays(render, start, count);
969 } else {
970 r300_begin_stencil_ref_fallback(r300);
971 r500_render_draw_arrays(render, start, count);
972 r300_switch_stencil_ref_side(r300);
973 r500_render_draw_arrays(render, start, count);
974 r300_end_stencil_ref_fallback(r300);
975 }
976 }
977
978 static void r300_render_draw_elements(struct vbuf_render* render,
979 const ushort* indices,
980 uint count)
981 {
982 struct r300_context* r300 = r300_render(render)->r300;
983
984 if (!r300->stencil_ref_bf_fallback) {
985 r500_render_draw_elements(render, indices, count);
986 } else {
987 r300_begin_stencil_ref_fallback(r300);
988 r500_render_draw_elements(render, indices, count);
989 r300_switch_stencil_ref_side(r300);
990 r500_render_draw_elements(render, indices, count);
991 r300_end_stencil_ref_fallback(r300);
992 }
993 }
994
995 static void r300_render_destroy(struct vbuf_render* render)
996 {
997 FREE(render);
998 }
999
1000 static struct vbuf_render* r300_render_create(struct r300_context* r300)
1001 {
1002 struct r300_render* r300render = CALLOC_STRUCT(r300_render);
1003
1004 r300render->r300 = r300;
1005
1006 /* XXX find real numbers plz */
1007 r300render->base.max_vertex_buffer_bytes = 128 * 1024;
1008 r300render->base.max_indices = 16 * 1024;
1009
1010 r300render->base.get_vertex_info = r300_render_get_vertex_info;
1011 r300render->base.allocate_vertices = r300_render_allocate_vertices;
1012 r300render->base.map_vertices = r300_render_map_vertices;
1013 r300render->base.unmap_vertices = r300_render_unmap_vertices;
1014 r300render->base.set_primitive = r300_render_set_primitive;
1015 if (r300->screen->caps.is_r500) {
1016 r300render->base.draw_elements = r500_render_draw_elements;
1017 r300render->base.draw_arrays = r500_render_draw_arrays;
1018 } else {
1019 r300render->base.draw_elements = r300_render_draw_elements;
1020 r300render->base.draw_arrays = r300_render_draw_arrays;
1021 }
1022 r300render->base.release_vertices = r300_render_release_vertices;
1023 r300render->base.destroy = r300_render_destroy;
1024
1025 r300render->vbo = NULL;
1026 r300render->vbo_size = 0;
1027 r300render->vbo_offset = 0;
1028
1029 return &r300render->base;
1030 }
1031
1032 struct draw_stage* r300_draw_stage(struct r300_context* r300)
1033 {
1034 struct vbuf_render* render;
1035 struct draw_stage* stage;
1036
1037 render = r300_render_create(r300);
1038
1039 if (!render) {
1040 return NULL;
1041 }
1042
1043 stage = draw_vbuf_stage(r300->draw, render);
1044
1045 if (!stage) {
1046 render->destroy(render);
1047 return NULL;
1048 }
1049
1050 draw_set_render(r300->draw, render);
1051
1052 return stage;
1053 }