winsys/radeon: hook up the new DRM_RADEON_GEM_WAIT ioctl
[mesa.git] / src / gallium / drivers / r300 / r300_screen.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "util/u_format.h"
25 #include "util/u_format_s3tc.h"
26 #include "util/u_memory.h"
27 #include "os/os_time.h"
28 #include "vl/vl_decoder.h"
29 #include "vl/vl_video_buffer.h"
30
31 #include "r300_context.h"
32 #include "r300_texture.h"
33 #include "r300_screen_buffer.h"
34 #include "r300_state_inlines.h"
35 #include "r300_public.h"
36
37 #include "draw/draw_context.h"
38
39 /* Return the identifier behind whom the brave coders responsible for this
40 * amalgamation of code, sweat, and duct tape, routinely obscure their names.
41 *
42 * ...I should have just put "Corbin Simpson", but I'm not that cool.
43 *
44 * (Or egotistical. Yet.) */
45 static const char* r300_get_vendor(struct pipe_screen* pscreen)
46 {
47 return "X.Org R300 Project";
48 }
49
50 static const char* chip_families[] = {
51 "ATI R300",
52 "ATI R350",
53 "ATI RV350",
54 "ATI RV370",
55 "ATI RV380",
56 "ATI RS400",
57 "ATI RC410",
58 "ATI RS480",
59 "ATI R420",
60 "ATI R423",
61 "ATI R430",
62 "ATI R480",
63 "ATI R481",
64 "ATI RV410",
65 "ATI RS600",
66 "ATI RS690",
67 "ATI RS740",
68 "ATI RV515",
69 "ATI R520",
70 "ATI RV530",
71 "ATI R580",
72 "ATI RV560",
73 "ATI RV570"
74 };
75
76 static const char* r300_get_name(struct pipe_screen* pscreen)
77 {
78 struct r300_screen* r300screen = r300_screen(pscreen);
79
80 return chip_families[r300screen->caps.family];
81 }
82
83 static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
84 {
85 struct r300_screen* r300screen = r300_screen(pscreen);
86 boolean is_r500 = r300screen->caps.is_r500;
87
88 switch (param) {
89 /* Supported features (boolean caps). */
90 case PIPE_CAP_NPOT_TEXTURES:
91 case PIPE_CAP_TWO_SIDED_STENCIL:
92 case PIPE_CAP_GLSL:
93 /* I'll be frank. This is a lie.
94 *
95 * We don't truly support GLSL on any of this driver's chipsets.
96 * To be fair, no chipset supports the full GLSL specification
97 * to the best of our knowledge, but some of the less esoteric
98 * features are still missing here.
99 *
100 * Rather than cripple ourselves intentionally, I'm going to set
101 * this flag, and as Gallium's interface continues to change, I
102 * hope that this single monolithic GLSL enable can slowly get
103 * split down into many different pieces and the state tracker
104 * will handle fallbacks transparently, like it should.
105 *
106 * ~ C.
107 */
108 case PIPE_CAP_ANISOTROPIC_FILTER:
109 case PIPE_CAP_POINT_SPRITE:
110 case PIPE_CAP_OCCLUSION_QUERY:
111 case PIPE_CAP_TEXTURE_SHADOW_MAP:
112 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
113 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
114 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
115 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
116 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
117 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
118 return 1;
119
120 /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
121 case PIPE_CAP_TEXTURE_SWIZZLE:
122 return util_format_s3tc_enabled ? r300screen->caps.dxtc_swizzle : 1;
123
124 /* Supported on r500 only. */
125 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
126 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
127 case PIPE_CAP_SM3:
128 return is_r500 ? 1 : 0;
129
130 /* Unsupported features. */
131 case PIPE_CAP_TIMER_QUERY:
132 case PIPE_CAP_DUAL_SOURCE_BLEND:
133 case PIPE_CAP_INDEP_BLEND_ENABLE:
134 case PIPE_CAP_INDEP_BLEND_FUNC:
135 case PIPE_CAP_DEPTH_CLAMP:
136 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
137 case PIPE_CAP_SHADER_STENCIL_EXPORT:
138 case PIPE_CAP_ARRAY_TEXTURES:
139 case PIPE_CAP_TGSI_INSTANCEID:
140 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
141 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
142 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
143 case PIPE_CAP_SEAMLESS_CUBE_MAP:
144 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
145 case PIPE_CAP_SCALED_RESOLVE:
146 return 0;
147
148 /* SWTCL-only features. */
149 case PIPE_CAP_STREAM_OUTPUT:
150 case PIPE_CAP_PRIMITIVE_RESTART:
151 return !r300screen->caps.has_tcl;
152
153 /* Texturing. */
154 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
155 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
156 return r300screen->caps.num_tex_units;
157 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
158 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
159 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
160 /* 13 == 4096, 12 == 2048 */
161 return is_r500 ? 13 : 12;
162
163 /* Render targets. */
164 case PIPE_CAP_MAX_RENDER_TARGETS:
165 return 4;
166
167 default:
168 debug_printf("r300: Warning: Unknown CAP %d in get_param.\n",
169 param);
170 return 0;
171 }
172 }
173
174 static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
175 {
176 struct r300_screen* r300screen = r300_screen(pscreen);
177 boolean is_r400 = r300screen->caps.is_r400;
178 boolean is_r500 = r300screen->caps.is_r500;
179
180 switch (shader)
181 {
182 case PIPE_SHADER_FRAGMENT:
183 switch (param)
184 {
185 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
186 return is_r500 || is_r400 ? 512 : 96;
187 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
188 return is_r500 || is_r400 ? 512 : 64;
189 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
190 return is_r500 || is_r400 ? 512 : 32;
191 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
192 return is_r500 ? 511 : 4;
193 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
194 return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
195 /* Fragment shader limits. */
196 case PIPE_SHADER_CAP_MAX_INPUTS:
197 /* 2 colors + 8 texcoords are always supported
198 * (minus fog and wpos).
199 *
200 * R500 has the ability to turn 3rd and 4th color into
201 * additional texcoords but there is no two-sided color
202 * selection then. However the facing bit can be used instead. */
203 return 10;
204 case PIPE_SHADER_CAP_MAX_CONSTS:
205 return is_r500 ? 256 : 32;
206 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
207 return 1;
208 case PIPE_SHADER_CAP_MAX_TEMPS:
209 return is_r500 ? 128 : is_r400 ? 64 : 32;
210 case PIPE_SHADER_CAP_MAX_ADDRS:
211 return 0;
212 case PIPE_SHADER_CAP_MAX_PREDS:
213 return is_r500 ? 1 : 0;
214 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
215 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
216 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
217 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
218 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
219 case PIPE_SHADER_CAP_SUBROUTINES:
220 case PIPE_SHADER_CAP_INTEGERS:
221 return 0;
222 }
223 break;
224 case PIPE_SHADER_VERTEX:
225 if (!r300screen->caps.has_tcl) {
226 return draw_get_shader_param(shader, param);
227 }
228
229 switch (param)
230 {
231 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
232 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
233 return is_r500 ? 1024 : 256;
234 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
235 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
236 return 0;
237 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
238 return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
239 case PIPE_SHADER_CAP_MAX_INPUTS:
240 return 16;
241 case PIPE_SHADER_CAP_MAX_CONSTS:
242 return 256;
243 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
244 return 1;
245 case PIPE_SHADER_CAP_MAX_TEMPS:
246 return 32;
247 case PIPE_SHADER_CAP_MAX_ADDRS:
248 return 1; /* XXX guessed */
249 case PIPE_SHADER_CAP_MAX_PREDS:
250 return is_r500 ? 4 : 0; /* XXX guessed. */
251 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
252 return 1;
253 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
254 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
255 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
256 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
257 case PIPE_SHADER_CAP_SUBROUTINES:
258 case PIPE_SHADER_CAP_INTEGERS:
259 return 0;
260 }
261 break;
262 default:
263 break;
264 }
265 return 0;
266 }
267
268 static float r300_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
269 {
270 struct r300_screen* r300screen = r300_screen(pscreen);
271
272 switch (param) {
273 case PIPE_CAP_MAX_LINE_WIDTH:
274 case PIPE_CAP_MAX_LINE_WIDTH_AA:
275 case PIPE_CAP_MAX_POINT_WIDTH:
276 case PIPE_CAP_MAX_POINT_WIDTH_AA:
277 /* The maximum dimensions of the colorbuffer are our practical
278 * rendering limits. 2048 pixels should be enough for anybody. */
279 if (r300screen->caps.is_r500) {
280 return 4096.0f;
281 } else if (r300screen->caps.is_r400) {
282 return 4021.0f;
283 } else {
284 return 2560.0f;
285 }
286 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
287 return 16.0f;
288 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
289 return 16.0f;
290 case PIPE_CAP_GUARD_BAND_LEFT:
291 case PIPE_CAP_GUARD_BAND_TOP:
292 case PIPE_CAP_GUARD_BAND_RIGHT:
293 case PIPE_CAP_GUARD_BAND_BOTTOM:
294 /* XXX I don't know what these should be but the least we can do is
295 * silence the potential error message */
296 return 0.0f;
297 default:
298 debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
299 param);
300 return 0.0f;
301 }
302 }
303
304 static int r300_get_video_param(struct pipe_screen *screen,
305 enum pipe_video_profile profile,
306 enum pipe_video_cap param)
307 {
308 switch (param) {
309 case PIPE_VIDEO_CAP_SUPPORTED:
310 return vl_profile_supported(screen, profile);
311 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
312 return 0;
313 case PIPE_VIDEO_CAP_MAX_WIDTH:
314 case PIPE_VIDEO_CAP_MAX_HEIGHT:
315 return vl_video_buffer_max_size(screen);
316 default:
317 return 0;
318 }
319 }
320
321 static boolean r300_is_format_supported(struct pipe_screen* screen,
322 enum pipe_format format,
323 enum pipe_texture_target target,
324 unsigned sample_count,
325 unsigned usage)
326 {
327 uint32_t retval = 0;
328 boolean drm_2_8_0 = r300_screen(screen)->info.drm_minor >= 8;
329 boolean is_r500 = r300_screen(screen)->caps.is_r500;
330 boolean is_r400 = r300_screen(screen)->caps.is_r400;
331 boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
332 format == PIPE_FORMAT_R10G10B10X2_SNORM ||
333 format == PIPE_FORMAT_B10G10R10A2_UNORM ||
334 format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
335 boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
336 format == PIPE_FORMAT_RGTC1_SNORM ||
337 format == PIPE_FORMAT_LATC1_UNORM ||
338 format == PIPE_FORMAT_LATC1_SNORM;
339 boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
340 format == PIPE_FORMAT_RGTC2_SNORM ||
341 format == PIPE_FORMAT_LATC2_UNORM ||
342 format == PIPE_FORMAT_LATC2_SNORM;
343 boolean is_x16f_xy16f = format == PIPE_FORMAT_R16_FLOAT ||
344 format == PIPE_FORMAT_R16G16_FLOAT ||
345 format == PIPE_FORMAT_A16_FLOAT ||
346 format == PIPE_FORMAT_L16_FLOAT ||
347 format == PIPE_FORMAT_L16A16_FLOAT ||
348 format == PIPE_FORMAT_I16_FLOAT;
349 boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
350 format == PIPE_FORMAT_R16G16_FLOAT ||
351 format == PIPE_FORMAT_R16G16B16_FLOAT ||
352 format == PIPE_FORMAT_R16G16B16A16_FLOAT;
353
354 if (!util_format_is_supported(format, usage))
355 return FALSE;
356
357 /* Check multisampling support. */
358 switch (sample_count) {
359 case 0:
360 case 1:
361 break;
362 case 2:
363 case 3:
364 case 4:
365 case 6:
366 return FALSE;
367 #if 0
368 if (usage != PIPE_BIND_RENDER_TARGET ||
369 !util_format_is_rgba8_variant(
370 util_format_description(format))) {
371 return FALSE;
372 }
373 #endif
374 break;
375 default:
376 return FALSE;
377 }
378
379 /* Check sampler format support. */
380 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
381 /* ATI1N is r5xx-only. */
382 (is_r500 || !is_ati1n) &&
383 /* ATI2N is supported on r4xx-r5xx. */
384 (is_r400 || is_r500 || !is_ati2n) &&
385 /* R16F and RG16F texture support was added in as late as DRM 2.8.0 */
386 (drm_2_8_0 || !is_x16f_xy16f) &&
387 r300_is_sampler_format_supported(format)) {
388 retval |= PIPE_BIND_SAMPLER_VIEW;
389 }
390
391 /* Check colorbuffer format support. */
392 if ((usage & (PIPE_BIND_RENDER_TARGET |
393 PIPE_BIND_DISPLAY_TARGET |
394 PIPE_BIND_SCANOUT |
395 PIPE_BIND_SHARED)) &&
396 /* 2101010 cannot be rendered to on non-r5xx. */
397 (!is_color2101010 || (is_r500 && drm_2_8_0)) &&
398 r300_is_colorbuffer_format_supported(format)) {
399 retval |= usage &
400 (PIPE_BIND_RENDER_TARGET |
401 PIPE_BIND_DISPLAY_TARGET |
402 PIPE_BIND_SCANOUT |
403 PIPE_BIND_SHARED);
404 }
405
406 /* Check depth-stencil format support. */
407 if (usage & PIPE_BIND_DEPTH_STENCIL &&
408 r300_is_zs_format_supported(format)) {
409 retval |= PIPE_BIND_DEPTH_STENCIL;
410 }
411
412 /* Check vertex buffer format support. */
413 if (usage & PIPE_BIND_VERTEX_BUFFER &&
414 /* Half float is supported on >= RV350. */
415 (is_r400 || is_r500 || !is_half_float) &&
416 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
417 retval |= PIPE_BIND_VERTEX_BUFFER;
418 }
419
420 /* Transfers are always supported. */
421 if (usage & PIPE_BIND_TRANSFER_READ)
422 retval |= PIPE_BIND_TRANSFER_READ;
423 if (usage & PIPE_BIND_TRANSFER_WRITE)
424 retval |= PIPE_BIND_TRANSFER_WRITE;
425
426 return retval == usage;
427 }
428
429 static void r300_destroy_screen(struct pipe_screen* pscreen)
430 {
431 struct r300_screen* r300screen = r300_screen(pscreen);
432 struct radeon_winsys *rws = radeon_winsys(pscreen);
433
434 util_slab_destroy(&r300screen->pool_buffers);
435 pipe_mutex_destroy(r300screen->num_contexts_mutex);
436
437 if (rws)
438 rws->destroy(rws);
439
440 FREE(r300screen);
441 }
442
443 static void r300_fence_reference(struct pipe_screen *screen,
444 struct pipe_fence_handle **ptr,
445 struct pipe_fence_handle *fence)
446 {
447 pb_reference((struct pb_buffer**)ptr,
448 (struct pb_buffer*)fence);
449 }
450
451 static boolean r300_fence_signalled(struct pipe_screen *screen,
452 struct pipe_fence_handle *fence)
453 {
454 struct radeon_winsys *rws = r300_screen(screen)->rws;
455 struct pb_buffer *rfence = (struct pb_buffer*)fence;
456
457 return !rws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE);
458 }
459
460 static boolean r300_fence_finish(struct pipe_screen *screen,
461 struct pipe_fence_handle *fence,
462 uint64_t timeout)
463 {
464 struct radeon_winsys *rws = r300_screen(screen)->rws;
465 struct pb_buffer *rfence = (struct pb_buffer*)fence;
466
467 if (timeout != PIPE_TIMEOUT_INFINITE) {
468 int64_t start_time = os_time_get();
469
470 /* Convert to microseconds. */
471 timeout /= 1000;
472
473 /* Wait in a loop. */
474 while (rws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE)) {
475 if (os_time_get() - start_time >= timeout) {
476 return FALSE;
477 }
478 os_time_sleep(10);
479 }
480 return TRUE;
481 }
482
483 rws->buffer_wait(rfence, RADEON_USAGE_READWRITE);
484 return TRUE;
485 }
486
487 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws)
488 {
489 struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
490
491 if (!r300screen) {
492 FREE(r300screen);
493 return NULL;
494 }
495
496 rws->query_info(rws, &r300screen->info);
497
498 r300_init_debug(r300screen);
499 r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
500
501 if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
502 r300screen->caps.zmask_ram = 0;
503 if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
504 r300screen->caps.hiz_ram = 0;
505
506 if (r300screen->info.drm_minor < 8)
507 r300screen->caps.has_us_format = FALSE;
508
509 pipe_mutex_init(r300screen->num_contexts_mutex);
510
511 util_slab_create(&r300screen->pool_buffers,
512 sizeof(struct r300_resource), 64,
513 UTIL_SLAB_SINGLETHREADED);
514
515 r300screen->rws = rws;
516 r300screen->screen.winsys = (struct pipe_winsys*)rws;
517 r300screen->screen.destroy = r300_destroy_screen;
518 r300screen->screen.get_name = r300_get_name;
519 r300screen->screen.get_vendor = r300_get_vendor;
520 r300screen->screen.get_param = r300_get_param;
521 r300screen->screen.get_shader_param = r300_get_shader_param;
522 r300screen->screen.get_paramf = r300_get_paramf;
523 r300screen->screen.get_video_param = r300_get_video_param;
524 r300screen->screen.is_format_supported = r300_is_format_supported;
525 r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
526 r300screen->screen.context_create = r300_create_context;
527 r300screen->screen.fence_reference = r300_fence_reference;
528 r300screen->screen.fence_signalled = r300_fence_signalled;
529 r300screen->screen.fence_finish = r300_fence_finish;
530
531 r300_init_screen_resource_functions(r300screen);
532
533 util_format_s3tc_init();
534
535 return &r300screen->screen;
536 }