19b273f4f492b73ad219aa1c937f61da65739232
[mesa.git] / src / gallium / drivers / r300 / r300_screen.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "util/u_format.h"
25 #include "util/u_format_s3tc.h"
26 #include "util/u_memory.h"
27 #include "os/os_time.h"
28 #include "vl/vl_video_buffer.h"
29
30 #include "r300_context.h"
31 #include "r300_texture.h"
32 #include "r300_screen_buffer.h"
33 #include "r300_state_inlines.h"
34 #include "r300_public.h"
35
36 #include "draw/draw_context.h"
37
38 /* Return the identifier behind whom the brave coders responsible for this
39 * amalgamation of code, sweat, and duct tape, routinely obscure their names.
40 *
41 * ...I should have just put "Corbin Simpson", but I'm not that cool.
42 *
43 * (Or egotistical. Yet.) */
44 static const char* r300_get_vendor(struct pipe_screen* pscreen)
45 {
46 return "X.Org R300 Project";
47 }
48
49 static const char* chip_families[] = {
50 "ATI R300",
51 "ATI R350",
52 "ATI RV350",
53 "ATI RV370",
54 "ATI RV380",
55 "ATI RS400",
56 "ATI RC410",
57 "ATI RS480",
58 "ATI R420",
59 "ATI R423",
60 "ATI R430",
61 "ATI R480",
62 "ATI R481",
63 "ATI RV410",
64 "ATI RS600",
65 "ATI RS690",
66 "ATI RS740",
67 "ATI RV515",
68 "ATI R520",
69 "ATI RV530",
70 "ATI R580",
71 "ATI RV560",
72 "ATI RV570"
73 };
74
75 static const char* r300_get_name(struct pipe_screen* pscreen)
76 {
77 struct r300_screen* r300screen = r300_screen(pscreen);
78
79 return chip_families[r300screen->caps.family];
80 }
81
82 static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
83 {
84 struct r300_screen* r300screen = r300_screen(pscreen);
85 boolean is_r500 = r300screen->caps.is_r500;
86
87 switch (param) {
88 /* Supported features (boolean caps). */
89 case PIPE_CAP_NPOT_TEXTURES:
90 case PIPE_CAP_TWO_SIDED_STENCIL:
91 case PIPE_CAP_GLSL:
92 /* I'll be frank. This is a lie.
93 *
94 * We don't truly support GLSL on any of this driver's chipsets.
95 * To be fair, no chipset supports the full GLSL specification
96 * to the best of our knowledge, but some of the less esoteric
97 * features are still missing here.
98 *
99 * Rather than cripple ourselves intentionally, I'm going to set
100 * this flag, and as Gallium's interface continues to change, I
101 * hope that this single monolithic GLSL enable can slowly get
102 * split down into many different pieces and the state tracker
103 * will handle fallbacks transparently, like it should.
104 *
105 * ~ C.
106 */
107 case PIPE_CAP_ANISOTROPIC_FILTER:
108 case PIPE_CAP_POINT_SPRITE:
109 case PIPE_CAP_OCCLUSION_QUERY:
110 case PIPE_CAP_TEXTURE_SHADOW_MAP:
111 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
112 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
113 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
114 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
115 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
116 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
117 return 1;
118
119 /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
120 case PIPE_CAP_TEXTURE_SWIZZLE:
121 return util_format_s3tc_enabled ? r300screen->caps.dxtc_swizzle : 1;
122
123 /* Supported on r500 only. */
124 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
125 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
126 case PIPE_CAP_SM3:
127 return is_r500 ? 1 : 0;
128
129 /* Unsupported features. */
130 case PIPE_CAP_TIMER_QUERY:
131 case PIPE_CAP_DUAL_SOURCE_BLEND:
132 case PIPE_CAP_INDEP_BLEND_ENABLE:
133 case PIPE_CAP_INDEP_BLEND_FUNC:
134 case PIPE_CAP_DEPTH_CLAMP:
135 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
136 case PIPE_CAP_SHADER_STENCIL_EXPORT:
137 case PIPE_CAP_ARRAY_TEXTURES:
138 case PIPE_CAP_TGSI_INSTANCEID:
139 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
140 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
141 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
142 case PIPE_CAP_SEAMLESS_CUBE_MAP:
143 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
144 return 0;
145
146 /* SWTCL-only features. */
147 case PIPE_CAP_STREAM_OUTPUT:
148 case PIPE_CAP_PRIMITIVE_RESTART:
149 return !r300screen->caps.has_tcl;
150
151 /* Texturing. */
152 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
153 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
154 return r300screen->caps.num_tex_units;
155 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
156 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
157 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
158 /* 13 == 4096, 12 == 2048 */
159 return is_r500 ? 13 : 12;
160
161 /* Render targets. */
162 case PIPE_CAP_MAX_RENDER_TARGETS:
163 return 4;
164
165 default:
166 debug_printf("r300: Warning: Unknown CAP %d in get_param.\n",
167 param);
168 return 0;
169 }
170 }
171
172 static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
173 {
174 struct r300_screen* r300screen = r300_screen(pscreen);
175 boolean is_r400 = r300screen->caps.is_r400;
176 boolean is_r500 = r300screen->caps.is_r500;
177
178 switch (shader)
179 {
180 case PIPE_SHADER_FRAGMENT:
181 switch (param)
182 {
183 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
184 return is_r500 || is_r400 ? 512 : 96;
185 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
186 return is_r500 || is_r400 ? 512 : 64;
187 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
188 return is_r500 || is_r400 ? 512 : 32;
189 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
190 return is_r500 ? 511 : 4;
191 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
192 return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
193 /* Fragment shader limits. */
194 case PIPE_SHADER_CAP_MAX_INPUTS:
195 /* 2 colors + 8 texcoords are always supported
196 * (minus fog and wpos).
197 *
198 * R500 has the ability to turn 3rd and 4th color into
199 * additional texcoords but there is no two-sided color
200 * selection then. However the facing bit can be used instead. */
201 return 10;
202 case PIPE_SHADER_CAP_MAX_CONSTS:
203 return is_r500 ? 256 : 32;
204 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
205 return 1;
206 case PIPE_SHADER_CAP_MAX_TEMPS:
207 return is_r500 ? 128 : is_r400 ? 64 : 32;
208 case PIPE_SHADER_CAP_MAX_ADDRS:
209 return 0;
210 case PIPE_SHADER_CAP_MAX_PREDS:
211 return is_r500 ? 1 : 0;
212 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
213 return 0;
214 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
215 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
216 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
217 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
218 return 0;
219 case PIPE_SHADER_CAP_SUBROUTINES:
220 return 0;
221 }
222 break;
223 case PIPE_SHADER_VERTEX:
224 if (!r300screen->caps.has_tcl) {
225 return draw_get_shader_param(shader, param);
226 }
227
228 switch (param)
229 {
230 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
231 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
232 return is_r500 ? 1024 : 256;
233 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
234 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
235 return 0;
236 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
237 return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
238 case PIPE_SHADER_CAP_MAX_INPUTS:
239 return 16;
240 case PIPE_SHADER_CAP_MAX_CONSTS:
241 return 256;
242 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
243 return 1;
244 case PIPE_SHADER_CAP_MAX_TEMPS:
245 return 32;
246 case PIPE_SHADER_CAP_MAX_ADDRS:
247 return 1; /* XXX guessed */
248 case PIPE_SHADER_CAP_MAX_PREDS:
249 return is_r500 ? 4 : 0; /* XXX guessed. */
250 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
251 return 0;
252 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
253 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
254 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
255 return 0;
256 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
257 return 1;
258 case PIPE_SHADER_CAP_SUBROUTINES:
259 return 0;
260 default:
261 break;
262 }
263 break;
264 default:
265 break;
266 }
267 return 0;
268 }
269
270 static float r300_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
271 {
272 struct r300_screen* r300screen = r300_screen(pscreen);
273
274 switch (param) {
275 case PIPE_CAP_MAX_LINE_WIDTH:
276 case PIPE_CAP_MAX_LINE_WIDTH_AA:
277 case PIPE_CAP_MAX_POINT_WIDTH:
278 case PIPE_CAP_MAX_POINT_WIDTH_AA:
279 /* The maximum dimensions of the colorbuffer are our practical
280 * rendering limits. 2048 pixels should be enough for anybody. */
281 if (r300screen->caps.is_r500) {
282 return 4096.0f;
283 } else if (r300screen->caps.is_r400) {
284 return 4021.0f;
285 } else {
286 return 2560.0f;
287 }
288 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
289 return 16.0f;
290 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
291 return 16.0f;
292 case PIPE_CAP_GUARD_BAND_LEFT:
293 case PIPE_CAP_GUARD_BAND_TOP:
294 case PIPE_CAP_GUARD_BAND_RIGHT:
295 case PIPE_CAP_GUARD_BAND_BOTTOM:
296 /* XXX I don't know what these should be but the least we can do is
297 * silence the potential error message */
298 return 0.0f;
299 default:
300 debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
301 param);
302 return 0.0f;
303 }
304 }
305
306 static int r300_get_video_param(struct pipe_screen *screen,
307 enum pipe_video_profile profile,
308 enum pipe_video_cap param)
309 {
310 switch (param) {
311 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
312 return 0;
313 default:
314 return 0;
315 }
316 }
317
318 static boolean r300_is_format_supported(struct pipe_screen* screen,
319 enum pipe_format format,
320 enum pipe_texture_target target,
321 unsigned sample_count,
322 unsigned usage)
323 {
324 struct radeon_winsys *rws = r300_screen(screen)->rws;
325 uint32_t retval = 0;
326 boolean drm_2_8_0 = rws->get_value(rws, RADEON_VID_DRM_2_8_0);
327 boolean is_r500 = r300_screen(screen)->caps.is_r500;
328 boolean is_r400 = r300_screen(screen)->caps.is_r400;
329 boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
330 format == PIPE_FORMAT_R10G10B10X2_SNORM ||
331 format == PIPE_FORMAT_B10G10R10A2_UNORM ||
332 format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
333 boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
334 format == PIPE_FORMAT_RGTC1_SNORM ||
335 format == PIPE_FORMAT_LATC1_UNORM ||
336 format == PIPE_FORMAT_LATC1_SNORM;
337 boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
338 format == PIPE_FORMAT_RGTC2_SNORM ||
339 format == PIPE_FORMAT_LATC2_UNORM ||
340 format == PIPE_FORMAT_LATC2_SNORM;
341 boolean is_x16f_xy16f = format == PIPE_FORMAT_R16_FLOAT ||
342 format == PIPE_FORMAT_R16G16_FLOAT ||
343 format == PIPE_FORMAT_A16_FLOAT ||
344 format == PIPE_FORMAT_L16_FLOAT ||
345 format == PIPE_FORMAT_L16A16_FLOAT ||
346 format == PIPE_FORMAT_I16_FLOAT;
347 boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
348 format == PIPE_FORMAT_R16G16_FLOAT ||
349 format == PIPE_FORMAT_R16G16B16_FLOAT ||
350 format == PIPE_FORMAT_R16G16B16A16_FLOAT;
351
352 if (!util_format_is_supported(format, usage))
353 return FALSE;
354
355 /* Check multisampling support. */
356 switch (sample_count) {
357 case 0:
358 case 1:
359 break;
360 case 2:
361 case 3:
362 case 4:
363 case 6:
364 return FALSE;
365 #if 0
366 if (usage != PIPE_BIND_RENDER_TARGET ||
367 !util_format_is_rgba8_variant(
368 util_format_description(format))) {
369 return FALSE;
370 }
371 #endif
372 break;
373 default:
374 return FALSE;
375 }
376
377 /* Check sampler format support. */
378 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
379 /* ATI1N is r5xx-only. */
380 (is_r500 || !is_ati1n) &&
381 /* ATI2N is supported on r4xx-r5xx. */
382 (is_r400 || is_r500 || !is_ati2n) &&
383 /* R16F and RG16F texture support was added in as late as DRM 2.8.0 */
384 (drm_2_8_0 || !is_x16f_xy16f) &&
385 r300_is_sampler_format_supported(format)) {
386 retval |= PIPE_BIND_SAMPLER_VIEW;
387 }
388
389 /* Check colorbuffer format support. */
390 if ((usage & (PIPE_BIND_RENDER_TARGET |
391 PIPE_BIND_DISPLAY_TARGET |
392 PIPE_BIND_SCANOUT |
393 PIPE_BIND_SHARED)) &&
394 /* 2101010 cannot be rendered to on non-r5xx. */
395 (!is_color2101010 || (is_r500 && drm_2_8_0)) &&
396 r300_is_colorbuffer_format_supported(format)) {
397 retval |= usage &
398 (PIPE_BIND_RENDER_TARGET |
399 PIPE_BIND_DISPLAY_TARGET |
400 PIPE_BIND_SCANOUT |
401 PIPE_BIND_SHARED);
402 }
403
404 /* Check depth-stencil format support. */
405 if (usage & PIPE_BIND_DEPTH_STENCIL &&
406 r300_is_zs_format_supported(format)) {
407 retval |= PIPE_BIND_DEPTH_STENCIL;
408 }
409
410 /* Check vertex buffer format support. */
411 if (usage & PIPE_BIND_VERTEX_BUFFER &&
412 /* Half float is supported on >= RV350. */
413 (is_r400 || is_r500 || !is_half_float) &&
414 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
415 retval |= PIPE_BIND_VERTEX_BUFFER;
416 }
417
418 /* Transfers are always supported. */
419 if (usage & PIPE_BIND_TRANSFER_READ)
420 retval |= PIPE_BIND_TRANSFER_READ;
421 if (usage & PIPE_BIND_TRANSFER_WRITE)
422 retval |= PIPE_BIND_TRANSFER_WRITE;
423
424 return retval == usage;
425 }
426
427 static void r300_destroy_screen(struct pipe_screen* pscreen)
428 {
429 struct r300_screen* r300screen = r300_screen(pscreen);
430 struct radeon_winsys *rws = radeon_winsys(pscreen);
431
432 util_slab_destroy(&r300screen->pool_buffers);
433 pipe_mutex_destroy(r300screen->num_contexts_mutex);
434
435 if (rws)
436 rws->destroy(rws);
437
438 FREE(r300screen);
439 }
440
441 static void r300_fence_reference(struct pipe_screen *screen,
442 struct pipe_fence_handle **ptr,
443 struct pipe_fence_handle *fence)
444 {
445 pb_reference((struct pb_buffer**)ptr,
446 (struct pb_buffer*)fence);
447 }
448
449 static boolean r300_fence_signalled(struct pipe_screen *screen,
450 struct pipe_fence_handle *fence)
451 {
452 struct radeon_winsys *rws = r300_screen(screen)->rws;
453 struct pb_buffer *rfence = (struct pb_buffer*)fence;
454
455 return !rws->buffer_is_busy(rfence);
456 }
457
458 static boolean r300_fence_finish(struct pipe_screen *screen,
459 struct pipe_fence_handle *fence,
460 uint64_t timeout)
461 {
462 struct radeon_winsys *rws = r300_screen(screen)->rws;
463 struct pb_buffer *rfence = (struct pb_buffer*)fence;
464
465 if (timeout != PIPE_TIMEOUT_INFINITE) {
466 int64_t start_time = os_time_get();
467
468 /* Convert to microseconds. */
469 timeout /= 1000;
470
471 /* Wait in a loop. */
472 while (rws->buffer_is_busy(rfence)) {
473 if (os_time_get() - start_time >= timeout) {
474 return FALSE;
475 }
476 os_time_sleep(10);
477 }
478 return TRUE;
479 }
480
481 rws->buffer_wait(rfence);
482 return TRUE;
483 }
484
485 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws)
486 {
487 struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
488
489 if (!r300screen) {
490 FREE(r300screen);
491 return NULL;
492 }
493
494 r300screen->caps.pci_id = rws->get_value(rws, RADEON_VID_PCI_ID);
495 r300screen->caps.num_frag_pipes = rws->get_value(rws, RADEON_VID_R300_GB_PIPES);
496 r300screen->caps.num_z_pipes = rws->get_value(rws, RADEON_VID_R300_Z_PIPES);
497
498 r300_init_debug(r300screen);
499 r300_parse_chipset(&r300screen->caps);
500
501 if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
502 r300screen->caps.zmask_ram = 0;
503 if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
504 r300screen->caps.hiz_ram = 0;
505
506 if (!rws->get_value(rws, RADEON_VID_DRM_2_8_0))
507 r300screen->caps.has_us_format = FALSE;
508
509 pipe_mutex_init(r300screen->num_contexts_mutex);
510
511 util_slab_create(&r300screen->pool_buffers,
512 sizeof(struct r300_resource), 64,
513 UTIL_SLAB_SINGLETHREADED);
514
515 r300screen->rws = rws;
516 r300screen->screen.winsys = (struct pipe_winsys*)rws;
517 r300screen->screen.destroy = r300_destroy_screen;
518 r300screen->screen.get_name = r300_get_name;
519 r300screen->screen.get_vendor = r300_get_vendor;
520 r300screen->screen.get_param = r300_get_param;
521 r300screen->screen.get_shader_param = r300_get_shader_param;
522 r300screen->screen.get_paramf = r300_get_paramf;
523 r300screen->screen.get_video_param = r300_get_video_param;
524 r300screen->screen.is_format_supported = r300_is_format_supported;
525 r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
526 r300screen->screen.context_create = r300_create_context;
527 r300screen->screen.fence_reference = r300_fence_reference;
528 r300screen->screen.fence_signalled = r300_fence_signalled;
529 r300screen->screen.fence_finish = r300_fence_finish;
530
531 r300_init_screen_resource_functions(r300screen);
532
533 util_format_s3tc_init();
534
535 return &r300screen->screen;
536 }