swr: [rasterizer jitter] unitialized component fix in fetch jit
[mesa.git] / src / gallium / drivers / r300 / r300_screen.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "util/u_format.h"
25 #include "util/u_format_s3tc.h"
26 #include "util/u_memory.h"
27 #include "os/os_time.h"
28 #include "vl/vl_decoder.h"
29 #include "vl/vl_video_buffer.h"
30
31 #include "r300_context.h"
32 #include "r300_texture.h"
33 #include "r300_screen_buffer.h"
34 #include "r300_state_inlines.h"
35 #include "r300_public.h"
36
37 #include "draw/draw_context.h"
38
39 /* Return the identifier behind whom the brave coders responsible for this
40 * amalgamation of code, sweat, and duct tape, routinely obscure their names.
41 *
42 * ...I should have just put "Corbin Simpson", but I'm not that cool.
43 *
44 * (Or egotistical. Yet.) */
45 static const char* r300_get_vendor(struct pipe_screen* pscreen)
46 {
47 return "X.Org R300 Project";
48 }
49
50 static const char* r300_get_device_vendor(struct pipe_screen* pscreen)
51 {
52 return "ATI";
53 }
54
55 static const char* chip_families[] = {
56 "unknown",
57 "ATI R300",
58 "ATI R350",
59 "ATI RV350",
60 "ATI RV370",
61 "ATI RV380",
62 "ATI RS400",
63 "ATI RC410",
64 "ATI RS480",
65 "ATI R420",
66 "ATI R423",
67 "ATI R430",
68 "ATI R480",
69 "ATI R481",
70 "ATI RV410",
71 "ATI RS600",
72 "ATI RS690",
73 "ATI RS740",
74 "ATI RV515",
75 "ATI R520",
76 "ATI RV530",
77 "ATI R580",
78 "ATI RV560",
79 "ATI RV570"
80 };
81
82 static const char* r300_get_name(struct pipe_screen* pscreen)
83 {
84 struct r300_screen* r300screen = r300_screen(pscreen);
85
86 return chip_families[r300screen->caps.family];
87 }
88
89 static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
90 {
91 struct r300_screen* r300screen = r300_screen(pscreen);
92 boolean is_r500 = r300screen->caps.is_r500;
93
94 switch (param) {
95 /* Supported features (boolean caps). */
96 case PIPE_CAP_NPOT_TEXTURES:
97 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
98 case PIPE_CAP_TWO_SIDED_STENCIL:
99 case PIPE_CAP_ANISOTROPIC_FILTER:
100 case PIPE_CAP_POINT_SPRITE:
101 case PIPE_CAP_OCCLUSION_QUERY:
102 case PIPE_CAP_TEXTURE_SHADOW_MAP:
103 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
104 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
105 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
106 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
107 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
108 case PIPE_CAP_CONDITIONAL_RENDER:
109 case PIPE_CAP_TEXTURE_BARRIER:
110 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
111 case PIPE_CAP_USER_INDEX_BUFFERS:
112 case PIPE_CAP_USER_CONSTANT_BUFFERS:
113 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
114 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
115 case PIPE_CAP_CLIP_HALFZ:
116 return 1;
117
118 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
119 return R300_BUFFER_ALIGNMENT;
120
121 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
122 return 16;
123
124 case PIPE_CAP_GLSL_FEATURE_LEVEL:
125 return 120;
126
127 /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
128 case PIPE_CAP_TEXTURE_SWIZZLE:
129 return util_format_s3tc_enabled ? r300screen->caps.dxtc_swizzle : 1;
130
131 /* We don't support color clamping on r500, so that we can use color
132 * intepolators for generic varyings. */
133 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
134 return !is_r500;
135
136 /* Supported on r500 only. */
137 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
138 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
139 case PIPE_CAP_SM3:
140 return is_r500 ? 1 : 0;
141
142 /* Unsupported features. */
143 case PIPE_CAP_QUERY_TIME_ELAPSED:
144 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
145 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
146 case PIPE_CAP_INDEP_BLEND_ENABLE:
147 case PIPE_CAP_INDEP_BLEND_FUNC:
148 case PIPE_CAP_DEPTH_CLIP_DISABLE:
149 case PIPE_CAP_SHADER_STENCIL_EXPORT:
150 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
151 case PIPE_CAP_TGSI_INSTANCEID:
152 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
153 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
154 case PIPE_CAP_SEAMLESS_CUBE_MAP:
155 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
156 case PIPE_CAP_MIN_TEXEL_OFFSET:
157 case PIPE_CAP_MAX_TEXEL_OFFSET:
158 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
159 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
160 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
161 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
162 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
163 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
164 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
165 case PIPE_CAP_MAX_VERTEX_STREAMS:
166 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
167 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
168 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
169 case PIPE_CAP_COMPUTE:
170 case PIPE_CAP_START_INSTANCE:
171 case PIPE_CAP_QUERY_TIMESTAMP:
172 case PIPE_CAP_TEXTURE_MULTISAMPLE:
173 case PIPE_CAP_CUBE_MAP_ARRAY:
174 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
175 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
176 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
177 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
178 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
179 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
180 case PIPE_CAP_TEXTURE_GATHER_SM5:
181 case PIPE_CAP_TEXTURE_QUERY_LOD:
182 case PIPE_CAP_FAKE_SW_MSAA:
183 case PIPE_CAP_SAMPLE_SHADING:
184 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
185 case PIPE_CAP_DRAW_INDIRECT:
186 case PIPE_CAP_MULTI_DRAW_INDIRECT:
187 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
188 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
189 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
190 case PIPE_CAP_SAMPLER_VIEW_TARGET:
191 case PIPE_CAP_VERTEXID_NOBASE:
192 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
193 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
194 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
195 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
196 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
197 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
198 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
199 case PIPE_CAP_DEPTH_BOUNDS_TEST:
200 case PIPE_CAP_TGSI_TXQS:
201 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
202 case PIPE_CAP_SHAREABLE_SHADERS:
203 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
204 case PIPE_CAP_CLEAR_TEXTURE:
205 case PIPE_CAP_DRAW_PARAMETERS:
206 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
207 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
208 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
209 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
210 case PIPE_CAP_INVALIDATE_BUFFER:
211 case PIPE_CAP_GENERATE_MIPMAP:
212 case PIPE_CAP_STRING_MARKER:
213 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
214 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
215 case PIPE_CAP_QUERY_BUFFER_OBJECT:
216 case PIPE_CAP_QUERY_MEMORY_INFO:
217 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
218 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
219 case PIPE_CAP_CULL_DISTANCE:
220 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
221 case PIPE_CAP_TGSI_VOTE:
222 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
223 return 0;
224
225 /* SWTCL-only features. */
226 case PIPE_CAP_PRIMITIVE_RESTART:
227 case PIPE_CAP_USER_VERTEX_BUFFERS:
228 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
229 return !r300screen->caps.has_tcl;
230
231 /* HWTCL-only features / limitations. */
232 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
233 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
234 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
235 return r300screen->caps.has_tcl;
236 case PIPE_CAP_TGSI_TEXCOORD:
237 return 0;
238
239 /* Texturing. */
240 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
241 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
242 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
243 /* 13 == 4096, 12 == 2048 */
244 return is_r500 ? 13 : 12;
245
246 /* Render targets. */
247 case PIPE_CAP_MAX_RENDER_TARGETS:
248 return 4;
249 case PIPE_CAP_ENDIANNESS:
250 return PIPE_ENDIAN_LITTLE;
251
252 case PIPE_CAP_MAX_VIEWPORTS:
253 return 1;
254
255 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
256 return 2048;
257
258 case PIPE_CAP_VENDOR_ID:
259 return 0x1002;
260 case PIPE_CAP_DEVICE_ID:
261 return r300screen->info.pci_id;
262 case PIPE_CAP_ACCELERATED:
263 return 1;
264 case PIPE_CAP_VIDEO_MEMORY:
265 return r300screen->info.vram_size >> 20;
266 case PIPE_CAP_UMA:
267 return 0;
268 case PIPE_CAP_PCI_GROUP:
269 return r300screen->info.pci_domain;
270 case PIPE_CAP_PCI_BUS:
271 return r300screen->info.pci_bus;
272 case PIPE_CAP_PCI_DEVICE:
273 return r300screen->info.pci_dev;
274 case PIPE_CAP_PCI_FUNCTION:
275 return r300screen->info.pci_func;
276 }
277 return 0;
278 }
279
280 static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
281 {
282 struct r300_screen* r300screen = r300_screen(pscreen);
283 boolean is_r400 = r300screen->caps.is_r400;
284 boolean is_r500 = r300screen->caps.is_r500;
285
286 switch (shader) {
287 case PIPE_SHADER_FRAGMENT:
288 switch (param)
289 {
290 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
291 return is_r500 || is_r400 ? 512 : 96;
292 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
293 return is_r500 || is_r400 ? 512 : 64;
294 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
295 return is_r500 || is_r400 ? 512 : 32;
296 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
297 return is_r500 ? 511 : 4;
298 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
299 return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
300 /* Fragment shader limits. */
301 case PIPE_SHADER_CAP_MAX_INPUTS:
302 /* 2 colors + 8 texcoords are always supported
303 * (minus fog and wpos).
304 *
305 * R500 has the ability to turn 3rd and 4th color into
306 * additional texcoords but there is no two-sided color
307 * selection then. However the facing bit can be used instead. */
308 return 10;
309 case PIPE_SHADER_CAP_MAX_OUTPUTS:
310 return 4;
311 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
312 return (is_r500 ? 256 : 32) * sizeof(float[4]);
313 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
314 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
315 return 1;
316 case PIPE_SHADER_CAP_MAX_TEMPS:
317 return is_r500 ? 128 : is_r400 ? 64 : 32;
318 case PIPE_SHADER_CAP_MAX_PREDS:
319 return 0; /* unused */
320 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
321 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
322 return r300screen->caps.num_tex_units;
323 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
324 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
325 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
326 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
327 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
328 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
329 case PIPE_SHADER_CAP_SUBROUTINES:
330 case PIPE_SHADER_CAP_INTEGERS:
331 case PIPE_SHADER_CAP_DOUBLES:
332 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
333 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
334 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
335 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
336 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
337 return 0;
338 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
339 return 32;
340 case PIPE_SHADER_CAP_PREFERRED_IR:
341 return PIPE_SHADER_IR_TGSI;
342 case PIPE_SHADER_CAP_SUPPORTED_IRS:
343 return 0;
344 }
345 break;
346 case PIPE_SHADER_VERTEX:
347 switch (param)
348 {
349 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
350 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
351 case PIPE_SHADER_CAP_SUBROUTINES:
352 return 0;
353 default:;
354 }
355
356 if (!r300screen->caps.has_tcl) {
357 return draw_get_shader_param(shader, param);
358 }
359
360 switch (param)
361 {
362 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
363 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
364 return is_r500 ? 1024 : 256;
365 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
366 return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
367 case PIPE_SHADER_CAP_MAX_INPUTS:
368 return 16;
369 case PIPE_SHADER_CAP_MAX_OUTPUTS:
370 return 10;
371 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
372 return 256 * sizeof(float[4]);
373 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
374 return 1;
375 case PIPE_SHADER_CAP_MAX_TEMPS:
376 return 32;
377 case PIPE_SHADER_CAP_MAX_PREDS:
378 return 0; /* unused */
379 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
380 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
381 return 1;
382 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
383 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
384 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
385 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
386 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
387 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
388 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
389 case PIPE_SHADER_CAP_SUBROUTINES:
390 case PIPE_SHADER_CAP_INTEGERS:
391 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
392 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
393 case PIPE_SHADER_CAP_DOUBLES:
394 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
395 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
396 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
397 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
398 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
399 return 0;
400 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
401 return 32;
402 case PIPE_SHADER_CAP_PREFERRED_IR:
403 return PIPE_SHADER_IR_TGSI;
404 case PIPE_SHADER_CAP_SUPPORTED_IRS:
405 return 0;
406 }
407 break;
408 }
409 return 0;
410 }
411
412 static float r300_get_paramf(struct pipe_screen* pscreen,
413 enum pipe_capf param)
414 {
415 struct r300_screen* r300screen = r300_screen(pscreen);
416
417 switch (param) {
418 case PIPE_CAPF_MAX_LINE_WIDTH:
419 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
420 case PIPE_CAPF_MAX_POINT_WIDTH:
421 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
422 /* The maximum dimensions of the colorbuffer are our practical
423 * rendering limits. 2048 pixels should be enough for anybody. */
424 if (r300screen->caps.is_r500) {
425 return 4096.0f;
426 } else if (r300screen->caps.is_r400) {
427 return 4021.0f;
428 } else {
429 return 2560.0f;
430 }
431 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
432 return 16.0f;
433 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
434 return 16.0f;
435 case PIPE_CAPF_GUARD_BAND_LEFT:
436 case PIPE_CAPF_GUARD_BAND_TOP:
437 case PIPE_CAPF_GUARD_BAND_RIGHT:
438 case PIPE_CAPF_GUARD_BAND_BOTTOM:
439 return 0.0f;
440 default:
441 debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
442 param);
443 return 0.0f;
444 }
445 }
446
447 static int r300_get_video_param(struct pipe_screen *screen,
448 enum pipe_video_profile profile,
449 enum pipe_video_entrypoint entrypoint,
450 enum pipe_video_cap param)
451 {
452 switch (param) {
453 case PIPE_VIDEO_CAP_SUPPORTED:
454 return vl_profile_supported(screen, profile, entrypoint);
455 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
456 return 0;
457 case PIPE_VIDEO_CAP_MAX_WIDTH:
458 case PIPE_VIDEO_CAP_MAX_HEIGHT:
459 return vl_video_buffer_max_size(screen);
460 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
461 return PIPE_FORMAT_NV12;
462 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
463 return false;
464 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
465 return false;
466 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
467 return true;
468 case PIPE_VIDEO_CAP_MAX_LEVEL:
469 return vl_level_supported(screen, profile);
470 default:
471 return 0;
472 }
473 }
474
475 /**
476 * Whether the format matches:
477 * PIPE_FORMAT_?10?10?10?2_UNORM
478 */
479 static inline boolean
480 util_format_is_rgba1010102_variant(const struct util_format_description *desc)
481 {
482 static const unsigned size[4] = {10, 10, 10, 2};
483 unsigned chan;
484
485 if (desc->block.width != 1 ||
486 desc->block.height != 1 ||
487 desc->block.bits != 32)
488 return FALSE;
489
490 for (chan = 0; chan < 4; ++chan) {
491 if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
492 desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
493 return FALSE;
494 if (desc->channel[chan].size != size[chan])
495 return FALSE;
496 }
497
498 return TRUE;
499 }
500
501 static bool r300_is_blending_supported(struct r300_screen *rscreen,
502 enum pipe_format format)
503 {
504 int c;
505 const struct util_format_description *desc =
506 util_format_description(format);
507
508 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
509 return false;
510
511 c = util_format_get_first_non_void_channel(format);
512
513 /* RGBA16F */
514 if (rscreen->caps.is_r500 &&
515 desc->nr_channels == 4 &&
516 desc->channel[c].size == 16 &&
517 desc->channel[c].type == UTIL_FORMAT_TYPE_FLOAT)
518 return true;
519
520 if (desc->channel[c].normalized &&
521 desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED &&
522 desc->channel[c].size >= 4 &&
523 desc->channel[c].size <= 10) {
524 /* RGB10_A2, RGBA8, RGB5_A1, RGBA4, RGB565 */
525 if (desc->nr_channels >= 3)
526 return true;
527
528 if (format == PIPE_FORMAT_R8G8_UNORM)
529 return true;
530
531 /* R8, I8, L8, A8 */
532 if (desc->nr_channels == 1)
533 return true;
534 }
535
536 return false;
537 }
538
539 static boolean r300_is_format_supported(struct pipe_screen* screen,
540 enum pipe_format format,
541 enum pipe_texture_target target,
542 unsigned sample_count,
543 unsigned usage)
544 {
545 uint32_t retval = 0;
546 boolean is_r500 = r300_screen(screen)->caps.is_r500;
547 boolean is_r400 = r300_screen(screen)->caps.is_r400;
548 boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
549 format == PIPE_FORMAT_R10G10B10X2_SNORM ||
550 format == PIPE_FORMAT_B10G10R10A2_UNORM ||
551 format == PIPE_FORMAT_B10G10R10X2_UNORM ||
552 format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
553 boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
554 format == PIPE_FORMAT_RGTC1_SNORM ||
555 format == PIPE_FORMAT_LATC1_UNORM ||
556 format == PIPE_FORMAT_LATC1_SNORM;
557 boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
558 format == PIPE_FORMAT_RGTC2_SNORM ||
559 format == PIPE_FORMAT_LATC2_UNORM ||
560 format == PIPE_FORMAT_LATC2_SNORM;
561 boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
562 format == PIPE_FORMAT_R16G16_FLOAT ||
563 format == PIPE_FORMAT_R16G16B16_FLOAT ||
564 format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
565 format == PIPE_FORMAT_R16G16B16X16_FLOAT;
566 const struct util_format_description *desc;
567
568 if (!util_format_is_supported(format, usage))
569 return FALSE;
570
571 /* Check multisampling support. */
572 switch (sample_count) {
573 case 0:
574 case 1:
575 break;
576 case 2:
577 case 4:
578 case 6:
579 /* No texturing and scanout. */
580 if (usage & (PIPE_BIND_SAMPLER_VIEW |
581 PIPE_BIND_DISPLAY_TARGET |
582 PIPE_BIND_SCANOUT)) {
583 return FALSE;
584 }
585
586 desc = util_format_description(format);
587
588 if (is_r500) {
589 /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
590 if (!util_format_is_depth_or_stencil(format) &&
591 !util_format_is_rgba8_variant(desc) &&
592 !util_format_is_rgba1010102_variant(desc) &&
593 format != PIPE_FORMAT_R16G16B16A16_FLOAT &&
594 format != PIPE_FORMAT_R16G16B16X16_FLOAT) {
595 return FALSE;
596 }
597 } else {
598 /* Only allow depth/stencil, RGBA8. */
599 if (!util_format_is_depth_or_stencil(format) &&
600 !util_format_is_rgba8_variant(desc)) {
601 return FALSE;
602 }
603 }
604 break;
605 default:
606 return FALSE;
607 }
608
609 /* Check sampler format support. */
610 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
611 /* these two are broken for an unknown reason */
612 format != PIPE_FORMAT_R8G8B8X8_SNORM &&
613 format != PIPE_FORMAT_R16G16B16X16_SNORM &&
614 /* ATI1N is r5xx-only. */
615 (is_r500 || !is_ati1n) &&
616 /* ATI2N is supported on r4xx-r5xx. */
617 (is_r400 || is_r500 || !is_ati2n) &&
618 r300_is_sampler_format_supported(format)) {
619 retval |= PIPE_BIND_SAMPLER_VIEW;
620 }
621
622 /* Check colorbuffer format support. */
623 if ((usage & (PIPE_BIND_RENDER_TARGET |
624 PIPE_BIND_DISPLAY_TARGET |
625 PIPE_BIND_SCANOUT |
626 PIPE_BIND_SHARED |
627 PIPE_BIND_BLENDABLE)) &&
628 /* 2101010 cannot be rendered to on non-r5xx. */
629 (!is_color2101010 || is_r500) &&
630 r300_is_colorbuffer_format_supported(format)) {
631 retval |= usage &
632 (PIPE_BIND_RENDER_TARGET |
633 PIPE_BIND_DISPLAY_TARGET |
634 PIPE_BIND_SCANOUT |
635 PIPE_BIND_SHARED);
636
637 if (r300_is_blending_supported(r300_screen(screen), format)) {
638 retval |= usage & PIPE_BIND_BLENDABLE;
639 }
640 }
641
642 /* Check depth-stencil format support. */
643 if (usage & PIPE_BIND_DEPTH_STENCIL &&
644 r300_is_zs_format_supported(format)) {
645 retval |= PIPE_BIND_DEPTH_STENCIL;
646 }
647
648 /* Check vertex buffer format support. */
649 if (usage & PIPE_BIND_VERTEX_BUFFER) {
650 if (r300_screen(screen)->caps.has_tcl) {
651 /* Half float is supported on >= R400. */
652 if ((is_r400 || is_r500 || !is_half_float) &&
653 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
654 retval |= PIPE_BIND_VERTEX_BUFFER;
655 }
656 } else {
657 /* SW TCL */
658 if (!util_format_is_pure_integer(format)) {
659 retval |= PIPE_BIND_VERTEX_BUFFER;
660 }
661 }
662 }
663
664 /* Transfers are always supported. */
665 if (usage & PIPE_BIND_TRANSFER_READ)
666 retval |= PIPE_BIND_TRANSFER_READ;
667 if (usage & PIPE_BIND_TRANSFER_WRITE)
668 retval |= PIPE_BIND_TRANSFER_WRITE;
669
670 return retval == usage;
671 }
672
673 static void r300_destroy_screen(struct pipe_screen* pscreen)
674 {
675 struct r300_screen* r300screen = r300_screen(pscreen);
676 struct radeon_winsys *rws = radeon_winsys(pscreen);
677
678 if (rws && !rws->unref(rws))
679 return;
680
681 pipe_mutex_destroy(r300screen->cmask_mutex);
682
683 if (rws)
684 rws->destroy(rws);
685
686 FREE(r300screen);
687 }
688
689 static void r300_fence_reference(struct pipe_screen *screen,
690 struct pipe_fence_handle **ptr,
691 struct pipe_fence_handle *fence)
692 {
693 struct radeon_winsys *rws = r300_screen(screen)->rws;
694
695 rws->fence_reference(ptr, fence);
696 }
697
698 static boolean r300_fence_finish(struct pipe_screen *screen,
699 struct pipe_fence_handle *fence,
700 uint64_t timeout)
701 {
702 struct radeon_winsys *rws = r300_screen(screen)->rws;
703
704 return rws->fence_wait(rws, fence, timeout);
705 }
706
707 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws)
708 {
709 struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
710
711 if (!r300screen) {
712 FREE(r300screen);
713 return NULL;
714 }
715
716 rws->query_info(rws, &r300screen->info);
717
718 r300_init_debug(r300screen);
719 r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
720
721 if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
722 r300screen->caps.zmask_ram = 0;
723 if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
724 r300screen->caps.hiz_ram = 0;
725
726 r300screen->rws = rws;
727 r300screen->screen.destroy = r300_destroy_screen;
728 r300screen->screen.get_name = r300_get_name;
729 r300screen->screen.get_vendor = r300_get_vendor;
730 r300screen->screen.get_device_vendor = r300_get_device_vendor;
731 r300screen->screen.get_param = r300_get_param;
732 r300screen->screen.get_shader_param = r300_get_shader_param;
733 r300screen->screen.get_paramf = r300_get_paramf;
734 r300screen->screen.get_video_param = r300_get_video_param;
735 r300screen->screen.is_format_supported = r300_is_format_supported;
736 r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
737 r300screen->screen.context_create = r300_create_context;
738 r300screen->screen.fence_reference = r300_fence_reference;
739 r300screen->screen.fence_finish = r300_fence_finish;
740
741 r300_init_screen_resource_functions(r300screen);
742
743 util_format_s3tc_init();
744 pipe_mutex_init(r300screen->cmask_mutex);
745
746 return &r300screen->screen;
747 }