src/gallium/drivers/r300/r300_screen.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #include "util/u_format.h"
  25 #include "util/u_format_s3tc.h"
  26 #include "util/u_memory.h"
  27 #include "os/os_time.h"
  28 #include "vl/vl_decoder.h"
  29 #include "vl/vl_video_buffer.h"
  30
  31 #include "r300_context.h"
  32 #include "r300_texture.h"
  33 #include "r300_screen_buffer.h"
  34 #include "r300_state_inlines.h"
  35 #include "r300_public.h"
  36
  37 #include "draw/draw_context.h"
  38
  39 /* Return the identifier behind whom the brave coders responsible for this
  40  * amalgamation of code, sweat, and duct tape, routinely obscure their names.
  41  *
  42  * ...I should have just put "Corbin Simpson", but I'm not that cool.
  43  *
  44  * (Or egotistical. Yet.) */
  45 static const char* r300_get_vendor(struct pipe_screen* pscreen)
  46 {
  47     return "X.Org R300 Project";
  48 }
  49
  50 static const char* chip_families[] = {
  51     "unknown",
  52     "ATI R300",
  53     "ATI R350",
  54     "ATI RV350",
  55     "ATI RV370",
  56     "ATI RV380",
  57     "ATI RS400",
  58     "ATI RC410",
  59     "ATI RS480",
  60     "ATI R420",
  61     "ATI R423",
  62     "ATI R430",
  63     "ATI R480",
  64     "ATI R481",
  65     "ATI RV410",
  66     "ATI RS600",
  67     "ATI RS690",
  68     "ATI RS740",
  69     "ATI RV515",
  70     "ATI R520",
  71     "ATI RV530",
  72     "ATI R580",
  73     "ATI RV560",
  74     "ATI RV570"
  75 };
  76
  77 static const char* r300_get_name(struct pipe_screen* pscreen)
  78 {
  79     struct r300_screen* r300screen = r300_screen(pscreen);
  80
  81     return chip_families[r300screen->caps.family];
  82 }
  83
  84 static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
  85 {
  86     struct r300_screen* r300screen = r300_screen(pscreen);
  87     boolean is_r500 = r300screen->caps.is_r500;
  88
  89     switch (param) {
  90         /* Supported features (boolean caps). */
  91         case PIPE_CAP_NPOT_TEXTURES:
  92         case PIPE_CAP_TWO_SIDED_STENCIL:
  93         case PIPE_CAP_ANISOTROPIC_FILTER:
  94         case PIPE_CAP_POINT_SPRITE:
  95         case PIPE_CAP_OCCLUSION_QUERY:
  96         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  97         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  98         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  99         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 100         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 101         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 102         case PIPE_CAP_CONDITIONAL_RENDER:
 103         case PIPE_CAP_TEXTURE_BARRIER:
 104         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 105         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 106         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 107         case PIPE_CAP_USER_INDEX_BUFFERS:
 108         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 109         case PIPE_CAP_DEPTH_CLIP_DISABLE: /* XXX implemented, but breaks Regnum Online */
 110             return 1;
 111
 112         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 113             return R300_BUFFER_ALIGNMENT;
 114
 115         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 116             return 16;
 117
 118         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 119             return 120;
 120
 121         /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
 122         case PIPE_CAP_TEXTURE_SWIZZLE:
 123             return util_format_s3tc_enabled ? r300screen->caps.dxtc_swizzle : 1;
 124
 125         /* Supported on r500 only. */
 126         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 127         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 128         case PIPE_CAP_SM3:
 129             return is_r500 ? 1 : 0;
 130
 131         /* Unsupported features. */
 132         case PIPE_CAP_QUERY_TIME_ELAPSED:
 133         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 134         case PIPE_CAP_INDEP_BLEND_ENABLE:
 135         case PIPE_CAP_INDEP_BLEND_FUNC:
 136         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 137         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 138         case PIPE_CAP_TGSI_INSTANCEID:
 139         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 140         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 141         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 142         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 143         case PIPE_CAP_SCALED_RESOLVE:
 144         case PIPE_CAP_MIN_TEXEL_OFFSET:
 145         case PIPE_CAP_MAX_TEXEL_OFFSET:
 146         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 147         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 148         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 149         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 150         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 151         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 152         case PIPE_CAP_COMPUTE:
 153         case PIPE_CAP_START_INSTANCE:
 154         case PIPE_CAP_QUERY_TIMESTAMP:
 155         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 156         case PIPE_CAP_CUBE_MAP_ARRAY:
 157         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 158             return 0;
 159
 160         /* SWTCL-only features. */
 161         case PIPE_CAP_PRIMITIVE_RESTART:
 162         case PIPE_CAP_USER_VERTEX_BUFFERS:
 163             return !r300screen->caps.has_tcl;
 164
 165         /* HWTCL-only features / limitations. */
 166         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 167         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 168         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 169             return r300screen->caps.has_tcl;
 170
 171         /* Texturing. */
 172         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 173             return r300screen->caps.num_tex_units;
 174         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 175         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 176         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 177             /* 13 == 4096, 12 == 2048 */
 178             return is_r500 ? 13 : 12;
 179
 180         /* Render targets. */
 181         case PIPE_CAP_MAX_RENDER_TARGETS:
 182             return 4;
 183     }
 184     return 0;
 185 }
 186
 187 static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
 188 {
 189    struct r300_screen* r300screen = r300_screen(pscreen);
 190    boolean is_r400 = r300screen->caps.is_r400;
 191    boolean is_r500 = r300screen->caps.is_r500;
 192
 193    switch (shader) {
 194     case PIPE_SHADER_FRAGMENT:
 195         switch (param)
 196         {
 197         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 198             return is_r500 || is_r400 ? 512 : 96;
 199         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 200             return is_r500 || is_r400 ? 512 : 64;
 201         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 202             return is_r500 || is_r400 ? 512 : 32;
 203         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 204             return is_r500 ? 511 : 4;
 205         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 206             return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
 207             /* Fragment shader limits. */
 208         case PIPE_SHADER_CAP_MAX_INPUTS:
 209             /* 2 colors + 8 texcoords are always supported
 210              * (minus fog and wpos).
 211              *
 212              * R500 has the ability to turn 3rd and 4th color into
 213              * additional texcoords but there is no two-sided color
 214              * selection then. However the facing bit can be used instead. */
 215             return 10;
 216         case PIPE_SHADER_CAP_MAX_CONSTS:
 217             return is_r500 ? 256 : 32;
 218         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 219             return 1;
 220         case PIPE_SHADER_CAP_MAX_TEMPS:
 221             return is_r500 ? 128 : is_r400 ? 64 : 32;
 222         case PIPE_SHADER_CAP_MAX_PREDS:
 223             return is_r500 ? 1 : 0;
 224         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 225            return r300screen->caps.num_tex_units;
 226         case PIPE_SHADER_CAP_MAX_ADDRS:
 227         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 228         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 229         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 230         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 231         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 232         case PIPE_SHADER_CAP_SUBROUTINES:
 233         case PIPE_SHADER_CAP_INTEGERS:
 234             return 0;
 235         case PIPE_SHADER_CAP_PREFERRED_IR:
 236             return PIPE_SHADER_IR_TGSI;
 237         }
 238         break;
 239     case PIPE_SHADER_VERTEX:
 240         switch (param)
 241         {
 242         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 243         case PIPE_SHADER_CAP_SUBROUTINES:
 244             return 0;
 245         default:;
 246         }
 247
 248         if (!r300screen->caps.has_tcl) {
 249             return draw_get_shader_param(shader, param);
 250         }
 251
 252         switch (param)
 253         {
 254         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 255         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 256             return is_r500 ? 1024 : 256;
 257         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 258             return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
 259         case PIPE_SHADER_CAP_MAX_INPUTS:
 260             return 16;
 261         case PIPE_SHADER_CAP_MAX_CONSTS:
 262             return 256;
 263         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 264             return 1;
 265         case PIPE_SHADER_CAP_MAX_TEMPS:
 266             return 32;
 267         case PIPE_SHADER_CAP_MAX_ADDRS:
 268             return 1; /* XXX guessed */
 269         case PIPE_SHADER_CAP_MAX_PREDS:
 270             return is_r500 ? 4 : 0; /* XXX guessed. */
 271         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 272             return 1;
 273         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 274         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 275         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 276         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 277         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 278         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 279         case PIPE_SHADER_CAP_SUBROUTINES:
 280         case PIPE_SHADER_CAP_INTEGERS:
 281         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 282             return 0;
 283         case PIPE_SHADER_CAP_PREFERRED_IR:
 284             return PIPE_SHADER_IR_TGSI;
 285         }
 286         break;
 287     }
 288     return 0;
 289 }
 290
 291 static float r300_get_paramf(struct pipe_screen* pscreen,
 292                              enum pipe_capf param)
 293 {
 294     struct r300_screen* r300screen = r300_screen(pscreen);
 295
 296     switch (param) {
 297         case PIPE_CAPF_MAX_LINE_WIDTH:
 298         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 299         case PIPE_CAPF_MAX_POINT_WIDTH:
 300         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 301             /* The maximum dimensions of the colorbuffer are our practical
 302              * rendering limits. 2048 pixels should be enough for anybody. */
 303             if (r300screen->caps.is_r500) {
 304                 return 4096.0f;
 305             } else if (r300screen->caps.is_r400) {
 306                 return 4021.0f;
 307             } else {
 308                 return 2560.0f;
 309             }
 310         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 311             return 16.0f;
 312         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 313             return 16.0f;
 314         case PIPE_CAPF_GUARD_BAND_LEFT:
 315         case PIPE_CAPF_GUARD_BAND_TOP:
 316         case PIPE_CAPF_GUARD_BAND_RIGHT:
 317         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 318             /* XXX I don't know what these should be but the least we can do is
 319              * silence the potential error message */
 320             return 0.0f;
 321         default:
 322             debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
 323                          param);
 324             return 0.0f;
 325     }
 326 }
 327
 328 static int r300_get_video_param(struct pipe_screen *screen,
 329                                 enum pipe_video_profile profile,
 330                                 enum pipe_video_cap param)
 331 {
 332    switch (param) {
 333       case PIPE_VIDEO_CAP_SUPPORTED:
 334          return vl_profile_supported(screen, profile);
 335       case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 336          return 0;
 337       case PIPE_VIDEO_CAP_MAX_WIDTH:
 338       case PIPE_VIDEO_CAP_MAX_HEIGHT:
 339          return vl_video_buffer_max_size(screen);
 340       case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 341          return PIPE_FORMAT_NV12;
 342       case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 343          return false;
 344       case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 345          return false;
 346       case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 347          return true;
 348       default:
 349          return 0;
 350    }
 351 }
 352
 353 /**
 354  * Whether the format matches:
 355  *   PIPE_FORMAT_?10?10?10?2_UNORM
 356  */
 357 static INLINE boolean
 358 util_format_is_rgba1010102_variant(const struct util_format_description *desc)
 359 {
 360    static const unsigned size[4] = {10, 10, 10, 2};
 361    unsigned chan;
 362
 363    if (desc->block.width != 1 ||
 364        desc->block.height != 1 ||
 365        desc->block.bits != 32)
 366       return FALSE;
 367
 368    for (chan = 0; chan < 4; ++chan) {
 369       if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
 370          desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
 371          return FALSE;
 372       if (desc->channel[chan].size != size[chan])
 373          return FALSE;
 374    }
 375
 376    return TRUE;
 377 }
 378
 379 static boolean r300_is_format_supported(struct pipe_screen* screen,
 380                                         enum pipe_format format,
 381                                         enum pipe_texture_target target,
 382                                         unsigned sample_count,
 383                                         unsigned usage)
 384 {
 385     uint32_t retval = 0;
 386     boolean drm_2_8_0 = r300_screen(screen)->info.drm_minor >= 8;
 387     boolean is_r500 = r300_screen(screen)->caps.is_r500;
 388     boolean is_r400 = r300_screen(screen)->caps.is_r400;
 389     boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
 390                               format == PIPE_FORMAT_R10G10B10X2_SNORM ||
 391                               format == PIPE_FORMAT_B10G10R10A2_UNORM ||
 392                               format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
 393     boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
 394                        format == PIPE_FORMAT_RGTC1_SNORM ||
 395                        format == PIPE_FORMAT_LATC1_UNORM ||
 396                        format == PIPE_FORMAT_LATC1_SNORM;
 397     boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
 398                        format == PIPE_FORMAT_RGTC2_SNORM ||
 399                        format == PIPE_FORMAT_LATC2_UNORM ||
 400                        format == PIPE_FORMAT_LATC2_SNORM;
 401     boolean is_x16f_xy16f = format == PIPE_FORMAT_R16_FLOAT ||
 402                             format == PIPE_FORMAT_R16G16_FLOAT ||
 403                             format == PIPE_FORMAT_A16_FLOAT ||
 404                             format == PIPE_FORMAT_L16_FLOAT ||
 405                             format == PIPE_FORMAT_L16A16_FLOAT ||
 406                             format == PIPE_FORMAT_I16_FLOAT;
 407     boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
 408                             format == PIPE_FORMAT_R16G16_FLOAT ||
 409                             format == PIPE_FORMAT_R16G16B16_FLOAT ||
 410                             format == PIPE_FORMAT_R16G16B16A16_FLOAT;
 411     const struct util_format_description *desc;
 412
 413     if (!util_format_is_supported(format, usage))
 414        return FALSE;
 415
 416     /* Check multisampling support. */
 417     switch (sample_count) {
 418         case 0:
 419         case 1:
 420             break;
 421         case 2:
 422         case 4:
 423         case 6:
 424             /* We need DRM 2.8.0. */
 425             if (!drm_2_8_0) {
 426                 return FALSE;
 427             }
 428             /* Only support R500, because I didn't test older chipsets,
 429              * but MSAA should work there too. */
 430             if (!is_r500 && !debug_get_bool_option("RADEON_MSAA", FALSE)) {
 431                 return FALSE;
 432             }
 433             /* No texturing and scanout. */
 434             if (usage & (PIPE_BIND_SAMPLER_VIEW |
 435                          PIPE_BIND_DISPLAY_TARGET |
 436                          PIPE_BIND_SCANOUT)) {
 437                 return FALSE;
 438             }
 439
 440             desc = util_format_description(format);
 441
 442             if (is_r500) {
 443                 /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
 444                 if (!util_format_is_depth_or_stencil(format) &&
 445                     !util_format_is_rgba8_variant(desc) &&
 446                     !util_format_is_rgba1010102_variant(desc) &&
 447                     format != PIPE_FORMAT_R16G16B16A16_FLOAT) {
 448                     return FALSE;
 449                 }
 450             } else {
 451                 /* Only allow depth/stencil, RGBA8. */
 452                 if (!util_format_is_depth_or_stencil(format) &&
 453                     !util_format_is_rgba8_variant(desc)) {
 454                     return FALSE;
 455                 }
 456             }
 457             break;
 458         default:
 459             return FALSE;
 460     }
 461
 462     /* Check sampler format support. */
 463     if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 464         /* ATI1N is r5xx-only. */
 465         (is_r500 || !is_ati1n) &&
 466         /* ATI2N is supported on r4xx-r5xx. */
 467         (is_r400 || is_r500 || !is_ati2n) &&
 468         /* R16F and RG16F texture support was added in as late as DRM 2.8.0 */
 469         (drm_2_8_0 || !is_x16f_xy16f) &&
 470         r300_is_sampler_format_supported(format)) {
 471         retval |= PIPE_BIND_SAMPLER_VIEW;
 472     }
 473
 474     /* Check colorbuffer format support. */
 475     if ((usage & (PIPE_BIND_RENDER_TARGET |
 476                   PIPE_BIND_DISPLAY_TARGET |
 477                   PIPE_BIND_SCANOUT |
 478                   PIPE_BIND_SHARED)) &&
 479         /* 2101010 cannot be rendered to on non-r5xx. */
 480         (!is_color2101010 || (is_r500 && drm_2_8_0)) &&
 481         r300_is_colorbuffer_format_supported(format)) {
 482         retval |= usage &
 483             (PIPE_BIND_RENDER_TARGET |
 484              PIPE_BIND_DISPLAY_TARGET |
 485              PIPE_BIND_SCANOUT |
 486              PIPE_BIND_SHARED);
 487     }
 488
 489     /* Check depth-stencil format support. */
 490     if (usage & PIPE_BIND_DEPTH_STENCIL &&
 491         r300_is_zs_format_supported(format)) {
 492         retval |= PIPE_BIND_DEPTH_STENCIL;
 493     }
 494
 495     /* Check vertex buffer format support. */
 496     if (usage & PIPE_BIND_VERTEX_BUFFER) {
 497         if (r300_screen(screen)->caps.has_tcl) {
 498             /* Half float is supported on >= R400. */
 499             if ((is_r400 || is_r500 || !is_half_float) &&
 500                 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
 501                 retval |= PIPE_BIND_VERTEX_BUFFER;
 502             }
 503         } else {
 504             /* SW TCL */
 505             if (!util_format_is_pure_integer(format)) {
 506                 retval |= PIPE_BIND_VERTEX_BUFFER;
 507             }
 508         }
 509     }
 510
 511     /* Transfers are always supported. */
 512     if (usage & PIPE_BIND_TRANSFER_READ)
 513         retval |= PIPE_BIND_TRANSFER_READ;
 514     if (usage & PIPE_BIND_TRANSFER_WRITE)
 515         retval |= PIPE_BIND_TRANSFER_WRITE;
 516
 517     return retval == usage;
 518 }
 519
 520 static void r300_destroy_screen(struct pipe_screen* pscreen)
 521 {
 522     struct r300_screen* r300screen = r300_screen(pscreen);
 523     struct radeon_winsys *rws = radeon_winsys(pscreen);
 524
 525     pipe_mutex_destroy(r300screen->cmask_mutex);
 526
 527     if (rws)
 528       rws->destroy(rws);
 529
 530     FREE(r300screen);
 531 }
 532
 533 static void r300_fence_reference(struct pipe_screen *screen,
 534                                  struct pipe_fence_handle **ptr,
 535                                  struct pipe_fence_handle *fence)
 536 {
 537     pb_reference((struct pb_buffer**)ptr,
 538                              (struct pb_buffer*)fence);
 539 }
 540
 541 static boolean r300_fence_signalled(struct pipe_screen *screen,
 542                                     struct pipe_fence_handle *fence)
 543 {
 544     struct radeon_winsys *rws = r300_screen(screen)->rws;
 545     struct pb_buffer *rfence = (struct pb_buffer*)fence;
 546
 547     return !rws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE);
 548 }
 549
 550 static boolean r300_fence_finish(struct pipe_screen *screen,
 551                                  struct pipe_fence_handle *fence,
 552                                  uint64_t timeout)
 553 {
 554     struct radeon_winsys *rws = r300_screen(screen)->rws;
 555     struct pb_buffer *rfence = (struct pb_buffer*)fence;
 556
 557     if (timeout != PIPE_TIMEOUT_INFINITE) {
 558         int64_t start_time = os_time_get();
 559
 560         /* Convert to microseconds. */
 561         timeout /= 1000;
 562
 563         /* Wait in a loop. */
 564         while (rws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE)) {
 565             if (os_time_get() - start_time >= timeout) {
 566                 return FALSE;
 567             }
 568             os_time_sleep(10);
 569         }
 570         return TRUE;
 571     }
 572
 573     rws->buffer_wait(rfence, RADEON_USAGE_READWRITE);
 574     return TRUE;
 575 }
 576
 577 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws)
 578 {
 579     struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
 580
 581     if (!r300screen) {
 582         FREE(r300screen);
 583         return NULL;
 584     }
 585
 586     rws->query_info(rws, &r300screen->info);
 587
 588     r300_init_debug(r300screen);
 589     r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
 590
 591     if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
 592         r300screen->caps.zmask_ram = 0;
 593     if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
 594         r300screen->caps.hiz_ram = 0;
 595
 596     if (r300screen->info.drm_minor < 8)
 597         r300screen->caps.has_us_format = FALSE;
 598
 599     r300screen->rws = rws;
 600     r300screen->screen.destroy = r300_destroy_screen;
 601     r300screen->screen.get_name = r300_get_name;
 602     r300screen->screen.get_vendor = r300_get_vendor;
 603     r300screen->screen.get_param = r300_get_param;
 604     r300screen->screen.get_shader_param = r300_get_shader_param;
 605     r300screen->screen.get_paramf = r300_get_paramf;
 606     r300screen->screen.get_video_param = r300_get_video_param;
 607     r300screen->screen.is_format_supported = r300_is_format_supported;
 608     r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 609     r300screen->screen.context_create = r300_create_context;
 610     r300screen->screen.fence_reference = r300_fence_reference;
 611     r300screen->screen.fence_signalled = r300_fence_signalled;
 612     r300screen->screen.fence_finish = r300_fence_finish;
 613
 614     r300_init_screen_resource_functions(r300screen);
 615
 616     util_format_s3tc_init();
 617     pipe_mutex_init(r300screen->cmask_mutex);
 618
 619     return &r300screen->screen;
 620 }