gallium: plumb context priority through to driver
[mesa.git] / src / gallium / drivers / r300 / r300_screen.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "util/u_format.h"
25 #include "util/u_format_s3tc.h"
26 #include "util/u_memory.h"
27 #include "util/os_time.h"
28 #include "vl/vl_decoder.h"
29 #include "vl/vl_video_buffer.h"
30
31 #include "r300_context.h"
32 #include "r300_texture.h"
33 #include "r300_screen_buffer.h"
34 #include "r300_state_inlines.h"
35 #include "r300_public.h"
36
37 #include "draw/draw_context.h"
38
39 /* Return the identifier behind whom the brave coders responsible for this
40 * amalgamation of code, sweat, and duct tape, routinely obscure their names.
41 *
42 * ...I should have just put "Corbin Simpson", but I'm not that cool.
43 *
44 * (Or egotistical. Yet.) */
45 static const char* r300_get_vendor(struct pipe_screen* pscreen)
46 {
47 return "X.Org R300 Project";
48 }
49
50 static const char* r300_get_device_vendor(struct pipe_screen* pscreen)
51 {
52 return "ATI";
53 }
54
55 static const char* chip_families[] = {
56 "unknown",
57 "ATI R300",
58 "ATI R350",
59 "ATI RV350",
60 "ATI RV370",
61 "ATI RV380",
62 "ATI RS400",
63 "ATI RC410",
64 "ATI RS480",
65 "ATI R420",
66 "ATI R423",
67 "ATI R430",
68 "ATI R480",
69 "ATI R481",
70 "ATI RV410",
71 "ATI RS600",
72 "ATI RS690",
73 "ATI RS740",
74 "ATI RV515",
75 "ATI R520",
76 "ATI RV530",
77 "ATI R580",
78 "ATI RV560",
79 "ATI RV570"
80 };
81
82 static const char* r300_get_name(struct pipe_screen* pscreen)
83 {
84 struct r300_screen* r300screen = r300_screen(pscreen);
85
86 return chip_families[r300screen->caps.family];
87 }
88
89 static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
90 {
91 struct r300_screen* r300screen = r300_screen(pscreen);
92 boolean is_r500 = r300screen->caps.is_r500;
93
94 switch (param) {
95 /* Supported features (boolean caps). */
96 case PIPE_CAP_NPOT_TEXTURES:
97 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
98 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
99 case PIPE_CAP_TWO_SIDED_STENCIL:
100 case PIPE_CAP_ANISOTROPIC_FILTER:
101 case PIPE_CAP_POINT_SPRITE:
102 case PIPE_CAP_OCCLUSION_QUERY:
103 case PIPE_CAP_TEXTURE_SHADOW_MAP:
104 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
105 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
106 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
107 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
108 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
109 case PIPE_CAP_CONDITIONAL_RENDER:
110 case PIPE_CAP_TEXTURE_BARRIER:
111 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
112 case PIPE_CAP_USER_CONSTANT_BUFFERS:
113 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
114 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
115 case PIPE_CAP_CLIP_HALFZ:
116 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
117 return 1;
118
119 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
120 return R300_BUFFER_ALIGNMENT;
121
122 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
123 return 16;
124
125 case PIPE_CAP_GLSL_FEATURE_LEVEL:
126 return 120;
127
128 /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
129 case PIPE_CAP_TEXTURE_SWIZZLE:
130 return r300screen->caps.dxtc_swizzle;
131
132 /* We don't support color clamping on r500, so that we can use color
133 * intepolators for generic varyings. */
134 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
135 return !is_r500;
136
137 /* Supported on r500 only. */
138 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
139 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
140 case PIPE_CAP_SM3:
141 return is_r500 ? 1 : 0;
142
143 /* Unsupported features. */
144 case PIPE_CAP_QUERY_TIME_ELAPSED:
145 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
146 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
147 case PIPE_CAP_INDEP_BLEND_ENABLE:
148 case PIPE_CAP_INDEP_BLEND_FUNC:
149 case PIPE_CAP_DEPTH_CLIP_DISABLE:
150 case PIPE_CAP_SHADER_STENCIL_EXPORT:
151 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
152 case PIPE_CAP_TGSI_INSTANCEID:
153 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
154 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
155 case PIPE_CAP_SEAMLESS_CUBE_MAP:
156 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
157 case PIPE_CAP_MIN_TEXEL_OFFSET:
158 case PIPE_CAP_MAX_TEXEL_OFFSET:
159 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
160 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
161 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
162 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
163 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
164 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
165 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
166 case PIPE_CAP_MAX_VERTEX_STREAMS:
167 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
168 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
169 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
170 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
171 case PIPE_CAP_COMPUTE:
172 case PIPE_CAP_START_INSTANCE:
173 case PIPE_CAP_QUERY_TIMESTAMP:
174 case PIPE_CAP_TEXTURE_MULTISAMPLE:
175 case PIPE_CAP_CUBE_MAP_ARRAY:
176 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
177 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
178 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
179 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
180 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
181 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
182 case PIPE_CAP_TEXTURE_GATHER_SM5:
183 case PIPE_CAP_TEXTURE_QUERY_LOD:
184 case PIPE_CAP_FAKE_SW_MSAA:
185 case PIPE_CAP_SAMPLE_SHADING:
186 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
187 case PIPE_CAP_DRAW_INDIRECT:
188 case PIPE_CAP_MULTI_DRAW_INDIRECT:
189 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
190 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
191 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
192 case PIPE_CAP_SAMPLER_VIEW_TARGET:
193 case PIPE_CAP_VERTEXID_NOBASE:
194 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
195 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
196 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
197 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
198 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
199 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
200 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
201 case PIPE_CAP_DEPTH_BOUNDS_TEST:
202 case PIPE_CAP_TGSI_TXQS:
203 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
204 case PIPE_CAP_SHAREABLE_SHADERS:
205 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
206 case PIPE_CAP_CLEAR_TEXTURE:
207 case PIPE_CAP_DRAW_PARAMETERS:
208 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
209 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
210 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
211 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
212 case PIPE_CAP_INVALIDATE_BUFFER:
213 case PIPE_CAP_GENERATE_MIPMAP:
214 case PIPE_CAP_STRING_MARKER:
215 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
216 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
217 case PIPE_CAP_QUERY_BUFFER_OBJECT:
218 case PIPE_CAP_QUERY_MEMORY_INFO:
219 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
220 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
221 case PIPE_CAP_CULL_DISTANCE:
222 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
223 case PIPE_CAP_TGSI_VOTE:
224 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
225 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
226 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
227 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
228 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
229 case PIPE_CAP_NATIVE_FENCE_FD:
230 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
231 case PIPE_CAP_TGSI_FS_FBFETCH:
232 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
233 case PIPE_CAP_DOUBLES:
234 case PIPE_CAP_INT64:
235 case PIPE_CAP_INT64_DIVMOD:
236 case PIPE_CAP_TGSI_TEX_TXF_LZ:
237 case PIPE_CAP_TGSI_CLOCK:
238 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
239 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
240 case PIPE_CAP_TGSI_BALLOT:
241 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
242 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
243 case PIPE_CAP_POST_DEPTH_COVERAGE:
244 case PIPE_CAP_BINDLESS_TEXTURE:
245 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
246 case PIPE_CAP_QUERY_SO_OVERFLOW:
247 case PIPE_CAP_MEMOBJ:
248 case PIPE_CAP_LOAD_CONSTBUF:
249 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
250 case PIPE_CAP_TILE_RASTER_ORDER:
251 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
252 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
253 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
254 return 0;
255
256 /* SWTCL-only features. */
257 case PIPE_CAP_PRIMITIVE_RESTART:
258 case PIPE_CAP_USER_VERTEX_BUFFERS:
259 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
260 return !r300screen->caps.has_tcl;
261
262 /* HWTCL-only features / limitations. */
263 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
264 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
265 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
266 return r300screen->caps.has_tcl;
267 case PIPE_CAP_TGSI_TEXCOORD:
268 return 0;
269
270 /* Texturing. */
271 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
272 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
273 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
274 /* 13 == 4096, 12 == 2048 */
275 return is_r500 ? 13 : 12;
276
277 /* Render targets. */
278 case PIPE_CAP_MAX_RENDER_TARGETS:
279 return 4;
280 case PIPE_CAP_ENDIANNESS:
281 return PIPE_ENDIAN_LITTLE;
282
283 case PIPE_CAP_MAX_VIEWPORTS:
284 return 1;
285
286 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
287 return 2048;
288
289 case PIPE_CAP_VENDOR_ID:
290 return 0x1002;
291 case PIPE_CAP_DEVICE_ID:
292 return r300screen->info.pci_id;
293 case PIPE_CAP_ACCELERATED:
294 return 1;
295 case PIPE_CAP_VIDEO_MEMORY:
296 return r300screen->info.vram_size >> 20;
297 case PIPE_CAP_UMA:
298 return 0;
299 case PIPE_CAP_PCI_GROUP:
300 return r300screen->info.pci_domain;
301 case PIPE_CAP_PCI_BUS:
302 return r300screen->info.pci_bus;
303 case PIPE_CAP_PCI_DEVICE:
304 return r300screen->info.pci_dev;
305 case PIPE_CAP_PCI_FUNCTION:
306 return r300screen->info.pci_func;
307 }
308 return 0;
309 }
310
311 static int r300_get_shader_param(struct pipe_screen *pscreen,
312 enum pipe_shader_type shader,
313 enum pipe_shader_cap param)
314 {
315 struct r300_screen* r300screen = r300_screen(pscreen);
316 boolean is_r400 = r300screen->caps.is_r400;
317 boolean is_r500 = r300screen->caps.is_r500;
318
319 switch (shader) {
320 case PIPE_SHADER_FRAGMENT:
321 switch (param)
322 {
323 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
324 return is_r500 || is_r400 ? 512 : 96;
325 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
326 return is_r500 || is_r400 ? 512 : 64;
327 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
328 return is_r500 || is_r400 ? 512 : 32;
329 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
330 return is_r500 ? 511 : 4;
331 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
332 return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
333 /* Fragment shader limits. */
334 case PIPE_SHADER_CAP_MAX_INPUTS:
335 /* 2 colors + 8 texcoords are always supported
336 * (minus fog and wpos).
337 *
338 * R500 has the ability to turn 3rd and 4th color into
339 * additional texcoords but there is no two-sided color
340 * selection then. However the facing bit can be used instead. */
341 return 10;
342 case PIPE_SHADER_CAP_MAX_OUTPUTS:
343 return 4;
344 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
345 return (is_r500 ? 256 : 32) * sizeof(float[4]);
346 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
347 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
348 return 1;
349 case PIPE_SHADER_CAP_MAX_TEMPS:
350 return is_r500 ? 128 : is_r400 ? 64 : 32;
351 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
352 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
353 return r300screen->caps.num_tex_units;
354 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
355 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
356 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
357 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
358 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
359 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
360 case PIPE_SHADER_CAP_SUBROUTINES:
361 case PIPE_SHADER_CAP_INTEGERS:
362 case PIPE_SHADER_CAP_INT64_ATOMICS:
363 case PIPE_SHADER_CAP_FP16:
364 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
365 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
366 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
367 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
368 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
369 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
370 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
371 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
372 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
373 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
374 return 0;
375 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
376 return 32;
377 case PIPE_SHADER_CAP_PREFERRED_IR:
378 return PIPE_SHADER_IR_TGSI;
379 case PIPE_SHADER_CAP_SUPPORTED_IRS:
380 return 0;
381 }
382 break;
383 case PIPE_SHADER_VERTEX:
384 switch (param)
385 {
386 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
387 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
388 case PIPE_SHADER_CAP_SUBROUTINES:
389 return 0;
390 default:;
391 }
392
393 if (!r300screen->caps.has_tcl) {
394 return draw_get_shader_param(shader, param);
395 }
396
397 switch (param)
398 {
399 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
400 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
401 return is_r500 ? 1024 : 256;
402 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
403 return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
404 case PIPE_SHADER_CAP_MAX_INPUTS:
405 return 16;
406 case PIPE_SHADER_CAP_MAX_OUTPUTS:
407 return 10;
408 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
409 return 256 * sizeof(float[4]);
410 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
411 return 1;
412 case PIPE_SHADER_CAP_MAX_TEMPS:
413 return 32;
414 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
415 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
416 return 1;
417 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
418 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
419 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
420 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
421 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
422 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
423 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
424 case PIPE_SHADER_CAP_SUBROUTINES:
425 case PIPE_SHADER_CAP_INTEGERS:
426 case PIPE_SHADER_CAP_FP16:
427 case PIPE_SHADER_CAP_INT64_ATOMICS:
428 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
429 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
430 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
431 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
432 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
433 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
434 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
435 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
436 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
437 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
438 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
439 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
440 return 0;
441 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
442 return 32;
443 case PIPE_SHADER_CAP_PREFERRED_IR:
444 return PIPE_SHADER_IR_TGSI;
445 case PIPE_SHADER_CAP_SUPPORTED_IRS:
446 return 0;
447 }
448 break;
449 default:
450 ; /* nothing */
451 }
452 return 0;
453 }
454
455 static float r300_get_paramf(struct pipe_screen* pscreen,
456 enum pipe_capf param)
457 {
458 struct r300_screen* r300screen = r300_screen(pscreen);
459
460 switch (param) {
461 case PIPE_CAPF_MAX_LINE_WIDTH:
462 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
463 case PIPE_CAPF_MAX_POINT_WIDTH:
464 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
465 /* The maximum dimensions of the colorbuffer are our practical
466 * rendering limits. 2048 pixels should be enough for anybody. */
467 if (r300screen->caps.is_r500) {
468 return 4096.0f;
469 } else if (r300screen->caps.is_r400) {
470 return 4021.0f;
471 } else {
472 return 2560.0f;
473 }
474 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
475 return 16.0f;
476 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
477 return 16.0f;
478 case PIPE_CAPF_GUARD_BAND_LEFT:
479 case PIPE_CAPF_GUARD_BAND_TOP:
480 case PIPE_CAPF_GUARD_BAND_RIGHT:
481 case PIPE_CAPF_GUARD_BAND_BOTTOM:
482 return 0.0f;
483 default:
484 debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
485 param);
486 return 0.0f;
487 }
488 }
489
490 static int r300_get_video_param(struct pipe_screen *screen,
491 enum pipe_video_profile profile,
492 enum pipe_video_entrypoint entrypoint,
493 enum pipe_video_cap param)
494 {
495 switch (param) {
496 case PIPE_VIDEO_CAP_SUPPORTED:
497 return vl_profile_supported(screen, profile, entrypoint);
498 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
499 return 0;
500 case PIPE_VIDEO_CAP_MAX_WIDTH:
501 case PIPE_VIDEO_CAP_MAX_HEIGHT:
502 return vl_video_buffer_max_size(screen);
503 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
504 return PIPE_FORMAT_NV12;
505 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
506 return false;
507 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
508 return false;
509 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
510 return true;
511 case PIPE_VIDEO_CAP_MAX_LEVEL:
512 return vl_level_supported(screen, profile);
513 default:
514 return 0;
515 }
516 }
517
518 /**
519 * Whether the format matches:
520 * PIPE_FORMAT_?10?10?10?2_UNORM
521 */
522 static inline boolean
523 util_format_is_rgba1010102_variant(const struct util_format_description *desc)
524 {
525 static const unsigned size[4] = {10, 10, 10, 2};
526 unsigned chan;
527
528 if (desc->block.width != 1 ||
529 desc->block.height != 1 ||
530 desc->block.bits != 32)
531 return FALSE;
532
533 for (chan = 0; chan < 4; ++chan) {
534 if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
535 desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
536 return FALSE;
537 if (desc->channel[chan].size != size[chan])
538 return FALSE;
539 }
540
541 return TRUE;
542 }
543
544 static bool r300_is_blending_supported(struct r300_screen *rscreen,
545 enum pipe_format format)
546 {
547 int c;
548 const struct util_format_description *desc =
549 util_format_description(format);
550
551 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
552 return false;
553
554 c = util_format_get_first_non_void_channel(format);
555
556 /* RGBA16F */
557 if (rscreen->caps.is_r500 &&
558 desc->nr_channels == 4 &&
559 desc->channel[c].size == 16 &&
560 desc->channel[c].type == UTIL_FORMAT_TYPE_FLOAT)
561 return true;
562
563 if (desc->channel[c].normalized &&
564 desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED &&
565 desc->channel[c].size >= 4 &&
566 desc->channel[c].size <= 10) {
567 /* RGB10_A2, RGBA8, RGB5_A1, RGBA4, RGB565 */
568 if (desc->nr_channels >= 3)
569 return true;
570
571 if (format == PIPE_FORMAT_R8G8_UNORM)
572 return true;
573
574 /* R8, I8, L8, A8 */
575 if (desc->nr_channels == 1)
576 return true;
577 }
578
579 return false;
580 }
581
582 static boolean r300_is_format_supported(struct pipe_screen* screen,
583 enum pipe_format format,
584 enum pipe_texture_target target,
585 unsigned sample_count,
586 unsigned usage)
587 {
588 uint32_t retval = 0;
589 boolean is_r500 = r300_screen(screen)->caps.is_r500;
590 boolean is_r400 = r300_screen(screen)->caps.is_r400;
591 boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
592 format == PIPE_FORMAT_R10G10B10X2_SNORM ||
593 format == PIPE_FORMAT_B10G10R10A2_UNORM ||
594 format == PIPE_FORMAT_B10G10R10X2_UNORM ||
595 format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
596 boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
597 format == PIPE_FORMAT_RGTC1_SNORM ||
598 format == PIPE_FORMAT_LATC1_UNORM ||
599 format == PIPE_FORMAT_LATC1_SNORM;
600 boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
601 format == PIPE_FORMAT_RGTC2_SNORM ||
602 format == PIPE_FORMAT_LATC2_UNORM ||
603 format == PIPE_FORMAT_LATC2_SNORM;
604 boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
605 format == PIPE_FORMAT_R16G16_FLOAT ||
606 format == PIPE_FORMAT_R16G16B16_FLOAT ||
607 format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
608 format == PIPE_FORMAT_R16G16B16X16_FLOAT;
609 const struct util_format_description *desc;
610
611 if (!util_format_is_supported(format, usage))
612 return FALSE;
613
614 /* Check multisampling support. */
615 switch (sample_count) {
616 case 0:
617 case 1:
618 break;
619 case 2:
620 case 4:
621 case 6:
622 /* No texturing and scanout. */
623 if (usage & (PIPE_BIND_SAMPLER_VIEW |
624 PIPE_BIND_DISPLAY_TARGET |
625 PIPE_BIND_SCANOUT)) {
626 return FALSE;
627 }
628
629 desc = util_format_description(format);
630
631 if (is_r500) {
632 /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
633 if (!util_format_is_depth_or_stencil(format) &&
634 !util_format_is_rgba8_variant(desc) &&
635 !util_format_is_rgba1010102_variant(desc) &&
636 format != PIPE_FORMAT_R16G16B16A16_FLOAT &&
637 format != PIPE_FORMAT_R16G16B16X16_FLOAT) {
638 return FALSE;
639 }
640 } else {
641 /* Only allow depth/stencil, RGBA8. */
642 if (!util_format_is_depth_or_stencil(format) &&
643 !util_format_is_rgba8_variant(desc)) {
644 return FALSE;
645 }
646 }
647 break;
648 default:
649 return FALSE;
650 }
651
652 /* Check sampler format support. */
653 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
654 /* these two are broken for an unknown reason */
655 format != PIPE_FORMAT_R8G8B8X8_SNORM &&
656 format != PIPE_FORMAT_R16G16B16X16_SNORM &&
657 /* ATI1N is r5xx-only. */
658 (is_r500 || !is_ati1n) &&
659 /* ATI2N is supported on r4xx-r5xx. */
660 (is_r400 || is_r500 || !is_ati2n) &&
661 r300_is_sampler_format_supported(format)) {
662 retval |= PIPE_BIND_SAMPLER_VIEW;
663 }
664
665 /* Check colorbuffer format support. */
666 if ((usage & (PIPE_BIND_RENDER_TARGET |
667 PIPE_BIND_DISPLAY_TARGET |
668 PIPE_BIND_SCANOUT |
669 PIPE_BIND_SHARED |
670 PIPE_BIND_BLENDABLE)) &&
671 /* 2101010 cannot be rendered to on non-r5xx. */
672 (!is_color2101010 || is_r500) &&
673 r300_is_colorbuffer_format_supported(format)) {
674 retval |= usage &
675 (PIPE_BIND_RENDER_TARGET |
676 PIPE_BIND_DISPLAY_TARGET |
677 PIPE_BIND_SCANOUT |
678 PIPE_BIND_SHARED);
679
680 if (r300_is_blending_supported(r300_screen(screen), format)) {
681 retval |= usage & PIPE_BIND_BLENDABLE;
682 }
683 }
684
685 /* Check depth-stencil format support. */
686 if (usage & PIPE_BIND_DEPTH_STENCIL &&
687 r300_is_zs_format_supported(format)) {
688 retval |= PIPE_BIND_DEPTH_STENCIL;
689 }
690
691 /* Check vertex buffer format support. */
692 if (usage & PIPE_BIND_VERTEX_BUFFER) {
693 if (r300_screen(screen)->caps.has_tcl) {
694 /* Half float is supported on >= R400. */
695 if ((is_r400 || is_r500 || !is_half_float) &&
696 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
697 retval |= PIPE_BIND_VERTEX_BUFFER;
698 }
699 } else {
700 /* SW TCL */
701 if (!util_format_is_pure_integer(format)) {
702 retval |= PIPE_BIND_VERTEX_BUFFER;
703 }
704 }
705 }
706
707 return retval == usage;
708 }
709
710 static void r300_destroy_screen(struct pipe_screen* pscreen)
711 {
712 struct r300_screen* r300screen = r300_screen(pscreen);
713 struct radeon_winsys *rws = radeon_winsys(pscreen);
714
715 if (rws && !rws->unref(rws))
716 return;
717
718 mtx_destroy(&r300screen->cmask_mutex);
719 slab_destroy_parent(&r300screen->pool_transfers);
720
721 if (rws)
722 rws->destroy(rws);
723
724 FREE(r300screen);
725 }
726
727 static void r300_fence_reference(struct pipe_screen *screen,
728 struct pipe_fence_handle **ptr,
729 struct pipe_fence_handle *fence)
730 {
731 struct radeon_winsys *rws = r300_screen(screen)->rws;
732
733 rws->fence_reference(ptr, fence);
734 }
735
736 static boolean r300_fence_finish(struct pipe_screen *screen,
737 struct pipe_context *ctx,
738 struct pipe_fence_handle *fence,
739 uint64_t timeout)
740 {
741 struct radeon_winsys *rws = r300_screen(screen)->rws;
742
743 return rws->fence_wait(rws, fence, timeout);
744 }
745
746 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws,
747 const struct pipe_screen_config *config)
748 {
749 struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
750
751 if (!r300screen) {
752 FREE(r300screen);
753 return NULL;
754 }
755
756 rws->query_info(rws, &r300screen->info);
757
758 r300_init_debug(r300screen);
759 r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
760
761 if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
762 r300screen->caps.zmask_ram = 0;
763 if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
764 r300screen->caps.hiz_ram = 0;
765
766 r300screen->rws = rws;
767 r300screen->screen.destroy = r300_destroy_screen;
768 r300screen->screen.get_name = r300_get_name;
769 r300screen->screen.get_vendor = r300_get_vendor;
770 r300screen->screen.get_device_vendor = r300_get_device_vendor;
771 r300screen->screen.get_param = r300_get_param;
772 r300screen->screen.get_shader_param = r300_get_shader_param;
773 r300screen->screen.get_paramf = r300_get_paramf;
774 r300screen->screen.get_video_param = r300_get_video_param;
775 r300screen->screen.is_format_supported = r300_is_format_supported;
776 r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
777 r300screen->screen.context_create = r300_create_context;
778 r300screen->screen.fence_reference = r300_fence_reference;
779 r300screen->screen.fence_finish = r300_fence_finish;
780
781 r300_init_screen_resource_functions(r300screen);
782
783 slab_create_parent(&r300screen->pool_transfers, sizeof(struct pipe_transfer), 64);
784
785 (void) mtx_init(&r300screen->cmask_mutex, mtx_plain);
786
787 return &r300screen->screen;
788 }