gallium: add support for AMD_vertex_shader_layer
[mesa.git] / src / gallium / drivers / r300 / r300_screen.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "util/u_format.h"
25 #include "util/u_format_s3tc.h"
26 #include "util/u_memory.h"
27 #include "os/os_time.h"
28 #include "vl/vl_decoder.h"
29 #include "vl/vl_video_buffer.h"
30
31 #include "r300_context.h"
32 #include "r300_texture.h"
33 #include "r300_screen_buffer.h"
34 #include "r300_state_inlines.h"
35 #include "r300_public.h"
36
37 #include "draw/draw_context.h"
38
39 /* Return the identifier behind whom the brave coders responsible for this
40 * amalgamation of code, sweat, and duct tape, routinely obscure their names.
41 *
42 * ...I should have just put "Corbin Simpson", but I'm not that cool.
43 *
44 * (Or egotistical. Yet.) */
45 static const char* r300_get_vendor(struct pipe_screen* pscreen)
46 {
47 return "X.Org R300 Project";
48 }
49
50 static const char* chip_families[] = {
51 "unknown",
52 "ATI R300",
53 "ATI R350",
54 "ATI RV350",
55 "ATI RV370",
56 "ATI RV380",
57 "ATI RS400",
58 "ATI RC410",
59 "ATI RS480",
60 "ATI R420",
61 "ATI R423",
62 "ATI R430",
63 "ATI R480",
64 "ATI R481",
65 "ATI RV410",
66 "ATI RS600",
67 "ATI RS690",
68 "ATI RS740",
69 "ATI RV515",
70 "ATI R520",
71 "ATI RV530",
72 "ATI R580",
73 "ATI RV560",
74 "ATI RV570"
75 };
76
77 static const char* r300_get_name(struct pipe_screen* pscreen)
78 {
79 struct r300_screen* r300screen = r300_screen(pscreen);
80
81 return chip_families[r300screen->caps.family];
82 }
83
84 static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
85 {
86 struct r300_screen* r300screen = r300_screen(pscreen);
87 boolean is_r500 = r300screen->caps.is_r500;
88
89 switch (param) {
90 /* Supported features (boolean caps). */
91 case PIPE_CAP_NPOT_TEXTURES:
92 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
93 case PIPE_CAP_TWO_SIDED_STENCIL:
94 case PIPE_CAP_ANISOTROPIC_FILTER:
95 case PIPE_CAP_POINT_SPRITE:
96 case PIPE_CAP_OCCLUSION_QUERY:
97 case PIPE_CAP_TEXTURE_SHADOW_MAP:
98 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
99 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
100 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
101 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
102 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
103 case PIPE_CAP_CONDITIONAL_RENDER:
104 case PIPE_CAP_TEXTURE_BARRIER:
105 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
106 case PIPE_CAP_USER_INDEX_BUFFERS:
107 case PIPE_CAP_USER_CONSTANT_BUFFERS:
108 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
109 return 1;
110
111 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
112 return R300_BUFFER_ALIGNMENT;
113
114 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
115 return 16;
116
117 case PIPE_CAP_GLSL_FEATURE_LEVEL:
118 return 120;
119
120 /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
121 case PIPE_CAP_TEXTURE_SWIZZLE:
122 return util_format_s3tc_enabled ? r300screen->caps.dxtc_swizzle : 1;
123
124 /* We don't support color clamping on r500, so that we can use color
125 * intepolators for generic varyings. */
126 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
127 return !is_r500;
128
129 /* Supported on r500 only. */
130 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
131 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
132 case PIPE_CAP_SM3:
133 return is_r500 ? 1 : 0;
134
135 /* Unsupported features. */
136 case PIPE_CAP_QUERY_TIME_ELAPSED:
137 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
138 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
139 case PIPE_CAP_INDEP_BLEND_ENABLE:
140 case PIPE_CAP_INDEP_BLEND_FUNC:
141 case PIPE_CAP_DEPTH_CLIP_DISABLE:
142 case PIPE_CAP_SHADER_STENCIL_EXPORT:
143 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
144 case PIPE_CAP_TGSI_INSTANCEID:
145 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
146 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
147 case PIPE_CAP_SEAMLESS_CUBE_MAP:
148 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
149 case PIPE_CAP_SCALED_RESOLVE:
150 case PIPE_CAP_MIN_TEXEL_OFFSET:
151 case PIPE_CAP_MAX_TEXEL_OFFSET:
152 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
153 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
154 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
155 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
156 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
157 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
158 case PIPE_CAP_COMPUTE:
159 case PIPE_CAP_START_INSTANCE:
160 case PIPE_CAP_QUERY_TIMESTAMP:
161 case PIPE_CAP_TEXTURE_MULTISAMPLE:
162 case PIPE_CAP_CUBE_MAP_ARRAY:
163 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
164 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
165 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
166 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
167 case PIPE_CAP_TGSI_VS_LAYER:
168 return 0;
169
170 /* SWTCL-only features. */
171 case PIPE_CAP_PRIMITIVE_RESTART:
172 case PIPE_CAP_USER_VERTEX_BUFFERS:
173 return !r300screen->caps.has_tcl;
174
175 /* HWTCL-only features / limitations. */
176 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
177 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
178 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
179 return r300screen->caps.has_tcl;
180 case PIPE_CAP_TGSI_TEXCOORD:
181 return 0;
182
183 /* Texturing. */
184 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
185 return r300screen->caps.num_tex_units;
186 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
187 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
188 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
189 /* 13 == 4096, 12 == 2048 */
190 return is_r500 ? 13 : 12;
191
192 /* Render targets. */
193 case PIPE_CAP_MAX_RENDER_TARGETS:
194 return 4;
195 case PIPE_CAP_ENDIANNESS:
196 return PIPE_ENDIAN_LITTLE;
197
198 case PIPE_CAP_MAX_VIEWPORTS:
199 return 1;
200 }
201 return 0;
202 }
203
204 static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
205 {
206 struct r300_screen* r300screen = r300_screen(pscreen);
207 boolean is_r400 = r300screen->caps.is_r400;
208 boolean is_r500 = r300screen->caps.is_r500;
209
210 switch (shader) {
211 case PIPE_SHADER_FRAGMENT:
212 switch (param)
213 {
214 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
215 return is_r500 || is_r400 ? 512 : 96;
216 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
217 return is_r500 || is_r400 ? 512 : 64;
218 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
219 return is_r500 || is_r400 ? 512 : 32;
220 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
221 return is_r500 ? 511 : 4;
222 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
223 return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
224 /* Fragment shader limits. */
225 case PIPE_SHADER_CAP_MAX_INPUTS:
226 /* 2 colors + 8 texcoords are always supported
227 * (minus fog and wpos).
228 *
229 * R500 has the ability to turn 3rd and 4th color into
230 * additional texcoords but there is no two-sided color
231 * selection then. However the facing bit can be used instead. */
232 return 10;
233 case PIPE_SHADER_CAP_MAX_CONSTS:
234 return is_r500 ? 256 : 32;
235 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
236 return 1;
237 case PIPE_SHADER_CAP_MAX_TEMPS:
238 return is_r500 ? 128 : is_r400 ? 64 : 32;
239 case PIPE_SHADER_CAP_MAX_PREDS:
240 return is_r500 ? 1 : 0;
241 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
242 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
243 return r300screen->caps.num_tex_units;
244 case PIPE_SHADER_CAP_MAX_ADDRS:
245 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
246 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
247 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
248 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
249 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
250 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
251 case PIPE_SHADER_CAP_SUBROUTINES:
252 case PIPE_SHADER_CAP_INTEGERS:
253 return 0;
254 case PIPE_SHADER_CAP_PREFERRED_IR:
255 return PIPE_SHADER_IR_TGSI;
256 }
257 break;
258 case PIPE_SHADER_VERTEX:
259 switch (param)
260 {
261 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
262 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
263 case PIPE_SHADER_CAP_SUBROUTINES:
264 return 0;
265 default:;
266 }
267
268 if (!r300screen->caps.has_tcl) {
269 return draw_get_shader_param(shader, param);
270 }
271
272 switch (param)
273 {
274 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
275 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
276 return is_r500 ? 1024 : 256;
277 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
278 return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
279 case PIPE_SHADER_CAP_MAX_INPUTS:
280 return 16;
281 case PIPE_SHADER_CAP_MAX_CONSTS:
282 return 256;
283 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
284 return 1;
285 case PIPE_SHADER_CAP_MAX_TEMPS:
286 return 32;
287 case PIPE_SHADER_CAP_MAX_ADDRS:
288 return 1; /* XXX guessed */
289 case PIPE_SHADER_CAP_MAX_PREDS:
290 return is_r500 ? 4 : 0; /* XXX guessed. */
291 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
292 return 1;
293 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
294 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
295 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
296 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
297 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
298 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
299 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
300 case PIPE_SHADER_CAP_SUBROUTINES:
301 case PIPE_SHADER_CAP_INTEGERS:
302 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
303 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
304 return 0;
305 case PIPE_SHADER_CAP_PREFERRED_IR:
306 return PIPE_SHADER_IR_TGSI;
307 }
308 break;
309 }
310 return 0;
311 }
312
313 static float r300_get_paramf(struct pipe_screen* pscreen,
314 enum pipe_capf param)
315 {
316 struct r300_screen* r300screen = r300_screen(pscreen);
317
318 switch (param) {
319 case PIPE_CAPF_MAX_LINE_WIDTH:
320 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
321 case PIPE_CAPF_MAX_POINT_WIDTH:
322 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
323 /* The maximum dimensions of the colorbuffer are our practical
324 * rendering limits. 2048 pixels should be enough for anybody. */
325 if (r300screen->caps.is_r500) {
326 return 4096.0f;
327 } else if (r300screen->caps.is_r400) {
328 return 4021.0f;
329 } else {
330 return 2560.0f;
331 }
332 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
333 return 16.0f;
334 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
335 return 16.0f;
336 case PIPE_CAPF_GUARD_BAND_LEFT:
337 case PIPE_CAPF_GUARD_BAND_TOP:
338 case PIPE_CAPF_GUARD_BAND_RIGHT:
339 case PIPE_CAPF_GUARD_BAND_BOTTOM:
340 /* XXX I don't know what these should be but the least we can do is
341 * silence the potential error message */
342 return 0.0f;
343 default:
344 debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
345 param);
346 return 0.0f;
347 }
348 }
349
350 static int r300_get_video_param(struct pipe_screen *screen,
351 enum pipe_video_profile profile,
352 enum pipe_video_entrypoint entrypoint,
353 enum pipe_video_cap param)
354 {
355 switch (param) {
356 case PIPE_VIDEO_CAP_SUPPORTED:
357 return vl_profile_supported(screen, profile, entrypoint);
358 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
359 return 0;
360 case PIPE_VIDEO_CAP_MAX_WIDTH:
361 case PIPE_VIDEO_CAP_MAX_HEIGHT:
362 return vl_video_buffer_max_size(screen);
363 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
364 return PIPE_FORMAT_NV12;
365 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
366 return false;
367 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
368 return false;
369 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
370 return true;
371 case PIPE_VIDEO_CAP_MAX_LEVEL:
372 return vl_level_supported(screen, profile);
373 default:
374 return 0;
375 }
376 }
377
378 /**
379 * Whether the format matches:
380 * PIPE_FORMAT_?10?10?10?2_UNORM
381 */
382 static INLINE boolean
383 util_format_is_rgba1010102_variant(const struct util_format_description *desc)
384 {
385 static const unsigned size[4] = {10, 10, 10, 2};
386 unsigned chan;
387
388 if (desc->block.width != 1 ||
389 desc->block.height != 1 ||
390 desc->block.bits != 32)
391 return FALSE;
392
393 for (chan = 0; chan < 4; ++chan) {
394 if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
395 desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
396 return FALSE;
397 if (desc->channel[chan].size != size[chan])
398 return FALSE;
399 }
400
401 return TRUE;
402 }
403
404 static boolean r300_is_format_supported(struct pipe_screen* screen,
405 enum pipe_format format,
406 enum pipe_texture_target target,
407 unsigned sample_count,
408 unsigned usage)
409 {
410 uint32_t retval = 0;
411 boolean drm_2_8_0 = r300_screen(screen)->info.drm_minor >= 8;
412 boolean is_r500 = r300_screen(screen)->caps.is_r500;
413 boolean is_r400 = r300_screen(screen)->caps.is_r400;
414 boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
415 format == PIPE_FORMAT_R10G10B10X2_SNORM ||
416 format == PIPE_FORMAT_B10G10R10A2_UNORM ||
417 format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
418 boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
419 format == PIPE_FORMAT_RGTC1_SNORM ||
420 format == PIPE_FORMAT_LATC1_UNORM ||
421 format == PIPE_FORMAT_LATC1_SNORM;
422 boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
423 format == PIPE_FORMAT_RGTC2_SNORM ||
424 format == PIPE_FORMAT_LATC2_UNORM ||
425 format == PIPE_FORMAT_LATC2_SNORM;
426 boolean is_x16f_xy16f = format == PIPE_FORMAT_R16_FLOAT ||
427 format == PIPE_FORMAT_R16G16_FLOAT ||
428 format == PIPE_FORMAT_A16_FLOAT ||
429 format == PIPE_FORMAT_L16_FLOAT ||
430 format == PIPE_FORMAT_L16A16_FLOAT ||
431 format == PIPE_FORMAT_R16A16_FLOAT ||
432 format == PIPE_FORMAT_I16_FLOAT;
433 boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
434 format == PIPE_FORMAT_R16G16_FLOAT ||
435 format == PIPE_FORMAT_R16G16B16_FLOAT ||
436 format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
437 format == PIPE_FORMAT_R16G16B16X16_FLOAT;
438 const struct util_format_description *desc;
439
440 if (!util_format_is_supported(format, usage))
441 return FALSE;
442
443 /* Check multisampling support. */
444 switch (sample_count) {
445 case 0:
446 case 1:
447 break;
448 case 2:
449 case 4:
450 case 6:
451 /* We need DRM 2.8.0. */
452 if (!drm_2_8_0) {
453 return FALSE;
454 }
455 /* No texturing and scanout. */
456 if (usage & (PIPE_BIND_SAMPLER_VIEW |
457 PIPE_BIND_DISPLAY_TARGET |
458 PIPE_BIND_SCANOUT)) {
459 return FALSE;
460 }
461
462 desc = util_format_description(format);
463
464 if (is_r500) {
465 /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
466 if (!util_format_is_depth_or_stencil(format) &&
467 !util_format_is_rgba8_variant(desc) &&
468 !util_format_is_rgba1010102_variant(desc) &&
469 format != PIPE_FORMAT_R16G16B16A16_FLOAT &&
470 format != PIPE_FORMAT_R16G16B16X16_FLOAT) {
471 return FALSE;
472 }
473 } else {
474 /* Only allow depth/stencil, RGBA8. */
475 if (!util_format_is_depth_or_stencil(format) &&
476 !util_format_is_rgba8_variant(desc)) {
477 return FALSE;
478 }
479 }
480 break;
481 default:
482 return FALSE;
483 }
484
485 /* Check sampler format support. */
486 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
487 /* these two are broken for an unknown reason */
488 format != PIPE_FORMAT_R8G8B8X8_SNORM &&
489 format != PIPE_FORMAT_R16G16B16X16_SNORM &&
490 /* ATI1N is r5xx-only. */
491 (is_r500 || !is_ati1n) &&
492 /* ATI2N is supported on r4xx-r5xx. */
493 (is_r400 || is_r500 || !is_ati2n) &&
494 /* R16F and RG16F texture support was added in as late as DRM 2.8.0 */
495 (drm_2_8_0 || !is_x16f_xy16f) &&
496 r300_is_sampler_format_supported(format)) {
497 retval |= PIPE_BIND_SAMPLER_VIEW;
498 }
499
500 /* Check colorbuffer format support. */
501 if ((usage & (PIPE_BIND_RENDER_TARGET |
502 PIPE_BIND_DISPLAY_TARGET |
503 PIPE_BIND_SCANOUT |
504 PIPE_BIND_SHARED)) &&
505 /* 2101010 cannot be rendered to on non-r5xx. */
506 (!is_color2101010 || (is_r500 && drm_2_8_0)) &&
507 r300_is_colorbuffer_format_supported(format)) {
508 retval |= usage &
509 (PIPE_BIND_RENDER_TARGET |
510 PIPE_BIND_DISPLAY_TARGET |
511 PIPE_BIND_SCANOUT |
512 PIPE_BIND_SHARED);
513 }
514
515 /* Check depth-stencil format support. */
516 if (usage & PIPE_BIND_DEPTH_STENCIL &&
517 r300_is_zs_format_supported(format)) {
518 retval |= PIPE_BIND_DEPTH_STENCIL;
519 }
520
521 /* Check vertex buffer format support. */
522 if (usage & PIPE_BIND_VERTEX_BUFFER) {
523 if (r300_screen(screen)->caps.has_tcl) {
524 /* Half float is supported on >= R400. */
525 if ((is_r400 || is_r500 || !is_half_float) &&
526 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
527 retval |= PIPE_BIND_VERTEX_BUFFER;
528 }
529 } else {
530 /* SW TCL */
531 if (!util_format_is_pure_integer(format)) {
532 retval |= PIPE_BIND_VERTEX_BUFFER;
533 }
534 }
535 }
536
537 /* Transfers are always supported. */
538 if (usage & PIPE_BIND_TRANSFER_READ)
539 retval |= PIPE_BIND_TRANSFER_READ;
540 if (usage & PIPE_BIND_TRANSFER_WRITE)
541 retval |= PIPE_BIND_TRANSFER_WRITE;
542
543 return retval == usage;
544 }
545
546 static void r300_destroy_screen(struct pipe_screen* pscreen)
547 {
548 struct r300_screen* r300screen = r300_screen(pscreen);
549 struct radeon_winsys *rws = radeon_winsys(pscreen);
550
551 if (rws && !radeon_winsys_unref(rws))
552 return;
553
554 pipe_mutex_destroy(r300screen->cmask_mutex);
555
556 if (rws)
557 rws->destroy(rws);
558
559 FREE(r300screen);
560 }
561
562 static void r300_fence_reference(struct pipe_screen *screen,
563 struct pipe_fence_handle **ptr,
564 struct pipe_fence_handle *fence)
565 {
566 struct radeon_winsys *rws = r300_screen(screen)->rws;
567
568 rws->fence_reference(ptr, fence);
569 }
570
571 static boolean r300_fence_signalled(struct pipe_screen *screen,
572 struct pipe_fence_handle *fence)
573 {
574 struct radeon_winsys *rws = r300_screen(screen)->rws;
575
576 return rws->fence_wait(rws, fence, 0);
577 }
578
579 static boolean r300_fence_finish(struct pipe_screen *screen,
580 struct pipe_fence_handle *fence,
581 uint64_t timeout)
582 {
583 struct radeon_winsys *rws = r300_screen(screen)->rws;
584
585 return rws->fence_wait(rws, fence, timeout);
586 }
587
588 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws)
589 {
590 struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
591
592 if (!r300screen) {
593 FREE(r300screen);
594 return NULL;
595 }
596
597 rws->query_info(rws, &r300screen->info);
598
599 r300_init_debug(r300screen);
600 r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
601
602 if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
603 r300screen->caps.zmask_ram = 0;
604 if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
605 r300screen->caps.hiz_ram = 0;
606
607 if (r300screen->info.drm_minor < 8)
608 r300screen->caps.has_us_format = FALSE;
609
610 r300screen->rws = rws;
611 r300screen->screen.destroy = r300_destroy_screen;
612 r300screen->screen.get_name = r300_get_name;
613 r300screen->screen.get_vendor = r300_get_vendor;
614 r300screen->screen.get_param = r300_get_param;
615 r300screen->screen.get_shader_param = r300_get_shader_param;
616 r300screen->screen.get_paramf = r300_get_paramf;
617 r300screen->screen.get_video_param = r300_get_video_param;
618 r300screen->screen.is_format_supported = r300_is_format_supported;
619 r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
620 r300screen->screen.context_create = r300_create_context;
621 r300screen->screen.fence_reference = r300_fence_reference;
622 r300screen->screen.fence_signalled = r300_fence_signalled;
623 r300screen->screen.fence_finish = r300_fence_finish;
624
625 r300_init_screen_resource_functions(r300screen);
626
627 util_format_s3tc_init();
628 pipe_mutex_init(r300screen->cmask_mutex);
629
630 return &r300screen->screen;
631 }