gallium: remove PIPE_CAP_TWO_SIDED_STENCIL
[mesa.git] / src / gallium / drivers / r300 / r300_screen.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "util/u_format.h"
25 #include "util/u_format_s3tc.h"
26 #include "util/u_memory.h"
27 #include "util/os_time.h"
28 #include "vl/vl_decoder.h"
29 #include "vl/vl_video_buffer.h"
30
31 #include "r300_context.h"
32 #include "r300_texture.h"
33 #include "r300_screen_buffer.h"
34 #include "r300_state_inlines.h"
35 #include "r300_public.h"
36
37 #include "draw/draw_context.h"
38
39 /* Return the identifier behind whom the brave coders responsible for this
40 * amalgamation of code, sweat, and duct tape, routinely obscure their names.
41 *
42 * ...I should have just put "Corbin Simpson", but I'm not that cool.
43 *
44 * (Or egotistical. Yet.) */
45 static const char* r300_get_vendor(struct pipe_screen* pscreen)
46 {
47 return "X.Org R300 Project";
48 }
49
50 static const char* r300_get_device_vendor(struct pipe_screen* pscreen)
51 {
52 return "ATI";
53 }
54
55 static const char* chip_families[] = {
56 "unknown",
57 "ATI R300",
58 "ATI R350",
59 "ATI RV350",
60 "ATI RV370",
61 "ATI RV380",
62 "ATI RS400",
63 "ATI RC410",
64 "ATI RS480",
65 "ATI R420",
66 "ATI R423",
67 "ATI R430",
68 "ATI R480",
69 "ATI R481",
70 "ATI RV410",
71 "ATI RS600",
72 "ATI RS690",
73 "ATI RS740",
74 "ATI RV515",
75 "ATI R520",
76 "ATI RV530",
77 "ATI R580",
78 "ATI RV560",
79 "ATI RV570"
80 };
81
82 static const char* r300_get_name(struct pipe_screen* pscreen)
83 {
84 struct r300_screen* r300screen = r300_screen(pscreen);
85
86 return chip_families[r300screen->caps.family];
87 }
88
89 static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
90 {
91 struct r300_screen* r300screen = r300_screen(pscreen);
92 boolean is_r500 = r300screen->caps.is_r500;
93
94 switch (param) {
95 /* Supported features (boolean caps). */
96 case PIPE_CAP_NPOT_TEXTURES:
97 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
98 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
99 case PIPE_CAP_ANISOTROPIC_FILTER:
100 case PIPE_CAP_POINT_SPRITE:
101 case PIPE_CAP_OCCLUSION_QUERY:
102 case PIPE_CAP_TEXTURE_SHADOW_MAP:
103 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
104 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
105 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
106 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
107 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
108 case PIPE_CAP_CONDITIONAL_RENDER:
109 case PIPE_CAP_TEXTURE_BARRIER:
110 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
111 case PIPE_CAP_USER_CONSTANT_BUFFERS:
112 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
113 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
114 case PIPE_CAP_CLIP_HALFZ:
115 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
116 return 1;
117
118 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
119 return R300_BUFFER_ALIGNMENT;
120
121 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
122 return 16;
123
124 case PIPE_CAP_GLSL_FEATURE_LEVEL:
125 return 120;
126
127 /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
128 case PIPE_CAP_TEXTURE_SWIZZLE:
129 return r300screen->caps.dxtc_swizzle;
130
131 /* We don't support color clamping on r500, so that we can use color
132 * intepolators for generic varyings. */
133 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
134 return !is_r500;
135
136 /* Supported on r500 only. */
137 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
138 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
139 case PIPE_CAP_SM3:
140 return is_r500 ? 1 : 0;
141
142 /* Unsupported features. */
143 case PIPE_CAP_QUERY_TIME_ELAPSED:
144 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
145 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
146 case PIPE_CAP_INDEP_BLEND_ENABLE:
147 case PIPE_CAP_INDEP_BLEND_FUNC:
148 case PIPE_CAP_DEPTH_CLIP_DISABLE:
149 case PIPE_CAP_SHADER_STENCIL_EXPORT:
150 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
151 case PIPE_CAP_TGSI_INSTANCEID:
152 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
153 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
154 case PIPE_CAP_SEAMLESS_CUBE_MAP:
155 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
156 case PIPE_CAP_MIN_TEXEL_OFFSET:
157 case PIPE_CAP_MAX_TEXEL_OFFSET:
158 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
159 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
160 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
161 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
162 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
163 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
164 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
165 case PIPE_CAP_MAX_VERTEX_STREAMS:
166 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
167 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
168 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
169 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
170 case PIPE_CAP_COMPUTE:
171 case PIPE_CAP_START_INSTANCE:
172 case PIPE_CAP_QUERY_TIMESTAMP:
173 case PIPE_CAP_TEXTURE_MULTISAMPLE:
174 case PIPE_CAP_CUBE_MAP_ARRAY:
175 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
176 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
177 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
178 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
179 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
180 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
181 case PIPE_CAP_TEXTURE_GATHER_SM5:
182 case PIPE_CAP_TEXTURE_QUERY_LOD:
183 case PIPE_CAP_FAKE_SW_MSAA:
184 case PIPE_CAP_SAMPLE_SHADING:
185 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
186 case PIPE_CAP_DRAW_INDIRECT:
187 case PIPE_CAP_MULTI_DRAW_INDIRECT:
188 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
189 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
190 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
191 case PIPE_CAP_SAMPLER_VIEW_TARGET:
192 case PIPE_CAP_VERTEXID_NOBASE:
193 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
194 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
195 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
196 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
197 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
198 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
199 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
200 case PIPE_CAP_DEPTH_BOUNDS_TEST:
201 case PIPE_CAP_TGSI_TXQS:
202 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
203 case PIPE_CAP_SHAREABLE_SHADERS:
204 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
205 case PIPE_CAP_CLEAR_TEXTURE:
206 case PIPE_CAP_DRAW_PARAMETERS:
207 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
208 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
209 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
210 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
211 case PIPE_CAP_INVALIDATE_BUFFER:
212 case PIPE_CAP_GENERATE_MIPMAP:
213 case PIPE_CAP_STRING_MARKER:
214 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
215 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
216 case PIPE_CAP_QUERY_BUFFER_OBJECT:
217 case PIPE_CAP_QUERY_MEMORY_INFO:
218 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
219 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
220 case PIPE_CAP_CULL_DISTANCE:
221 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
222 case PIPE_CAP_TGSI_VOTE:
223 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
224 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
225 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
226 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
227 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
228 case PIPE_CAP_NATIVE_FENCE_FD:
229 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
230 case PIPE_CAP_TGSI_FS_FBFETCH:
231 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
232 case PIPE_CAP_DOUBLES:
233 case PIPE_CAP_INT64:
234 case PIPE_CAP_INT64_DIVMOD:
235 case PIPE_CAP_TGSI_TEX_TXF_LZ:
236 case PIPE_CAP_TGSI_CLOCK:
237 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
238 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
239 case PIPE_CAP_TGSI_BALLOT:
240 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
241 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
242 case PIPE_CAP_POST_DEPTH_COVERAGE:
243 case PIPE_CAP_BINDLESS_TEXTURE:
244 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
245 case PIPE_CAP_QUERY_SO_OVERFLOW:
246 case PIPE_CAP_MEMOBJ:
247 case PIPE_CAP_LOAD_CONSTBUF:
248 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
249 case PIPE_CAP_TILE_RASTER_ORDER:
250 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
251 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
252 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
253 return 0;
254
255 /* SWTCL-only features. */
256 case PIPE_CAP_PRIMITIVE_RESTART:
257 case PIPE_CAP_USER_VERTEX_BUFFERS:
258 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
259 return !r300screen->caps.has_tcl;
260
261 /* HWTCL-only features / limitations. */
262 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
263 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
264 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
265 return r300screen->caps.has_tcl;
266 case PIPE_CAP_TGSI_TEXCOORD:
267 return 0;
268
269 /* Texturing. */
270 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
271 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
272 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
273 /* 13 == 4096, 12 == 2048 */
274 return is_r500 ? 13 : 12;
275
276 /* Render targets. */
277 case PIPE_CAP_MAX_RENDER_TARGETS:
278 return 4;
279 case PIPE_CAP_ENDIANNESS:
280 return PIPE_ENDIAN_LITTLE;
281
282 case PIPE_CAP_MAX_VIEWPORTS:
283 return 1;
284
285 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
286 return 2048;
287
288 case PIPE_CAP_VENDOR_ID:
289 return 0x1002;
290 case PIPE_CAP_DEVICE_ID:
291 return r300screen->info.pci_id;
292 case PIPE_CAP_ACCELERATED:
293 return 1;
294 case PIPE_CAP_VIDEO_MEMORY:
295 return r300screen->info.vram_size >> 20;
296 case PIPE_CAP_UMA:
297 return 0;
298 case PIPE_CAP_PCI_GROUP:
299 return r300screen->info.pci_domain;
300 case PIPE_CAP_PCI_BUS:
301 return r300screen->info.pci_bus;
302 case PIPE_CAP_PCI_DEVICE:
303 return r300screen->info.pci_dev;
304 case PIPE_CAP_PCI_FUNCTION:
305 return r300screen->info.pci_func;
306 }
307 return 0;
308 }
309
310 static int r300_get_shader_param(struct pipe_screen *pscreen,
311 enum pipe_shader_type shader,
312 enum pipe_shader_cap param)
313 {
314 struct r300_screen* r300screen = r300_screen(pscreen);
315 boolean is_r400 = r300screen->caps.is_r400;
316 boolean is_r500 = r300screen->caps.is_r500;
317
318 switch (shader) {
319 case PIPE_SHADER_FRAGMENT:
320 switch (param)
321 {
322 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
323 return is_r500 || is_r400 ? 512 : 96;
324 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
325 return is_r500 || is_r400 ? 512 : 64;
326 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
327 return is_r500 || is_r400 ? 512 : 32;
328 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
329 return is_r500 ? 511 : 4;
330 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
331 return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
332 /* Fragment shader limits. */
333 case PIPE_SHADER_CAP_MAX_INPUTS:
334 /* 2 colors + 8 texcoords are always supported
335 * (minus fog and wpos).
336 *
337 * R500 has the ability to turn 3rd and 4th color into
338 * additional texcoords but there is no two-sided color
339 * selection then. However the facing bit can be used instead. */
340 return 10;
341 case PIPE_SHADER_CAP_MAX_OUTPUTS:
342 return 4;
343 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
344 return (is_r500 ? 256 : 32) * sizeof(float[4]);
345 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
346 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
347 return 1;
348 case PIPE_SHADER_CAP_MAX_TEMPS:
349 return is_r500 ? 128 : is_r400 ? 64 : 32;
350 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
351 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
352 return r300screen->caps.num_tex_units;
353 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
354 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
355 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
356 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
357 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
358 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
359 case PIPE_SHADER_CAP_SUBROUTINES:
360 case PIPE_SHADER_CAP_INTEGERS:
361 case PIPE_SHADER_CAP_INT64_ATOMICS:
362 case PIPE_SHADER_CAP_FP16:
363 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
364 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
365 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
366 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
367 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
368 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
369 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
370 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
371 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
372 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
373 return 0;
374 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
375 return 32;
376 case PIPE_SHADER_CAP_PREFERRED_IR:
377 return PIPE_SHADER_IR_TGSI;
378 case PIPE_SHADER_CAP_SUPPORTED_IRS:
379 return 0;
380 }
381 break;
382 case PIPE_SHADER_VERTEX:
383 switch (param)
384 {
385 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
386 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
387 case PIPE_SHADER_CAP_SUBROUTINES:
388 return 0;
389 default:;
390 }
391
392 if (!r300screen->caps.has_tcl) {
393 return draw_get_shader_param(shader, param);
394 }
395
396 switch (param)
397 {
398 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
399 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
400 return is_r500 ? 1024 : 256;
401 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
402 return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
403 case PIPE_SHADER_CAP_MAX_INPUTS:
404 return 16;
405 case PIPE_SHADER_CAP_MAX_OUTPUTS:
406 return 10;
407 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
408 return 256 * sizeof(float[4]);
409 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
410 return 1;
411 case PIPE_SHADER_CAP_MAX_TEMPS:
412 return 32;
413 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
414 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
415 return 1;
416 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
417 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
418 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
419 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
420 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
421 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
422 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
423 case PIPE_SHADER_CAP_SUBROUTINES:
424 case PIPE_SHADER_CAP_INTEGERS:
425 case PIPE_SHADER_CAP_FP16:
426 case PIPE_SHADER_CAP_INT64_ATOMICS:
427 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
428 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
429 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
430 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
431 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
432 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
433 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
434 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
435 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
436 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
437 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
438 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
439 return 0;
440 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
441 return 32;
442 case PIPE_SHADER_CAP_PREFERRED_IR:
443 return PIPE_SHADER_IR_TGSI;
444 case PIPE_SHADER_CAP_SUPPORTED_IRS:
445 return 0;
446 }
447 break;
448 default:
449 ; /* nothing */
450 }
451 return 0;
452 }
453
454 static float r300_get_paramf(struct pipe_screen* pscreen,
455 enum pipe_capf param)
456 {
457 struct r300_screen* r300screen = r300_screen(pscreen);
458
459 switch (param) {
460 case PIPE_CAPF_MAX_LINE_WIDTH:
461 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
462 case PIPE_CAPF_MAX_POINT_WIDTH:
463 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
464 /* The maximum dimensions of the colorbuffer are our practical
465 * rendering limits. 2048 pixels should be enough for anybody. */
466 if (r300screen->caps.is_r500) {
467 return 4096.0f;
468 } else if (r300screen->caps.is_r400) {
469 return 4021.0f;
470 } else {
471 return 2560.0f;
472 }
473 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
474 return 16.0f;
475 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
476 return 16.0f;
477 case PIPE_CAPF_GUARD_BAND_LEFT:
478 case PIPE_CAPF_GUARD_BAND_TOP:
479 case PIPE_CAPF_GUARD_BAND_RIGHT:
480 case PIPE_CAPF_GUARD_BAND_BOTTOM:
481 return 0.0f;
482 default:
483 debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
484 param);
485 return 0.0f;
486 }
487 }
488
489 static int r300_get_video_param(struct pipe_screen *screen,
490 enum pipe_video_profile profile,
491 enum pipe_video_entrypoint entrypoint,
492 enum pipe_video_cap param)
493 {
494 switch (param) {
495 case PIPE_VIDEO_CAP_SUPPORTED:
496 return vl_profile_supported(screen, profile, entrypoint);
497 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
498 return 0;
499 case PIPE_VIDEO_CAP_MAX_WIDTH:
500 case PIPE_VIDEO_CAP_MAX_HEIGHT:
501 return vl_video_buffer_max_size(screen);
502 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
503 return PIPE_FORMAT_NV12;
504 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
505 return false;
506 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
507 return false;
508 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
509 return true;
510 case PIPE_VIDEO_CAP_MAX_LEVEL:
511 return vl_level_supported(screen, profile);
512 default:
513 return 0;
514 }
515 }
516
517 /**
518 * Whether the format matches:
519 * PIPE_FORMAT_?10?10?10?2_UNORM
520 */
521 static inline boolean
522 util_format_is_rgba1010102_variant(const struct util_format_description *desc)
523 {
524 static const unsigned size[4] = {10, 10, 10, 2};
525 unsigned chan;
526
527 if (desc->block.width != 1 ||
528 desc->block.height != 1 ||
529 desc->block.bits != 32)
530 return FALSE;
531
532 for (chan = 0; chan < 4; ++chan) {
533 if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
534 desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
535 return FALSE;
536 if (desc->channel[chan].size != size[chan])
537 return FALSE;
538 }
539
540 return TRUE;
541 }
542
543 static bool r300_is_blending_supported(struct r300_screen *rscreen,
544 enum pipe_format format)
545 {
546 int c;
547 const struct util_format_description *desc =
548 util_format_description(format);
549
550 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
551 return false;
552
553 c = util_format_get_first_non_void_channel(format);
554
555 /* RGBA16F */
556 if (rscreen->caps.is_r500 &&
557 desc->nr_channels == 4 &&
558 desc->channel[c].size == 16 &&
559 desc->channel[c].type == UTIL_FORMAT_TYPE_FLOAT)
560 return true;
561
562 if (desc->channel[c].normalized &&
563 desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED &&
564 desc->channel[c].size >= 4 &&
565 desc->channel[c].size <= 10) {
566 /* RGB10_A2, RGBA8, RGB5_A1, RGBA4, RGB565 */
567 if (desc->nr_channels >= 3)
568 return true;
569
570 if (format == PIPE_FORMAT_R8G8_UNORM)
571 return true;
572
573 /* R8, I8, L8, A8 */
574 if (desc->nr_channels == 1)
575 return true;
576 }
577
578 return false;
579 }
580
581 static boolean r300_is_format_supported(struct pipe_screen* screen,
582 enum pipe_format format,
583 enum pipe_texture_target target,
584 unsigned sample_count,
585 unsigned usage)
586 {
587 uint32_t retval = 0;
588 boolean is_r500 = r300_screen(screen)->caps.is_r500;
589 boolean is_r400 = r300_screen(screen)->caps.is_r400;
590 boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
591 format == PIPE_FORMAT_R10G10B10X2_SNORM ||
592 format == PIPE_FORMAT_B10G10R10A2_UNORM ||
593 format == PIPE_FORMAT_B10G10R10X2_UNORM ||
594 format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
595 boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
596 format == PIPE_FORMAT_RGTC1_SNORM ||
597 format == PIPE_FORMAT_LATC1_UNORM ||
598 format == PIPE_FORMAT_LATC1_SNORM;
599 boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
600 format == PIPE_FORMAT_RGTC2_SNORM ||
601 format == PIPE_FORMAT_LATC2_UNORM ||
602 format == PIPE_FORMAT_LATC2_SNORM;
603 boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
604 format == PIPE_FORMAT_R16G16_FLOAT ||
605 format == PIPE_FORMAT_R16G16B16_FLOAT ||
606 format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
607 format == PIPE_FORMAT_R16G16B16X16_FLOAT;
608 const struct util_format_description *desc;
609
610 if (!util_format_is_supported(format, usage))
611 return FALSE;
612
613 /* Check multisampling support. */
614 switch (sample_count) {
615 case 0:
616 case 1:
617 break;
618 case 2:
619 case 4:
620 case 6:
621 /* No texturing and scanout. */
622 if (usage & (PIPE_BIND_SAMPLER_VIEW |
623 PIPE_BIND_DISPLAY_TARGET |
624 PIPE_BIND_SCANOUT)) {
625 return FALSE;
626 }
627
628 desc = util_format_description(format);
629
630 if (is_r500) {
631 /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
632 if (!util_format_is_depth_or_stencil(format) &&
633 !util_format_is_rgba8_variant(desc) &&
634 !util_format_is_rgba1010102_variant(desc) &&
635 format != PIPE_FORMAT_R16G16B16A16_FLOAT &&
636 format != PIPE_FORMAT_R16G16B16X16_FLOAT) {
637 return FALSE;
638 }
639 } else {
640 /* Only allow depth/stencil, RGBA8. */
641 if (!util_format_is_depth_or_stencil(format) &&
642 !util_format_is_rgba8_variant(desc)) {
643 return FALSE;
644 }
645 }
646 break;
647 default:
648 return FALSE;
649 }
650
651 /* Check sampler format support. */
652 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
653 /* these two are broken for an unknown reason */
654 format != PIPE_FORMAT_R8G8B8X8_SNORM &&
655 format != PIPE_FORMAT_R16G16B16X16_SNORM &&
656 /* ATI1N is r5xx-only. */
657 (is_r500 || !is_ati1n) &&
658 /* ATI2N is supported on r4xx-r5xx. */
659 (is_r400 || is_r500 || !is_ati2n) &&
660 r300_is_sampler_format_supported(format)) {
661 retval |= PIPE_BIND_SAMPLER_VIEW;
662 }
663
664 /* Check colorbuffer format support. */
665 if ((usage & (PIPE_BIND_RENDER_TARGET |
666 PIPE_BIND_DISPLAY_TARGET |
667 PIPE_BIND_SCANOUT |
668 PIPE_BIND_SHARED |
669 PIPE_BIND_BLENDABLE)) &&
670 /* 2101010 cannot be rendered to on non-r5xx. */
671 (!is_color2101010 || is_r500) &&
672 r300_is_colorbuffer_format_supported(format)) {
673 retval |= usage &
674 (PIPE_BIND_RENDER_TARGET |
675 PIPE_BIND_DISPLAY_TARGET |
676 PIPE_BIND_SCANOUT |
677 PIPE_BIND_SHARED);
678
679 if (r300_is_blending_supported(r300_screen(screen), format)) {
680 retval |= usage & PIPE_BIND_BLENDABLE;
681 }
682 }
683
684 /* Check depth-stencil format support. */
685 if (usage & PIPE_BIND_DEPTH_STENCIL &&
686 r300_is_zs_format_supported(format)) {
687 retval |= PIPE_BIND_DEPTH_STENCIL;
688 }
689
690 /* Check vertex buffer format support. */
691 if (usage & PIPE_BIND_VERTEX_BUFFER) {
692 if (r300_screen(screen)->caps.has_tcl) {
693 /* Half float is supported on >= R400. */
694 if ((is_r400 || is_r500 || !is_half_float) &&
695 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
696 retval |= PIPE_BIND_VERTEX_BUFFER;
697 }
698 } else {
699 /* SW TCL */
700 if (!util_format_is_pure_integer(format)) {
701 retval |= PIPE_BIND_VERTEX_BUFFER;
702 }
703 }
704 }
705
706 return retval == usage;
707 }
708
709 static void r300_destroy_screen(struct pipe_screen* pscreen)
710 {
711 struct r300_screen* r300screen = r300_screen(pscreen);
712 struct radeon_winsys *rws = radeon_winsys(pscreen);
713
714 if (rws && !rws->unref(rws))
715 return;
716
717 mtx_destroy(&r300screen->cmask_mutex);
718 slab_destroy_parent(&r300screen->pool_transfers);
719
720 if (rws)
721 rws->destroy(rws);
722
723 FREE(r300screen);
724 }
725
726 static void r300_fence_reference(struct pipe_screen *screen,
727 struct pipe_fence_handle **ptr,
728 struct pipe_fence_handle *fence)
729 {
730 struct radeon_winsys *rws = r300_screen(screen)->rws;
731
732 rws->fence_reference(ptr, fence);
733 }
734
735 static boolean r300_fence_finish(struct pipe_screen *screen,
736 struct pipe_context *ctx,
737 struct pipe_fence_handle *fence,
738 uint64_t timeout)
739 {
740 struct radeon_winsys *rws = r300_screen(screen)->rws;
741
742 return rws->fence_wait(rws, fence, timeout);
743 }
744
745 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws,
746 const struct pipe_screen_config *config)
747 {
748 struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
749
750 if (!r300screen) {
751 FREE(r300screen);
752 return NULL;
753 }
754
755 rws->query_info(rws, &r300screen->info);
756
757 r300_init_debug(r300screen);
758 r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
759
760 if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
761 r300screen->caps.zmask_ram = 0;
762 if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
763 r300screen->caps.hiz_ram = 0;
764
765 r300screen->rws = rws;
766 r300screen->screen.destroy = r300_destroy_screen;
767 r300screen->screen.get_name = r300_get_name;
768 r300screen->screen.get_vendor = r300_get_vendor;
769 r300screen->screen.get_device_vendor = r300_get_device_vendor;
770 r300screen->screen.get_param = r300_get_param;
771 r300screen->screen.get_shader_param = r300_get_shader_param;
772 r300screen->screen.get_paramf = r300_get_paramf;
773 r300screen->screen.get_video_param = r300_get_video_param;
774 r300screen->screen.is_format_supported = r300_is_format_supported;
775 r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
776 r300screen->screen.context_create = r300_create_context;
777 r300screen->screen.fence_reference = r300_fence_reference;
778 r300screen->screen.fence_finish = r300_fence_finish;
779
780 r300_init_screen_resource_functions(r300screen);
781
782 slab_create_parent(&r300screen->pool_transfers, sizeof(struct pipe_transfer), 64);
783
784 (void) mtx_init(&r300screen->cmask_mutex, mtx_plain);
785
786 return &r300screen->screen;
787 }