gallium: Add a cap to check if the driver supports ARB_post_depth_coverage
[mesa.git] / src / gallium / drivers / r300 / r300_screen.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "util/u_format.h"
25 #include "util/u_format_s3tc.h"
26 #include "util/u_memory.h"
27 #include "os/os_time.h"
28 #include "vl/vl_decoder.h"
29 #include "vl/vl_video_buffer.h"
30
31 #include "r300_context.h"
32 #include "r300_texture.h"
33 #include "r300_screen_buffer.h"
34 #include "r300_state_inlines.h"
35 #include "r300_public.h"
36
37 #include "draw/draw_context.h"
38
39 /* Return the identifier behind whom the brave coders responsible for this
40 * amalgamation of code, sweat, and duct tape, routinely obscure their names.
41 *
42 * ...I should have just put "Corbin Simpson", but I'm not that cool.
43 *
44 * (Or egotistical. Yet.) */
45 static const char* r300_get_vendor(struct pipe_screen* pscreen)
46 {
47 return "X.Org R300 Project";
48 }
49
50 static const char* r300_get_device_vendor(struct pipe_screen* pscreen)
51 {
52 return "ATI";
53 }
54
55 static const char* chip_families[] = {
56 "unknown",
57 "ATI R300",
58 "ATI R350",
59 "ATI RV350",
60 "ATI RV370",
61 "ATI RV380",
62 "ATI RS400",
63 "ATI RC410",
64 "ATI RS480",
65 "ATI R420",
66 "ATI R423",
67 "ATI R430",
68 "ATI R480",
69 "ATI R481",
70 "ATI RV410",
71 "ATI RS600",
72 "ATI RS690",
73 "ATI RS740",
74 "ATI RV515",
75 "ATI R520",
76 "ATI RV530",
77 "ATI R580",
78 "ATI RV560",
79 "ATI RV570"
80 };
81
82 static const char* r300_get_name(struct pipe_screen* pscreen)
83 {
84 struct r300_screen* r300screen = r300_screen(pscreen);
85
86 return chip_families[r300screen->caps.family];
87 }
88
89 static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
90 {
91 struct r300_screen* r300screen = r300_screen(pscreen);
92 boolean is_r500 = r300screen->caps.is_r500;
93
94 switch (param) {
95 /* Supported features (boolean caps). */
96 case PIPE_CAP_NPOT_TEXTURES:
97 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
98 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
99 case PIPE_CAP_TWO_SIDED_STENCIL:
100 case PIPE_CAP_ANISOTROPIC_FILTER:
101 case PIPE_CAP_POINT_SPRITE:
102 case PIPE_CAP_OCCLUSION_QUERY:
103 case PIPE_CAP_TEXTURE_SHADOW_MAP:
104 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
105 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
106 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
107 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
108 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
109 case PIPE_CAP_CONDITIONAL_RENDER:
110 case PIPE_CAP_TEXTURE_BARRIER:
111 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
112 case PIPE_CAP_USER_CONSTANT_BUFFERS:
113 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
114 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
115 case PIPE_CAP_CLIP_HALFZ:
116 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
117 return 1;
118
119 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
120 return R300_BUFFER_ALIGNMENT;
121
122 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
123 return 16;
124
125 case PIPE_CAP_GLSL_FEATURE_LEVEL:
126 return 120;
127
128 /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
129 case PIPE_CAP_TEXTURE_SWIZZLE:
130 return util_format_s3tc_enabled ? r300screen->caps.dxtc_swizzle : 1;
131
132 /* We don't support color clamping on r500, so that we can use color
133 * intepolators for generic varyings. */
134 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
135 return !is_r500;
136
137 /* Supported on r500 only. */
138 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
139 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
140 case PIPE_CAP_SM3:
141 return is_r500 ? 1 : 0;
142
143 /* Unsupported features. */
144 case PIPE_CAP_QUERY_TIME_ELAPSED:
145 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
146 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
147 case PIPE_CAP_INDEP_BLEND_ENABLE:
148 case PIPE_CAP_INDEP_BLEND_FUNC:
149 case PIPE_CAP_DEPTH_CLIP_DISABLE:
150 case PIPE_CAP_SHADER_STENCIL_EXPORT:
151 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
152 case PIPE_CAP_TGSI_INSTANCEID:
153 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
154 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
155 case PIPE_CAP_SEAMLESS_CUBE_MAP:
156 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
157 case PIPE_CAP_MIN_TEXEL_OFFSET:
158 case PIPE_CAP_MAX_TEXEL_OFFSET:
159 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
160 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
161 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
162 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
163 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
164 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
165 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
166 case PIPE_CAP_MAX_VERTEX_STREAMS:
167 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
168 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
169 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
170 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
171 case PIPE_CAP_COMPUTE:
172 case PIPE_CAP_START_INSTANCE:
173 case PIPE_CAP_QUERY_TIMESTAMP:
174 case PIPE_CAP_TEXTURE_MULTISAMPLE:
175 case PIPE_CAP_CUBE_MAP_ARRAY:
176 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
177 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
178 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
179 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
180 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
181 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
182 case PIPE_CAP_TEXTURE_GATHER_SM5:
183 case PIPE_CAP_TEXTURE_QUERY_LOD:
184 case PIPE_CAP_FAKE_SW_MSAA:
185 case PIPE_CAP_SAMPLE_SHADING:
186 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
187 case PIPE_CAP_DRAW_INDIRECT:
188 case PIPE_CAP_MULTI_DRAW_INDIRECT:
189 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
190 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
191 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
192 case PIPE_CAP_SAMPLER_VIEW_TARGET:
193 case PIPE_CAP_VERTEXID_NOBASE:
194 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
195 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
196 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
197 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
198 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
199 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
200 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
201 case PIPE_CAP_DEPTH_BOUNDS_TEST:
202 case PIPE_CAP_TGSI_TXQS:
203 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
204 case PIPE_CAP_SHAREABLE_SHADERS:
205 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
206 case PIPE_CAP_CLEAR_TEXTURE:
207 case PIPE_CAP_DRAW_PARAMETERS:
208 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
209 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
210 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
211 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
212 case PIPE_CAP_INVALIDATE_BUFFER:
213 case PIPE_CAP_GENERATE_MIPMAP:
214 case PIPE_CAP_STRING_MARKER:
215 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
216 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
217 case PIPE_CAP_QUERY_BUFFER_OBJECT:
218 case PIPE_CAP_QUERY_MEMORY_INFO:
219 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
220 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
221 case PIPE_CAP_CULL_DISTANCE:
222 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
223 case PIPE_CAP_TGSI_VOTE:
224 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
225 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
226 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
227 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
228 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
229 case PIPE_CAP_NATIVE_FENCE_FD:
230 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
231 case PIPE_CAP_TGSI_FS_FBFETCH:
232 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
233 case PIPE_CAP_DOUBLES:
234 case PIPE_CAP_INT64:
235 case PIPE_CAP_INT64_DIVMOD:
236 case PIPE_CAP_TGSI_TEX_TXF_LZ:
237 case PIPE_CAP_TGSI_CLOCK:
238 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
239 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
240 case PIPE_CAP_TGSI_BALLOT:
241 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
242 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
243 case PIPE_CAP_POST_DEPTH_COVERAGE:
244 return 0;
245
246 /* SWTCL-only features. */
247 case PIPE_CAP_PRIMITIVE_RESTART:
248 case PIPE_CAP_USER_VERTEX_BUFFERS:
249 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
250 return !r300screen->caps.has_tcl;
251
252 /* HWTCL-only features / limitations. */
253 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
254 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
255 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
256 return r300screen->caps.has_tcl;
257 case PIPE_CAP_TGSI_TEXCOORD:
258 return 0;
259
260 /* Texturing. */
261 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
262 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
263 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
264 /* 13 == 4096, 12 == 2048 */
265 return is_r500 ? 13 : 12;
266
267 /* Render targets. */
268 case PIPE_CAP_MAX_RENDER_TARGETS:
269 return 4;
270 case PIPE_CAP_ENDIANNESS:
271 return PIPE_ENDIAN_LITTLE;
272
273 case PIPE_CAP_MAX_VIEWPORTS:
274 return 1;
275
276 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
277 return 2048;
278
279 case PIPE_CAP_VENDOR_ID:
280 return 0x1002;
281 case PIPE_CAP_DEVICE_ID:
282 return r300screen->info.pci_id;
283 case PIPE_CAP_ACCELERATED:
284 return 1;
285 case PIPE_CAP_VIDEO_MEMORY:
286 return r300screen->info.vram_size >> 20;
287 case PIPE_CAP_UMA:
288 return 0;
289 case PIPE_CAP_PCI_GROUP:
290 return r300screen->info.pci_domain;
291 case PIPE_CAP_PCI_BUS:
292 return r300screen->info.pci_bus;
293 case PIPE_CAP_PCI_DEVICE:
294 return r300screen->info.pci_dev;
295 case PIPE_CAP_PCI_FUNCTION:
296 return r300screen->info.pci_func;
297 }
298 return 0;
299 }
300
301 static int r300_get_shader_param(struct pipe_screen *pscreen,
302 enum pipe_shader_type shader,
303 enum pipe_shader_cap param)
304 {
305 struct r300_screen* r300screen = r300_screen(pscreen);
306 boolean is_r400 = r300screen->caps.is_r400;
307 boolean is_r500 = r300screen->caps.is_r500;
308
309 switch (shader) {
310 case PIPE_SHADER_FRAGMENT:
311 switch (param)
312 {
313 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
314 return is_r500 || is_r400 ? 512 : 96;
315 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
316 return is_r500 || is_r400 ? 512 : 64;
317 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
318 return is_r500 || is_r400 ? 512 : 32;
319 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
320 return is_r500 ? 511 : 4;
321 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
322 return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
323 /* Fragment shader limits. */
324 case PIPE_SHADER_CAP_MAX_INPUTS:
325 /* 2 colors + 8 texcoords are always supported
326 * (minus fog and wpos).
327 *
328 * R500 has the ability to turn 3rd and 4th color into
329 * additional texcoords but there is no two-sided color
330 * selection then. However the facing bit can be used instead. */
331 return 10;
332 case PIPE_SHADER_CAP_MAX_OUTPUTS:
333 return 4;
334 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
335 return (is_r500 ? 256 : 32) * sizeof(float[4]);
336 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
337 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
338 return 1;
339 case PIPE_SHADER_CAP_MAX_TEMPS:
340 return is_r500 ? 128 : is_r400 ? 64 : 32;
341 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
342 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
343 return r300screen->caps.num_tex_units;
344 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
345 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
346 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
347 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
348 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
349 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
350 case PIPE_SHADER_CAP_SUBROUTINES:
351 case PIPE_SHADER_CAP_INTEGERS:
352 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
353 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
354 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
355 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
356 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
357 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
358 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
359 return 0;
360 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
361 return 32;
362 case PIPE_SHADER_CAP_PREFERRED_IR:
363 return PIPE_SHADER_IR_TGSI;
364 case PIPE_SHADER_CAP_SUPPORTED_IRS:
365 return 0;
366 }
367 break;
368 case PIPE_SHADER_VERTEX:
369 switch (param)
370 {
371 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
372 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
373 case PIPE_SHADER_CAP_SUBROUTINES:
374 return 0;
375 default:;
376 }
377
378 if (!r300screen->caps.has_tcl) {
379 return draw_get_shader_param(shader, param);
380 }
381
382 switch (param)
383 {
384 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
385 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
386 return is_r500 ? 1024 : 256;
387 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
388 return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
389 case PIPE_SHADER_CAP_MAX_INPUTS:
390 return 16;
391 case PIPE_SHADER_CAP_MAX_OUTPUTS:
392 return 10;
393 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
394 return 256 * sizeof(float[4]);
395 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
396 return 1;
397 case PIPE_SHADER_CAP_MAX_TEMPS:
398 return 32;
399 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
400 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
401 return 1;
402 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
403 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
404 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
405 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
406 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
407 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
408 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
409 case PIPE_SHADER_CAP_SUBROUTINES:
410 case PIPE_SHADER_CAP_INTEGERS:
411 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
412 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
413 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
414 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
415 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
416 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
417 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
418 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
419 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
420 return 0;
421 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
422 return 32;
423 case PIPE_SHADER_CAP_PREFERRED_IR:
424 return PIPE_SHADER_IR_TGSI;
425 case PIPE_SHADER_CAP_SUPPORTED_IRS:
426 return 0;
427 }
428 break;
429 default:
430 ; /* nothing */
431 }
432 return 0;
433 }
434
435 static float r300_get_paramf(struct pipe_screen* pscreen,
436 enum pipe_capf param)
437 {
438 struct r300_screen* r300screen = r300_screen(pscreen);
439
440 switch (param) {
441 case PIPE_CAPF_MAX_LINE_WIDTH:
442 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
443 case PIPE_CAPF_MAX_POINT_WIDTH:
444 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
445 /* The maximum dimensions of the colorbuffer are our practical
446 * rendering limits. 2048 pixels should be enough for anybody. */
447 if (r300screen->caps.is_r500) {
448 return 4096.0f;
449 } else if (r300screen->caps.is_r400) {
450 return 4021.0f;
451 } else {
452 return 2560.0f;
453 }
454 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
455 return 16.0f;
456 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
457 return 16.0f;
458 case PIPE_CAPF_GUARD_BAND_LEFT:
459 case PIPE_CAPF_GUARD_BAND_TOP:
460 case PIPE_CAPF_GUARD_BAND_RIGHT:
461 case PIPE_CAPF_GUARD_BAND_BOTTOM:
462 return 0.0f;
463 default:
464 debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
465 param);
466 return 0.0f;
467 }
468 }
469
470 static int r300_get_video_param(struct pipe_screen *screen,
471 enum pipe_video_profile profile,
472 enum pipe_video_entrypoint entrypoint,
473 enum pipe_video_cap param)
474 {
475 switch (param) {
476 case PIPE_VIDEO_CAP_SUPPORTED:
477 return vl_profile_supported(screen, profile, entrypoint);
478 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
479 return 0;
480 case PIPE_VIDEO_CAP_MAX_WIDTH:
481 case PIPE_VIDEO_CAP_MAX_HEIGHT:
482 return vl_video_buffer_max_size(screen);
483 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
484 return PIPE_FORMAT_NV12;
485 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
486 return false;
487 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
488 return false;
489 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
490 return true;
491 case PIPE_VIDEO_CAP_MAX_LEVEL:
492 return vl_level_supported(screen, profile);
493 default:
494 return 0;
495 }
496 }
497
498 /**
499 * Whether the format matches:
500 * PIPE_FORMAT_?10?10?10?2_UNORM
501 */
502 static inline boolean
503 util_format_is_rgba1010102_variant(const struct util_format_description *desc)
504 {
505 static const unsigned size[4] = {10, 10, 10, 2};
506 unsigned chan;
507
508 if (desc->block.width != 1 ||
509 desc->block.height != 1 ||
510 desc->block.bits != 32)
511 return FALSE;
512
513 for (chan = 0; chan < 4; ++chan) {
514 if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
515 desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
516 return FALSE;
517 if (desc->channel[chan].size != size[chan])
518 return FALSE;
519 }
520
521 return TRUE;
522 }
523
524 static bool r300_is_blending_supported(struct r300_screen *rscreen,
525 enum pipe_format format)
526 {
527 int c;
528 const struct util_format_description *desc =
529 util_format_description(format);
530
531 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
532 return false;
533
534 c = util_format_get_first_non_void_channel(format);
535
536 /* RGBA16F */
537 if (rscreen->caps.is_r500 &&
538 desc->nr_channels == 4 &&
539 desc->channel[c].size == 16 &&
540 desc->channel[c].type == UTIL_FORMAT_TYPE_FLOAT)
541 return true;
542
543 if (desc->channel[c].normalized &&
544 desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED &&
545 desc->channel[c].size >= 4 &&
546 desc->channel[c].size <= 10) {
547 /* RGB10_A2, RGBA8, RGB5_A1, RGBA4, RGB565 */
548 if (desc->nr_channels >= 3)
549 return true;
550
551 if (format == PIPE_FORMAT_R8G8_UNORM)
552 return true;
553
554 /* R8, I8, L8, A8 */
555 if (desc->nr_channels == 1)
556 return true;
557 }
558
559 return false;
560 }
561
562 static boolean r300_is_format_supported(struct pipe_screen* screen,
563 enum pipe_format format,
564 enum pipe_texture_target target,
565 unsigned sample_count,
566 unsigned usage)
567 {
568 uint32_t retval = 0;
569 boolean is_r500 = r300_screen(screen)->caps.is_r500;
570 boolean is_r400 = r300_screen(screen)->caps.is_r400;
571 boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
572 format == PIPE_FORMAT_R10G10B10X2_SNORM ||
573 format == PIPE_FORMAT_B10G10R10A2_UNORM ||
574 format == PIPE_FORMAT_B10G10R10X2_UNORM ||
575 format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
576 boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
577 format == PIPE_FORMAT_RGTC1_SNORM ||
578 format == PIPE_FORMAT_LATC1_UNORM ||
579 format == PIPE_FORMAT_LATC1_SNORM;
580 boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
581 format == PIPE_FORMAT_RGTC2_SNORM ||
582 format == PIPE_FORMAT_LATC2_UNORM ||
583 format == PIPE_FORMAT_LATC2_SNORM;
584 boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
585 format == PIPE_FORMAT_R16G16_FLOAT ||
586 format == PIPE_FORMAT_R16G16B16_FLOAT ||
587 format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
588 format == PIPE_FORMAT_R16G16B16X16_FLOAT;
589 const struct util_format_description *desc;
590
591 if (!util_format_is_supported(format, usage))
592 return FALSE;
593
594 /* Check multisampling support. */
595 switch (sample_count) {
596 case 0:
597 case 1:
598 break;
599 case 2:
600 case 4:
601 case 6:
602 /* No texturing and scanout. */
603 if (usage & (PIPE_BIND_SAMPLER_VIEW |
604 PIPE_BIND_DISPLAY_TARGET |
605 PIPE_BIND_SCANOUT)) {
606 return FALSE;
607 }
608
609 desc = util_format_description(format);
610
611 if (is_r500) {
612 /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
613 if (!util_format_is_depth_or_stencil(format) &&
614 !util_format_is_rgba8_variant(desc) &&
615 !util_format_is_rgba1010102_variant(desc) &&
616 format != PIPE_FORMAT_R16G16B16A16_FLOAT &&
617 format != PIPE_FORMAT_R16G16B16X16_FLOAT) {
618 return FALSE;
619 }
620 } else {
621 /* Only allow depth/stencil, RGBA8. */
622 if (!util_format_is_depth_or_stencil(format) &&
623 !util_format_is_rgba8_variant(desc)) {
624 return FALSE;
625 }
626 }
627 break;
628 default:
629 return FALSE;
630 }
631
632 /* Check sampler format support. */
633 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
634 /* these two are broken for an unknown reason */
635 format != PIPE_FORMAT_R8G8B8X8_SNORM &&
636 format != PIPE_FORMAT_R16G16B16X16_SNORM &&
637 /* ATI1N is r5xx-only. */
638 (is_r500 || !is_ati1n) &&
639 /* ATI2N is supported on r4xx-r5xx. */
640 (is_r400 || is_r500 || !is_ati2n) &&
641 r300_is_sampler_format_supported(format)) {
642 retval |= PIPE_BIND_SAMPLER_VIEW;
643 }
644
645 /* Check colorbuffer format support. */
646 if ((usage & (PIPE_BIND_RENDER_TARGET |
647 PIPE_BIND_DISPLAY_TARGET |
648 PIPE_BIND_SCANOUT |
649 PIPE_BIND_SHARED |
650 PIPE_BIND_BLENDABLE)) &&
651 /* 2101010 cannot be rendered to on non-r5xx. */
652 (!is_color2101010 || is_r500) &&
653 r300_is_colorbuffer_format_supported(format)) {
654 retval |= usage &
655 (PIPE_BIND_RENDER_TARGET |
656 PIPE_BIND_DISPLAY_TARGET |
657 PIPE_BIND_SCANOUT |
658 PIPE_BIND_SHARED);
659
660 if (r300_is_blending_supported(r300_screen(screen), format)) {
661 retval |= usage & PIPE_BIND_BLENDABLE;
662 }
663 }
664
665 /* Check depth-stencil format support. */
666 if (usage & PIPE_BIND_DEPTH_STENCIL &&
667 r300_is_zs_format_supported(format)) {
668 retval |= PIPE_BIND_DEPTH_STENCIL;
669 }
670
671 /* Check vertex buffer format support. */
672 if (usage & PIPE_BIND_VERTEX_BUFFER) {
673 if (r300_screen(screen)->caps.has_tcl) {
674 /* Half float is supported on >= R400. */
675 if ((is_r400 || is_r500 || !is_half_float) &&
676 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
677 retval |= PIPE_BIND_VERTEX_BUFFER;
678 }
679 } else {
680 /* SW TCL */
681 if (!util_format_is_pure_integer(format)) {
682 retval |= PIPE_BIND_VERTEX_BUFFER;
683 }
684 }
685 }
686
687 return retval == usage;
688 }
689
690 static void r300_destroy_screen(struct pipe_screen* pscreen)
691 {
692 struct r300_screen* r300screen = r300_screen(pscreen);
693 struct radeon_winsys *rws = radeon_winsys(pscreen);
694
695 if (rws && !rws->unref(rws))
696 return;
697
698 mtx_destroy(&r300screen->cmask_mutex);
699 slab_destroy_parent(&r300screen->pool_transfers);
700
701 if (rws)
702 rws->destroy(rws);
703
704 FREE(r300screen);
705 }
706
707 static void r300_fence_reference(struct pipe_screen *screen,
708 struct pipe_fence_handle **ptr,
709 struct pipe_fence_handle *fence)
710 {
711 struct radeon_winsys *rws = r300_screen(screen)->rws;
712
713 rws->fence_reference(ptr, fence);
714 }
715
716 static boolean r300_fence_finish(struct pipe_screen *screen,
717 struct pipe_context *ctx,
718 struct pipe_fence_handle *fence,
719 uint64_t timeout)
720 {
721 struct radeon_winsys *rws = r300_screen(screen)->rws;
722
723 return rws->fence_wait(rws, fence, timeout);
724 }
725
726 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws)
727 {
728 struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
729
730 if (!r300screen) {
731 FREE(r300screen);
732 return NULL;
733 }
734
735 rws->query_info(rws, &r300screen->info);
736
737 r300_init_debug(r300screen);
738 r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
739
740 if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
741 r300screen->caps.zmask_ram = 0;
742 if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
743 r300screen->caps.hiz_ram = 0;
744
745 r300screen->rws = rws;
746 r300screen->screen.destroy = r300_destroy_screen;
747 r300screen->screen.get_name = r300_get_name;
748 r300screen->screen.get_vendor = r300_get_vendor;
749 r300screen->screen.get_device_vendor = r300_get_device_vendor;
750 r300screen->screen.get_param = r300_get_param;
751 r300screen->screen.get_shader_param = r300_get_shader_param;
752 r300screen->screen.get_paramf = r300_get_paramf;
753 r300screen->screen.get_video_param = r300_get_video_param;
754 r300screen->screen.is_format_supported = r300_is_format_supported;
755 r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
756 r300screen->screen.context_create = r300_create_context;
757 r300screen->screen.fence_reference = r300_fence_reference;
758 r300screen->screen.fence_finish = r300_fence_finish;
759
760 r300_init_screen_resource_functions(r300screen);
761
762 slab_create_parent(&r300screen->pool_transfers, sizeof(struct pipe_transfer), 64);
763
764 util_format_s3tc_init();
765 (void) mtx_init(&r300screen->cmask_mutex, mtx_plain);
766
767 return &r300screen->screen;
768 }