src/gallium/drivers/r300/r300_screen.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #include "util/u_format.h"
  25 #include "util/u_format_s3tc.h"
  26 #include "util/u_memory.h"
  27 #include "os/os_time.h"
  28 #include "vl/vl_decoder.h"
  29 #include "vl/vl_video_buffer.h"
  30
  31 #include "r300_context.h"
  32 #include "r300_texture.h"
  33 #include "r300_screen_buffer.h"
  34 #include "r300_state_inlines.h"
  35 #include "r300_public.h"
  36
  37 #include "draw/draw_context.h"
  38
  39 /* Return the identifier behind whom the brave coders responsible for this
  40  * amalgamation of code, sweat, and duct tape, routinely obscure their names.
  41  *
  42  * ...I should have just put "Corbin Simpson", but I'm not that cool.
  43  *
  44  * (Or egotistical. Yet.) */
  45 static const char* r300_get_vendor(struct pipe_screen* pscreen)
  46 {
  47     return "X.Org R300 Project";
  48 }
  49
  50 static const char* chip_families[] = {
  51     "unknown",
  52     "ATI R300",
  53     "ATI R350",
  54     "ATI RV350",
  55     "ATI RV370",
  56     "ATI RV380",
  57     "ATI RS400",
  58     "ATI RC410",
  59     "ATI RS480",
  60     "ATI R420",
  61     "ATI R423",
  62     "ATI R430",
  63     "ATI R480",
  64     "ATI R481",
  65     "ATI RV410",
  66     "ATI RS600",
  67     "ATI RS690",
  68     "ATI RS740",
  69     "ATI RV515",
  70     "ATI R520",
  71     "ATI RV530",
  72     "ATI R580",
  73     "ATI RV560",
  74     "ATI RV570"
  75 };
  76
  77 static const char* r300_get_name(struct pipe_screen* pscreen)
  78 {
  79     struct r300_screen* r300screen = r300_screen(pscreen);
  80
  81     return chip_families[r300screen->caps.family];
  82 }
  83
  84 static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
  85 {
  86     struct r300_screen* r300screen = r300_screen(pscreen);
  87     boolean is_r500 = r300screen->caps.is_r500;
  88
  89     switch (param) {
  90         /* Supported features (boolean caps). */
  91         case PIPE_CAP_NPOT_TEXTURES:
  92         case PIPE_CAP_TWO_SIDED_STENCIL:
  93         case PIPE_CAP_ANISOTROPIC_FILTER:
  94         case PIPE_CAP_POINT_SPRITE:
  95         case PIPE_CAP_OCCLUSION_QUERY:
  96         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  97         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  98         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  99         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 100         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 101         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 102         case PIPE_CAP_CONDITIONAL_RENDER:
 103         case PIPE_CAP_TEXTURE_BARRIER:
 104         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 105         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 106         case PIPE_CAP_USER_INDEX_BUFFERS:
 107         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 108         case PIPE_CAP_DEPTH_CLIP_DISABLE: /* XXX implemented, but breaks Regnum Online */
 109             return 1;
 110
 111         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 112             return R300_BUFFER_ALIGNMENT;
 113
 114         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 115             return 16;
 116
 117         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 118             return 120;
 119
 120         /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
 121         case PIPE_CAP_TEXTURE_SWIZZLE:
 122             return util_format_s3tc_enabled ? r300screen->caps.dxtc_swizzle : 1;
 123
 124         /* We don't support color clamping on r500, so that we can use color
 125          * intepolators for generic varyings. */
 126         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 127             return !is_r500;
 128
 129         /* Supported on r500 only. */
 130         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 131         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 132         case PIPE_CAP_SM3:
 133             return is_r500 ? 1 : 0;
 134
 135         /* Unsupported features. */
 136         case PIPE_CAP_QUERY_TIME_ELAPSED:
 137         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 138         case PIPE_CAP_INDEP_BLEND_ENABLE:
 139         case PIPE_CAP_INDEP_BLEND_FUNC:
 140         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 141         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 142         case PIPE_CAP_TGSI_INSTANCEID:
 143         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 144         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 145         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 146         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 147         case PIPE_CAP_SCALED_RESOLVE:
 148         case PIPE_CAP_MIN_TEXEL_OFFSET:
 149         case PIPE_CAP_MAX_TEXEL_OFFSET:
 150         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 151         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 152         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 153         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 154         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 155         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 156         case PIPE_CAP_COMPUTE:
 157         case PIPE_CAP_START_INSTANCE:
 158         case PIPE_CAP_QUERY_TIMESTAMP:
 159         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 160         case PIPE_CAP_CUBE_MAP_ARRAY:
 161         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 162         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 163             return 0;
 164
 165         /* SWTCL-only features. */
 166         case PIPE_CAP_PRIMITIVE_RESTART:
 167         case PIPE_CAP_USER_VERTEX_BUFFERS:
 168             return !r300screen->caps.has_tcl;
 169
 170         /* HWTCL-only features / limitations. */
 171         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 172         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 173         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 174             return r300screen->caps.has_tcl;
 175
 176         /* Texturing. */
 177         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 178             return r300screen->caps.num_tex_units;
 179         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 180         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 181         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 182             /* 13 == 4096, 12 == 2048 */
 183             return is_r500 ? 13 : 12;
 184
 185         /* Render targets. */
 186         case PIPE_CAP_MAX_RENDER_TARGETS:
 187             return 4;
 188     }
 189     return 0;
 190 }
 191
 192 static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
 193 {
 194    struct r300_screen* r300screen = r300_screen(pscreen);
 195    boolean is_r400 = r300screen->caps.is_r400;
 196    boolean is_r500 = r300screen->caps.is_r500;
 197
 198    switch (shader) {
 199     case PIPE_SHADER_FRAGMENT:
 200         switch (param)
 201         {
 202         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 203             return is_r500 || is_r400 ? 512 : 96;
 204         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 205             return is_r500 || is_r400 ? 512 : 64;
 206         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 207             return is_r500 || is_r400 ? 512 : 32;
 208         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 209             return is_r500 ? 511 : 4;
 210         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 211             return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
 212             /* Fragment shader limits. */
 213         case PIPE_SHADER_CAP_MAX_INPUTS:
 214             /* 2 colors + 8 texcoords are always supported
 215              * (minus fog and wpos).
 216              *
 217              * R500 has the ability to turn 3rd and 4th color into
 218              * additional texcoords but there is no two-sided color
 219              * selection then. However the facing bit can be used instead. */
 220             return 10;
 221         case PIPE_SHADER_CAP_MAX_CONSTS:
 222             return is_r500 ? 256 : 32;
 223         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 224             return 1;
 225         case PIPE_SHADER_CAP_MAX_TEMPS:
 226             return is_r500 ? 128 : is_r400 ? 64 : 32;
 227         case PIPE_SHADER_CAP_MAX_PREDS:
 228             return is_r500 ? 1 : 0;
 229         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 230            return r300screen->caps.num_tex_units;
 231         case PIPE_SHADER_CAP_MAX_ADDRS:
 232         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 233         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 234         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 235         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 236         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 237         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 238         case PIPE_SHADER_CAP_SUBROUTINES:
 239         case PIPE_SHADER_CAP_INTEGERS:
 240             return 0;
 241         case PIPE_SHADER_CAP_PREFERRED_IR:
 242             return PIPE_SHADER_IR_TGSI;
 243         }
 244         break;
 245     case PIPE_SHADER_VERTEX:
 246         switch (param)
 247         {
 248         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 249         case PIPE_SHADER_CAP_SUBROUTINES:
 250             return 0;
 251         default:;
 252         }
 253
 254         if (!r300screen->caps.has_tcl) {
 255             return draw_get_shader_param(shader, param);
 256         }
 257
 258         switch (param)
 259         {
 260         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 261         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 262             return is_r500 ? 1024 : 256;
 263         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 264             return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
 265         case PIPE_SHADER_CAP_MAX_INPUTS:
 266             return 16;
 267         case PIPE_SHADER_CAP_MAX_CONSTS:
 268             return 256;
 269         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 270             return 1;
 271         case PIPE_SHADER_CAP_MAX_TEMPS:
 272             return 32;
 273         case PIPE_SHADER_CAP_MAX_ADDRS:
 274             return 1; /* XXX guessed */
 275         case PIPE_SHADER_CAP_MAX_PREDS:
 276             return is_r500 ? 4 : 0; /* XXX guessed. */
 277         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 278             return 1;
 279         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 280         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 281         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 282         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 283         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 284         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 285         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 286         case PIPE_SHADER_CAP_SUBROUTINES:
 287         case PIPE_SHADER_CAP_INTEGERS:
 288         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 289             return 0;
 290         case PIPE_SHADER_CAP_PREFERRED_IR:
 291             return PIPE_SHADER_IR_TGSI;
 292         }
 293         break;
 294     }
 295     return 0;
 296 }
 297
 298 static float r300_get_paramf(struct pipe_screen* pscreen,
 299                              enum pipe_capf param)
 300 {
 301     struct r300_screen* r300screen = r300_screen(pscreen);
 302
 303     switch (param) {
 304         case PIPE_CAPF_MAX_LINE_WIDTH:
 305         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 306         case PIPE_CAPF_MAX_POINT_WIDTH:
 307         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 308             /* The maximum dimensions of the colorbuffer are our practical
 309              * rendering limits. 2048 pixels should be enough for anybody. */
 310             if (r300screen->caps.is_r500) {
 311                 return 4096.0f;
 312             } else if (r300screen->caps.is_r400) {
 313                 return 4021.0f;
 314             } else {
 315                 return 2560.0f;
 316             }
 317         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 318             return 16.0f;
 319         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 320             return 16.0f;
 321         case PIPE_CAPF_GUARD_BAND_LEFT:
 322         case PIPE_CAPF_GUARD_BAND_TOP:
 323         case PIPE_CAPF_GUARD_BAND_RIGHT:
 324         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 325             /* XXX I don't know what these should be but the least we can do is
 326              * silence the potential error message */
 327             return 0.0f;
 328         default:
 329             debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
 330                          param);
 331             return 0.0f;
 332     }
 333 }
 334
 335 static int r300_get_video_param(struct pipe_screen *screen,
 336                                 enum pipe_video_profile profile,
 337                                 enum pipe_video_cap param)
 338 {
 339    switch (param) {
 340       case PIPE_VIDEO_CAP_SUPPORTED:
 341          return vl_profile_supported(screen, profile);
 342       case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 343          return 0;
 344       case PIPE_VIDEO_CAP_MAX_WIDTH:
 345       case PIPE_VIDEO_CAP_MAX_HEIGHT:
 346          return vl_video_buffer_max_size(screen);
 347       case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 348          return PIPE_FORMAT_NV12;
 349       case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 350          return false;
 351       case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 352          return false;
 353       case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 354          return true;
 355       default:
 356          return 0;
 357    }
 358 }
 359
 360 /**
 361  * Whether the format matches:
 362  *   PIPE_FORMAT_?10?10?10?2_UNORM
 363  */
 364 static INLINE boolean
 365 util_format_is_rgba1010102_variant(const struct util_format_description *desc)
 366 {
 367    static const unsigned size[4] = {10, 10, 10, 2};
 368    unsigned chan;
 369
 370    if (desc->block.width != 1 ||
 371        desc->block.height != 1 ||
 372        desc->block.bits != 32)
 373       return FALSE;
 374
 375    for (chan = 0; chan < 4; ++chan) {
 376       if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
 377          desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
 378          return FALSE;
 379       if (desc->channel[chan].size != size[chan])
 380          return FALSE;
 381    }
 382
 383    return TRUE;
 384 }
 385
 386 static boolean r300_is_format_supported(struct pipe_screen* screen,
 387                                         enum pipe_format format,
 388                                         enum pipe_texture_target target,
 389                                         unsigned sample_count,
 390                                         unsigned usage)
 391 {
 392     uint32_t retval = 0;
 393     boolean drm_2_8_0 = r300_screen(screen)->info.drm_minor >= 8;
 394     boolean is_r500 = r300_screen(screen)->caps.is_r500;
 395     boolean is_r400 = r300_screen(screen)->caps.is_r400;
 396     boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
 397                               format == PIPE_FORMAT_R10G10B10X2_SNORM ||
 398                               format == PIPE_FORMAT_B10G10R10A2_UNORM ||
 399                               format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
 400     boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
 401                        format == PIPE_FORMAT_RGTC1_SNORM ||
 402                        format == PIPE_FORMAT_LATC1_UNORM ||
 403                        format == PIPE_FORMAT_LATC1_SNORM;
 404     boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
 405                        format == PIPE_FORMAT_RGTC2_SNORM ||
 406                        format == PIPE_FORMAT_LATC2_UNORM ||
 407                        format == PIPE_FORMAT_LATC2_SNORM;
 408     boolean is_x16f_xy16f = format == PIPE_FORMAT_R16_FLOAT ||
 409                             format == PIPE_FORMAT_R16G16_FLOAT ||
 410                             format == PIPE_FORMAT_A16_FLOAT ||
 411                             format == PIPE_FORMAT_L16_FLOAT ||
 412                             format == PIPE_FORMAT_L16A16_FLOAT ||
 413                             format == PIPE_FORMAT_I16_FLOAT;
 414     boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
 415                             format == PIPE_FORMAT_R16G16_FLOAT ||
 416                             format == PIPE_FORMAT_R16G16B16_FLOAT ||
 417                             format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
 418                             format == PIPE_FORMAT_R16G16B16X16_FLOAT;
 419     const struct util_format_description *desc;
 420
 421     if (!util_format_is_supported(format, usage))
 422        return FALSE;
 423
 424     /* Check multisampling support. */
 425     switch (sample_count) {
 426         case 0:
 427         case 1:
 428             break;
 429         case 2:
 430         case 4:
 431         case 6:
 432             /* We need DRM 2.8.0. */
 433             if (!drm_2_8_0) {
 434                 return FALSE;
 435             }
 436             /* Only support R500, because I didn't test older chipsets,
 437              * but MSAA should work there too. */
 438             if (!is_r500 && !debug_get_bool_option("RADEON_MSAA", FALSE)) {
 439                 return FALSE;
 440             }
 441             /* No texturing and scanout. */
 442             if (usage & (PIPE_BIND_SAMPLER_VIEW |
 443                          PIPE_BIND_DISPLAY_TARGET |
 444                          PIPE_BIND_SCANOUT)) {
 445                 return FALSE;
 446             }
 447
 448             desc = util_format_description(format);
 449
 450             if (is_r500) {
 451                 /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
 452                 if (!util_format_is_depth_or_stencil(format) &&
 453                     !util_format_is_rgba8_variant(desc) &&
 454                     !util_format_is_rgba1010102_variant(desc) &&
 455                     format != PIPE_FORMAT_R16G16B16A16_FLOAT &&
 456                     format != PIPE_FORMAT_R16G16B16X16_FLOAT) {
 457                     return FALSE;
 458                 }
 459             } else {
 460                 /* Only allow depth/stencil, RGBA8. */
 461                 if (!util_format_is_depth_or_stencil(format) &&
 462                     !util_format_is_rgba8_variant(desc)) {
 463                     return FALSE;
 464                 }
 465             }
 466             break;
 467         default:
 468             return FALSE;
 469     }
 470
 471     /* Check sampler format support. */
 472     if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 473         /* these two are broken for an unknown reason */
 474         format != PIPE_FORMAT_R8G8B8X8_SNORM &&
 475         format != PIPE_FORMAT_R16G16B16X16_SNORM &&
 476         /* ATI1N is r5xx-only. */
 477         (is_r500 || !is_ati1n) &&
 478         /* ATI2N is supported on r4xx-r5xx. */
 479         (is_r400 || is_r500 || !is_ati2n) &&
 480         /* R16F and RG16F texture support was added in as late as DRM 2.8.0 */
 481         (drm_2_8_0 || !is_x16f_xy16f) &&
 482         r300_is_sampler_format_supported(format)) {
 483         retval |= PIPE_BIND_SAMPLER_VIEW;
 484     }
 485
 486     /* Check colorbuffer format support. */
 487     if ((usage & (PIPE_BIND_RENDER_TARGET |
 488                   PIPE_BIND_DISPLAY_TARGET |
 489                   PIPE_BIND_SCANOUT |
 490                   PIPE_BIND_SHARED)) &&
 491         /* 2101010 cannot be rendered to on non-r5xx. */
 492         (!is_color2101010 || (is_r500 && drm_2_8_0)) &&
 493         r300_is_colorbuffer_format_supported(format)) {
 494         retval |= usage &
 495             (PIPE_BIND_RENDER_TARGET |
 496              PIPE_BIND_DISPLAY_TARGET |
 497              PIPE_BIND_SCANOUT |
 498              PIPE_BIND_SHARED);
 499     }
 500
 501     /* Check depth-stencil format support. */
 502     if (usage & PIPE_BIND_DEPTH_STENCIL &&
 503         r300_is_zs_format_supported(format)) {
 504         retval |= PIPE_BIND_DEPTH_STENCIL;
 505     }
 506
 507     /* Check vertex buffer format support. */
 508     if (usage & PIPE_BIND_VERTEX_BUFFER) {
 509         if (r300_screen(screen)->caps.has_tcl) {
 510             /* Half float is supported on >= R400. */
 511             if ((is_r400 || is_r500 || !is_half_float) &&
 512                 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
 513                 retval |= PIPE_BIND_VERTEX_BUFFER;
 514             }
 515         } else {
 516             /* SW TCL */
 517             if (!util_format_is_pure_integer(format)) {
 518                 retval |= PIPE_BIND_VERTEX_BUFFER;
 519             }
 520         }
 521     }
 522
 523     /* Transfers are always supported. */
 524     if (usage & PIPE_BIND_TRANSFER_READ)
 525         retval |= PIPE_BIND_TRANSFER_READ;
 526     if (usage & PIPE_BIND_TRANSFER_WRITE)
 527         retval |= PIPE_BIND_TRANSFER_WRITE;
 528
 529     return retval == usage;
 530 }
 531
 532 static void r300_destroy_screen(struct pipe_screen* pscreen)
 533 {
 534     struct r300_screen* r300screen = r300_screen(pscreen);
 535     struct radeon_winsys *rws = radeon_winsys(pscreen);
 536
 537     pipe_mutex_destroy(r300screen->cmask_mutex);
 538
 539     if (rws)
 540       rws->destroy(rws);
 541
 542     FREE(r300screen);
 543 }
 544
 545 static void r300_fence_reference(struct pipe_screen *screen,
 546                                  struct pipe_fence_handle **ptr,
 547                                  struct pipe_fence_handle *fence)
 548 {
 549     pb_reference((struct pb_buffer**)ptr,
 550                              (struct pb_buffer*)fence);
 551 }
 552
 553 static boolean r300_fence_signalled(struct pipe_screen *screen,
 554                                     struct pipe_fence_handle *fence)
 555 {
 556     struct radeon_winsys *rws = r300_screen(screen)->rws;
 557     struct pb_buffer *rfence = (struct pb_buffer*)fence;
 558
 559     return !rws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE);
 560 }
 561
 562 static boolean r300_fence_finish(struct pipe_screen *screen,
 563                                  struct pipe_fence_handle *fence,
 564                                  uint64_t timeout)
 565 {
 566     struct radeon_winsys *rws = r300_screen(screen)->rws;
 567     struct pb_buffer *rfence = (struct pb_buffer*)fence;
 568
 569     if (timeout != PIPE_TIMEOUT_INFINITE) {
 570         int64_t start_time = os_time_get();
 571
 572         /* Convert to microseconds. */
 573         timeout /= 1000;
 574
 575         /* Wait in a loop. */
 576         while (rws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE)) {
 577             if (os_time_get() - start_time >= timeout) {
 578                 return FALSE;
 579             }
 580             os_time_sleep(10);
 581         }
 582         return TRUE;
 583     }
 584
 585     rws->buffer_wait(rfence, RADEON_USAGE_READWRITE);
 586     return TRUE;
 587 }
 588
 589 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws)
 590 {
 591     struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
 592
 593     if (!r300screen) {
 594         FREE(r300screen);
 595         return NULL;
 596     }
 597
 598     rws->query_info(rws, &r300screen->info);
 599
 600     r300_init_debug(r300screen);
 601     r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
 602
 603     if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
 604         r300screen->caps.zmask_ram = 0;
 605     if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
 606         r300screen->caps.hiz_ram = 0;
 607
 608     if (r300screen->info.drm_minor < 8)
 609         r300screen->caps.has_us_format = FALSE;
 610
 611     r300screen->rws = rws;
 612     r300screen->screen.destroy = r300_destroy_screen;
 613     r300screen->screen.get_name = r300_get_name;
 614     r300screen->screen.get_vendor = r300_get_vendor;
 615     r300screen->screen.get_param = r300_get_param;
 616     r300screen->screen.get_shader_param = r300_get_shader_param;
 617     r300screen->screen.get_paramf = r300_get_paramf;
 618     r300screen->screen.get_video_param = r300_get_video_param;
 619     r300screen->screen.is_format_supported = r300_is_format_supported;
 620     r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 621     r300screen->screen.context_create = r300_create_context;
 622     r300screen->screen.fence_reference = r300_fence_reference;
 623     r300screen->screen.fence_signalled = r300_fence_signalled;
 624     r300screen->screen.fence_finish = r300_fence_finish;
 625
 626     r300_init_screen_resource_functions(r300screen);
 627
 628     util_format_s3tc_init();
 629     pipe_mutex_init(r300screen->cmask_mutex);
 630
 631     return &r300screen->screen;
 632 }