src/gallium/drivers/r300/r300_screen.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #include "util/u_format.h"
  25 #include "util/u_format_s3tc.h"
  26 #include "util/u_memory.h"
  27 #include "os/os_time.h"
  28 #include "vl/vl_decoder.h"
  29 #include "vl/vl_video_buffer.h"
  30
  31 #include "r300_context.h"
  32 #include "r300_texture.h"
  33 #include "r300_screen_buffer.h"
  34 #include "r300_state_inlines.h"
  35 #include "r300_public.h"
  36
  37 #include "draw/draw_context.h"
  38
  39 /* Return the identifier behind whom the brave coders responsible for this
  40  * amalgamation of code, sweat, and duct tape, routinely obscure their names.
  41  *
  42  * ...I should have just put "Corbin Simpson", but I'm not that cool.
  43  *
  44  * (Or egotistical. Yet.) */
  45 static const char* r300_get_vendor(struct pipe_screen* pscreen)
  46 {
  47     return "X.Org R300 Project";
  48 }
  49
  50 static const char* chip_families[] = {
  51     "unknown",
  52     "ATI R300",
  53     "ATI R350",
  54     "ATI RV350",
  55     "ATI RV370",
  56     "ATI RV380",
  57     "ATI RS400",
  58     "ATI RC410",
  59     "ATI RS480",
  60     "ATI R420",
  61     "ATI R423",
  62     "ATI R430",
  63     "ATI R480",
  64     "ATI R481",
  65     "ATI RV410",
  66     "ATI RS600",
  67     "ATI RS690",
  68     "ATI RS740",
  69     "ATI RV515",
  70     "ATI R520",
  71     "ATI RV530",
  72     "ATI R580",
  73     "ATI RV560",
  74     "ATI RV570"
  75 };
  76
  77 static const char* r300_get_name(struct pipe_screen* pscreen)
  78 {
  79     struct r300_screen* r300screen = r300_screen(pscreen);
  80
  81     return chip_families[r300screen->caps.family];
  82 }
  83
  84 static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
  85 {
  86     struct r300_screen* r300screen = r300_screen(pscreen);
  87     boolean is_r500 = r300screen->caps.is_r500;
  88
  89     switch (param) {
  90         /* Supported features (boolean caps). */
  91         case PIPE_CAP_NPOT_TEXTURES:
  92         case PIPE_CAP_TWO_SIDED_STENCIL:
  93         case PIPE_CAP_ANISOTROPIC_FILTER:
  94         case PIPE_CAP_POINT_SPRITE:
  95         case PIPE_CAP_OCCLUSION_QUERY:
  96         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  97         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  98         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  99         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 100         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 101         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 102         case PIPE_CAP_CONDITIONAL_RENDER:
 103         case PIPE_CAP_TEXTURE_BARRIER:
 104         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 105         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 106         case PIPE_CAP_USER_INDEX_BUFFERS:
 107         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 108         case PIPE_CAP_DEPTH_CLIP_DISABLE: /* XXX implemented, but breaks Regnum Online */
 109             return 1;
 110
 111         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 112             return R300_BUFFER_ALIGNMENT;
 113
 114         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 115             return 16;
 116
 117         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 118             return 120;
 119
 120         /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
 121         case PIPE_CAP_TEXTURE_SWIZZLE:
 122             return util_format_s3tc_enabled ? r300screen->caps.dxtc_swizzle : 1;
 123
 124         /* We don't support color clamping on r500, so that we can use color
 125          * intepolators for generic varyings. */
 126         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 127             return !is_r500;
 128
 129         /* Supported on r500 only. */
 130         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 131         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 132         case PIPE_CAP_SM3:
 133             return is_r500 ? 1 : 0;
 134
 135         /* Unsupported features. */
 136         case PIPE_CAP_QUERY_TIME_ELAPSED:
 137         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 138         case PIPE_CAP_INDEP_BLEND_ENABLE:
 139         case PIPE_CAP_INDEP_BLEND_FUNC:
 140         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 141         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 142         case PIPE_CAP_TGSI_INSTANCEID:
 143         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 144         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 145         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 146         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 147         case PIPE_CAP_SCALED_RESOLVE:
 148         case PIPE_CAP_MIN_TEXEL_OFFSET:
 149         case PIPE_CAP_MAX_TEXEL_OFFSET:
 150         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 151         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 152         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 153         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 154         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 155         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 156         case PIPE_CAP_COMPUTE:
 157         case PIPE_CAP_START_INSTANCE:
 158         case PIPE_CAP_QUERY_TIMESTAMP:
 159         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 160         case PIPE_CAP_CUBE_MAP_ARRAY:
 161         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 162         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 163             return 0;
 164
 165         /* SWTCL-only features. */
 166         case PIPE_CAP_PRIMITIVE_RESTART:
 167         case PIPE_CAP_USER_VERTEX_BUFFERS:
 168             return !r300screen->caps.has_tcl;
 169
 170         /* HWTCL-only features / limitations. */
 171         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 172         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 173         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 174             return r300screen->caps.has_tcl;
 175         case PIPE_CAP_TGSI_TEXCOORD:
 176             return 0;
 177
 178         /* Texturing. */
 179         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 180             return r300screen->caps.num_tex_units;
 181         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 182         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 183         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 184             /* 13 == 4096, 12 == 2048 */
 185             return is_r500 ? 13 : 12;
 186
 187         /* Render targets. */
 188         case PIPE_CAP_MAX_RENDER_TARGETS:
 189             return 4;
 190     }
 191     return 0;
 192 }
 193
 194 static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
 195 {
 196    struct r300_screen* r300screen = r300_screen(pscreen);
 197    boolean is_r400 = r300screen->caps.is_r400;
 198    boolean is_r500 = r300screen->caps.is_r500;
 199
 200    switch (shader) {
 201     case PIPE_SHADER_FRAGMENT:
 202         switch (param)
 203         {
 204         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 205             return is_r500 || is_r400 ? 512 : 96;
 206         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 207             return is_r500 || is_r400 ? 512 : 64;
 208         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 209             return is_r500 || is_r400 ? 512 : 32;
 210         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 211             return is_r500 ? 511 : 4;
 212         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 213             return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
 214             /* Fragment shader limits. */
 215         case PIPE_SHADER_CAP_MAX_INPUTS:
 216             /* 2 colors + 8 texcoords are always supported
 217              * (minus fog and wpos).
 218              *
 219              * R500 has the ability to turn 3rd and 4th color into
 220              * additional texcoords but there is no two-sided color
 221              * selection then. However the facing bit can be used instead. */
 222             return 10;
 223         case PIPE_SHADER_CAP_MAX_CONSTS:
 224             return is_r500 ? 256 : 32;
 225         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 226             return 1;
 227         case PIPE_SHADER_CAP_MAX_TEMPS:
 228             return is_r500 ? 128 : is_r400 ? 64 : 32;
 229         case PIPE_SHADER_CAP_MAX_PREDS:
 230             return is_r500 ? 1 : 0;
 231         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 232            return r300screen->caps.num_tex_units;
 233         case PIPE_SHADER_CAP_MAX_ADDRS:
 234         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 235         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 236         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 237         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 238         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 239         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 240         case PIPE_SHADER_CAP_SUBROUTINES:
 241         case PIPE_SHADER_CAP_INTEGERS:
 242             return 0;
 243         case PIPE_SHADER_CAP_PREFERRED_IR:
 244             return PIPE_SHADER_IR_TGSI;
 245         }
 246         break;
 247     case PIPE_SHADER_VERTEX:
 248         switch (param)
 249         {
 250         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 251         case PIPE_SHADER_CAP_SUBROUTINES:
 252             return 0;
 253         default:;
 254         }
 255
 256         if (!r300screen->caps.has_tcl) {
 257             return draw_get_shader_param(shader, param);
 258         }
 259
 260         switch (param)
 261         {
 262         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 263         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 264             return is_r500 ? 1024 : 256;
 265         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 266             return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
 267         case PIPE_SHADER_CAP_MAX_INPUTS:
 268             return 16;
 269         case PIPE_SHADER_CAP_MAX_CONSTS:
 270             return 256;
 271         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 272             return 1;
 273         case PIPE_SHADER_CAP_MAX_TEMPS:
 274             return 32;
 275         case PIPE_SHADER_CAP_MAX_ADDRS:
 276             return 1; /* XXX guessed */
 277         case PIPE_SHADER_CAP_MAX_PREDS:
 278             return is_r500 ? 4 : 0; /* XXX guessed. */
 279         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 280             return 1;
 281         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 282         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 283         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 284         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 285         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 286         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 287         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 288         case PIPE_SHADER_CAP_SUBROUTINES:
 289         case PIPE_SHADER_CAP_INTEGERS:
 290         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 291             return 0;
 292         case PIPE_SHADER_CAP_PREFERRED_IR:
 293             return PIPE_SHADER_IR_TGSI;
 294         }
 295         break;
 296     }
 297     return 0;
 298 }
 299
 300 static float r300_get_paramf(struct pipe_screen* pscreen,
 301                              enum pipe_capf param)
 302 {
 303     struct r300_screen* r300screen = r300_screen(pscreen);
 304
 305     switch (param) {
 306         case PIPE_CAPF_MAX_LINE_WIDTH:
 307         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 308         case PIPE_CAPF_MAX_POINT_WIDTH:
 309         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 310             /* The maximum dimensions of the colorbuffer are our practical
 311              * rendering limits. 2048 pixels should be enough for anybody. */
 312             if (r300screen->caps.is_r500) {
 313                 return 4096.0f;
 314             } else if (r300screen->caps.is_r400) {
 315                 return 4021.0f;
 316             } else {
 317                 return 2560.0f;
 318             }
 319         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 320             return 16.0f;
 321         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 322             return 16.0f;
 323         case PIPE_CAPF_GUARD_BAND_LEFT:
 324         case PIPE_CAPF_GUARD_BAND_TOP:
 325         case PIPE_CAPF_GUARD_BAND_RIGHT:
 326         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 327             /* XXX I don't know what these should be but the least we can do is
 328              * silence the potential error message */
 329             return 0.0f;
 330         default:
 331             debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
 332                          param);
 333             return 0.0f;
 334     }
 335 }
 336
 337 static int r300_get_video_param(struct pipe_screen *screen,
 338                                 enum pipe_video_profile profile,
 339                                 enum pipe_video_cap param)
 340 {
 341    switch (param) {
 342       case PIPE_VIDEO_CAP_SUPPORTED:
 343          return vl_profile_supported(screen, profile);
 344       case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 345          return 0;
 346       case PIPE_VIDEO_CAP_MAX_WIDTH:
 347       case PIPE_VIDEO_CAP_MAX_HEIGHT:
 348          return vl_video_buffer_max_size(screen);
 349       case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 350          return PIPE_FORMAT_NV12;
 351       case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 352          return false;
 353       case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 354          return false;
 355       case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 356          return true;
 357       default:
 358          return 0;
 359    }
 360 }
 361
 362 /**
 363  * Whether the format matches:
 364  *   PIPE_FORMAT_?10?10?10?2_UNORM
 365  */
 366 static INLINE boolean
 367 util_format_is_rgba1010102_variant(const struct util_format_description *desc)
 368 {
 369    static const unsigned size[4] = {10, 10, 10, 2};
 370    unsigned chan;
 371
 372    if (desc->block.width != 1 ||
 373        desc->block.height != 1 ||
 374        desc->block.bits != 32)
 375       return FALSE;
 376
 377    for (chan = 0; chan < 4; ++chan) {
 378       if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
 379          desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
 380          return FALSE;
 381       if (desc->channel[chan].size != size[chan])
 382          return FALSE;
 383    }
 384
 385    return TRUE;
 386 }
 387
 388 static boolean r300_is_format_supported(struct pipe_screen* screen,
 389                                         enum pipe_format format,
 390                                         enum pipe_texture_target target,
 391                                         unsigned sample_count,
 392                                         unsigned usage)
 393 {
 394     uint32_t retval = 0;
 395     boolean drm_2_8_0 = r300_screen(screen)->info.drm_minor >= 8;
 396     boolean is_r500 = r300_screen(screen)->caps.is_r500;
 397     boolean is_r400 = r300_screen(screen)->caps.is_r400;
 398     boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
 399                               format == PIPE_FORMAT_R10G10B10X2_SNORM ||
 400                               format == PIPE_FORMAT_B10G10R10A2_UNORM ||
 401                               format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
 402     boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
 403                        format == PIPE_FORMAT_RGTC1_SNORM ||
 404                        format == PIPE_FORMAT_LATC1_UNORM ||
 405                        format == PIPE_FORMAT_LATC1_SNORM;
 406     boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
 407                        format == PIPE_FORMAT_RGTC2_SNORM ||
 408                        format == PIPE_FORMAT_LATC2_UNORM ||
 409                        format == PIPE_FORMAT_LATC2_SNORM;
 410     boolean is_x16f_xy16f = format == PIPE_FORMAT_R16_FLOAT ||
 411                             format == PIPE_FORMAT_R16G16_FLOAT ||
 412                             format == PIPE_FORMAT_A16_FLOAT ||
 413                             format == PIPE_FORMAT_L16_FLOAT ||
 414                             format == PIPE_FORMAT_L16A16_FLOAT ||
 415                             format == PIPE_FORMAT_R16A16_FLOAT ||
 416                             format == PIPE_FORMAT_I16_FLOAT;
 417     boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
 418                             format == PIPE_FORMAT_R16G16_FLOAT ||
 419                             format == PIPE_FORMAT_R16G16B16_FLOAT ||
 420                             format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
 421                             format == PIPE_FORMAT_R16G16B16X16_FLOAT;
 422     const struct util_format_description *desc;
 423
 424     if (!util_format_is_supported(format, usage))
 425        return FALSE;
 426
 427     /* Check multisampling support. */
 428     switch (sample_count) {
 429         case 0:
 430         case 1:
 431             break;
 432         case 2:
 433         case 4:
 434         case 6:
 435             /* We need DRM 2.8.0. */
 436             if (!drm_2_8_0) {
 437                 return FALSE;
 438             }
 439             /* Only support R500, because I didn't test older chipsets,
 440              * but MSAA should work there too. */
 441             if (!is_r500 && !debug_get_bool_option("RADEON_MSAA", FALSE)) {
 442                 return FALSE;
 443             }
 444             /* No texturing and scanout. */
 445             if (usage & (PIPE_BIND_SAMPLER_VIEW |
 446                          PIPE_BIND_DISPLAY_TARGET |
 447                          PIPE_BIND_SCANOUT)) {
 448                 return FALSE;
 449             }
 450
 451             desc = util_format_description(format);
 452
 453             if (is_r500) {
 454                 /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
 455                 if (!util_format_is_depth_or_stencil(format) &&
 456                     !util_format_is_rgba8_variant(desc) &&
 457                     !util_format_is_rgba1010102_variant(desc) &&
 458                     format != PIPE_FORMAT_R16G16B16A16_FLOAT &&
 459                     format != PIPE_FORMAT_R16G16B16X16_FLOAT) {
 460                     return FALSE;
 461                 }
 462             } else {
 463                 /* Only allow depth/stencil, RGBA8. */
 464                 if (!util_format_is_depth_or_stencil(format) &&
 465                     !util_format_is_rgba8_variant(desc)) {
 466                     return FALSE;
 467                 }
 468             }
 469             break;
 470         default:
 471             return FALSE;
 472     }
 473
 474     /* Check sampler format support. */
 475     if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 476         /* these two are broken for an unknown reason */
 477         format != PIPE_FORMAT_R8G8B8X8_SNORM &&
 478         format != PIPE_FORMAT_R16G16B16X16_SNORM &&
 479         /* ATI1N is r5xx-only. */
 480         (is_r500 || !is_ati1n) &&
 481         /* ATI2N is supported on r4xx-r5xx. */
 482         (is_r400 || is_r500 || !is_ati2n) &&
 483         /* R16F and RG16F texture support was added in as late as DRM 2.8.0 */
 484         (drm_2_8_0 || !is_x16f_xy16f) &&
 485         r300_is_sampler_format_supported(format)) {
 486         retval |= PIPE_BIND_SAMPLER_VIEW;
 487     }
 488
 489     /* Check colorbuffer format support. */
 490     if ((usage & (PIPE_BIND_RENDER_TARGET |
 491                   PIPE_BIND_DISPLAY_TARGET |
 492                   PIPE_BIND_SCANOUT |
 493                   PIPE_BIND_SHARED)) &&
 494         /* 2101010 cannot be rendered to on non-r5xx. */
 495         (!is_color2101010 || (is_r500 && drm_2_8_0)) &&
 496         r300_is_colorbuffer_format_supported(format)) {
 497         retval |= usage &
 498             (PIPE_BIND_RENDER_TARGET |
 499              PIPE_BIND_DISPLAY_TARGET |
 500              PIPE_BIND_SCANOUT |
 501              PIPE_BIND_SHARED);
 502     }
 503
 504     /* Check depth-stencil format support. */
 505     if (usage & PIPE_BIND_DEPTH_STENCIL &&
 506         r300_is_zs_format_supported(format)) {
 507         retval |= PIPE_BIND_DEPTH_STENCIL;
 508     }
 509
 510     /* Check vertex buffer format support. */
 511     if (usage & PIPE_BIND_VERTEX_BUFFER) {
 512         if (r300_screen(screen)->caps.has_tcl) {
 513             /* Half float is supported on >= R400. */
 514             if ((is_r400 || is_r500 || !is_half_float) &&
 515                 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
 516                 retval |= PIPE_BIND_VERTEX_BUFFER;
 517             }
 518         } else {
 519             /* SW TCL */
 520             if (!util_format_is_pure_integer(format)) {
 521                 retval |= PIPE_BIND_VERTEX_BUFFER;
 522             }
 523         }
 524     }
 525
 526     /* Transfers are always supported. */
 527     if (usage & PIPE_BIND_TRANSFER_READ)
 528         retval |= PIPE_BIND_TRANSFER_READ;
 529     if (usage & PIPE_BIND_TRANSFER_WRITE)
 530         retval |= PIPE_BIND_TRANSFER_WRITE;
 531
 532     return retval == usage;
 533 }
 534
 535 static void r300_destroy_screen(struct pipe_screen* pscreen)
 536 {
 537     struct r300_screen* r300screen = r300_screen(pscreen);
 538     struct radeon_winsys *rws = radeon_winsys(pscreen);
 539
 540     pipe_mutex_destroy(r300screen->cmask_mutex);
 541
 542     if (rws)
 543       rws->destroy(rws);
 544
 545     FREE(r300screen);
 546 }
 547
 548 static void r300_fence_reference(struct pipe_screen *screen,
 549                                  struct pipe_fence_handle **ptr,
 550                                  struct pipe_fence_handle *fence)
 551 {
 552     pb_reference((struct pb_buffer**)ptr,
 553                              (struct pb_buffer*)fence);
 554 }
 555
 556 static boolean r300_fence_signalled(struct pipe_screen *screen,
 557                                     struct pipe_fence_handle *fence)
 558 {
 559     struct radeon_winsys *rws = r300_screen(screen)->rws;
 560     struct pb_buffer *rfence = (struct pb_buffer*)fence;
 561
 562     return !rws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE);
 563 }
 564
 565 static boolean r300_fence_finish(struct pipe_screen *screen,
 566                                  struct pipe_fence_handle *fence,
 567                                  uint64_t timeout)
 568 {
 569     struct radeon_winsys *rws = r300_screen(screen)->rws;
 570     struct pb_buffer *rfence = (struct pb_buffer*)fence;
 571
 572     if (timeout != PIPE_TIMEOUT_INFINITE) {
 573         int64_t start_time = os_time_get();
 574
 575         /* Convert to microseconds. */
 576         timeout /= 1000;
 577
 578         /* Wait in a loop. */
 579         while (rws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE)) {
 580             if (os_time_get() - start_time >= timeout) {
 581                 return FALSE;
 582             }
 583             os_time_sleep(10);
 584         }
 585         return TRUE;
 586     }
 587
 588     rws->buffer_wait(rfence, RADEON_USAGE_READWRITE);
 589     return TRUE;
 590 }
 591
 592 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws)
 593 {
 594     struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
 595
 596     if (!r300screen) {
 597         FREE(r300screen);
 598         return NULL;
 599     }
 600
 601     rws->query_info(rws, &r300screen->info);
 602
 603     r300_init_debug(r300screen);
 604     r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
 605
 606     if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
 607         r300screen->caps.zmask_ram = 0;
 608     if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
 609         r300screen->caps.hiz_ram = 0;
 610
 611     if (r300screen->info.drm_minor < 8)
 612         r300screen->caps.has_us_format = FALSE;
 613
 614     r300screen->rws = rws;
 615     r300screen->screen.destroy = r300_destroy_screen;
 616     r300screen->screen.get_name = r300_get_name;
 617     r300screen->screen.get_vendor = r300_get_vendor;
 618     r300screen->screen.get_param = r300_get_param;
 619     r300screen->screen.get_shader_param = r300_get_shader_param;
 620     r300screen->screen.get_paramf = r300_get_paramf;
 621     r300screen->screen.get_video_param = r300_get_video_param;
 622     r300screen->screen.is_format_supported = r300_is_format_supported;
 623     r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 624     r300screen->screen.context_create = r300_create_context;
 625     r300screen->screen.fence_reference = r300_fence_reference;
 626     r300screen->screen.fence_signalled = r300_fence_signalled;
 627     r300screen->screen.fence_finish = r300_fence_finish;
 628
 629     r300_init_screen_resource_functions(r300screen);
 630
 631     util_format_s3tc_init();
 632     pipe_mutex_init(r300screen->cmask_mutex);
 633
 634     return &r300screen->screen;
 635 }