gallium: add a cap to expose whether driver supports mixed color/zs bits
[mesa.git] / src / gallium / drivers / r300 / r300_screen.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "util/u_format.h"
25 #include "util/u_format_s3tc.h"
26 #include "util/u_memory.h"
27 #include "os/os_time.h"
28 #include "vl/vl_decoder.h"
29 #include "vl/vl_video_buffer.h"
30
31 #include "r300_context.h"
32 #include "r300_texture.h"
33 #include "r300_screen_buffer.h"
34 #include "r300_state_inlines.h"
35 #include "r300_public.h"
36
37 #include "draw/draw_context.h"
38
39 /* Return the identifier behind whom the brave coders responsible for this
40 * amalgamation of code, sweat, and duct tape, routinely obscure their names.
41 *
42 * ...I should have just put "Corbin Simpson", but I'm not that cool.
43 *
44 * (Or egotistical. Yet.) */
45 static const char* r300_get_vendor(struct pipe_screen* pscreen)
46 {
47 return "X.Org R300 Project";
48 }
49
50 static const char* r300_get_device_vendor(struct pipe_screen* pscreen)
51 {
52 return "ATI";
53 }
54
55 static const char* chip_families[] = {
56 "unknown",
57 "ATI R300",
58 "ATI R350",
59 "ATI RV350",
60 "ATI RV370",
61 "ATI RV380",
62 "ATI RS400",
63 "ATI RC410",
64 "ATI RS480",
65 "ATI R420",
66 "ATI R423",
67 "ATI R430",
68 "ATI R480",
69 "ATI R481",
70 "ATI RV410",
71 "ATI RS600",
72 "ATI RS690",
73 "ATI RS740",
74 "ATI RV515",
75 "ATI R520",
76 "ATI RV530",
77 "ATI R580",
78 "ATI RV560",
79 "ATI RV570"
80 };
81
82 static const char* r300_get_name(struct pipe_screen* pscreen)
83 {
84 struct r300_screen* r300screen = r300_screen(pscreen);
85
86 return chip_families[r300screen->caps.family];
87 }
88
89 static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
90 {
91 struct r300_screen* r300screen = r300_screen(pscreen);
92 boolean is_r500 = r300screen->caps.is_r500;
93
94 switch (param) {
95 /* Supported features (boolean caps). */
96 case PIPE_CAP_NPOT_TEXTURES:
97 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
98 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
99 case PIPE_CAP_TWO_SIDED_STENCIL:
100 case PIPE_CAP_ANISOTROPIC_FILTER:
101 case PIPE_CAP_POINT_SPRITE:
102 case PIPE_CAP_OCCLUSION_QUERY:
103 case PIPE_CAP_TEXTURE_SHADOW_MAP:
104 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
105 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
106 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
107 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
108 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
109 case PIPE_CAP_CONDITIONAL_RENDER:
110 case PIPE_CAP_TEXTURE_BARRIER:
111 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
112 case PIPE_CAP_USER_INDEX_BUFFERS:
113 case PIPE_CAP_USER_CONSTANT_BUFFERS:
114 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
115 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
116 case PIPE_CAP_CLIP_HALFZ:
117 return 1;
118
119 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
120 return R300_BUFFER_ALIGNMENT;
121
122 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
123 return 16;
124
125 case PIPE_CAP_GLSL_FEATURE_LEVEL:
126 return 120;
127
128 /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
129 case PIPE_CAP_TEXTURE_SWIZZLE:
130 return util_format_s3tc_enabled ? r300screen->caps.dxtc_swizzle : 1;
131
132 /* We don't support color clamping on r500, so that we can use color
133 * intepolators for generic varyings. */
134 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
135 return !is_r500;
136
137 /* Supported on r500 only. */
138 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
139 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
140 case PIPE_CAP_SM3:
141 return is_r500 ? 1 : 0;
142
143 /* Unsupported features. */
144 case PIPE_CAP_QUERY_TIME_ELAPSED:
145 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
146 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
147 case PIPE_CAP_INDEP_BLEND_ENABLE:
148 case PIPE_CAP_INDEP_BLEND_FUNC:
149 case PIPE_CAP_DEPTH_CLIP_DISABLE:
150 case PIPE_CAP_SHADER_STENCIL_EXPORT:
151 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
152 case PIPE_CAP_TGSI_INSTANCEID:
153 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
154 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
155 case PIPE_CAP_SEAMLESS_CUBE_MAP:
156 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
157 case PIPE_CAP_MIN_TEXEL_OFFSET:
158 case PIPE_CAP_MAX_TEXEL_OFFSET:
159 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
160 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
161 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
162 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
163 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
164 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
165 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
166 case PIPE_CAP_MAX_VERTEX_STREAMS:
167 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
168 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
169 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
170 case PIPE_CAP_COMPUTE:
171 case PIPE_CAP_START_INSTANCE:
172 case PIPE_CAP_QUERY_TIMESTAMP:
173 case PIPE_CAP_TEXTURE_MULTISAMPLE:
174 case PIPE_CAP_CUBE_MAP_ARRAY:
175 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
176 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
177 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
178 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
179 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
180 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
181 case PIPE_CAP_TEXTURE_GATHER_SM5:
182 case PIPE_CAP_TEXTURE_QUERY_LOD:
183 case PIPE_CAP_FAKE_SW_MSAA:
184 case PIPE_CAP_SAMPLE_SHADING:
185 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
186 case PIPE_CAP_DRAW_INDIRECT:
187 case PIPE_CAP_MULTI_DRAW_INDIRECT:
188 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
189 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
190 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
191 case PIPE_CAP_SAMPLER_VIEW_TARGET:
192 case PIPE_CAP_VERTEXID_NOBASE:
193 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
194 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
195 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
196 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
197 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
198 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
199 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
200 case PIPE_CAP_DEPTH_BOUNDS_TEST:
201 case PIPE_CAP_TGSI_TXQS:
202 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
203 case PIPE_CAP_SHAREABLE_SHADERS:
204 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
205 case PIPE_CAP_CLEAR_TEXTURE:
206 case PIPE_CAP_DRAW_PARAMETERS:
207 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
208 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
209 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
210 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
211 case PIPE_CAP_INVALIDATE_BUFFER:
212 case PIPE_CAP_GENERATE_MIPMAP:
213 case PIPE_CAP_STRING_MARKER:
214 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
215 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
216 case PIPE_CAP_QUERY_BUFFER_OBJECT:
217 case PIPE_CAP_QUERY_MEMORY_INFO:
218 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
219 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
220 case PIPE_CAP_CULL_DISTANCE:
221 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
222 case PIPE_CAP_TGSI_VOTE:
223 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
224 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
225 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
226 return 0;
227
228 /* SWTCL-only features. */
229 case PIPE_CAP_PRIMITIVE_RESTART:
230 case PIPE_CAP_USER_VERTEX_BUFFERS:
231 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
232 return !r300screen->caps.has_tcl;
233
234 /* HWTCL-only features / limitations. */
235 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
236 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
237 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
238 return r300screen->caps.has_tcl;
239 case PIPE_CAP_TGSI_TEXCOORD:
240 return 0;
241
242 /* Texturing. */
243 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
244 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
245 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
246 /* 13 == 4096, 12 == 2048 */
247 return is_r500 ? 13 : 12;
248
249 /* Render targets. */
250 case PIPE_CAP_MAX_RENDER_TARGETS:
251 return 4;
252 case PIPE_CAP_ENDIANNESS:
253 return PIPE_ENDIAN_LITTLE;
254
255 case PIPE_CAP_MAX_VIEWPORTS:
256 return 1;
257
258 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
259 return 2048;
260
261 case PIPE_CAP_VENDOR_ID:
262 return 0x1002;
263 case PIPE_CAP_DEVICE_ID:
264 return r300screen->info.pci_id;
265 case PIPE_CAP_ACCELERATED:
266 return 1;
267 case PIPE_CAP_VIDEO_MEMORY:
268 return r300screen->info.vram_size >> 20;
269 case PIPE_CAP_UMA:
270 return 0;
271 case PIPE_CAP_PCI_GROUP:
272 return r300screen->info.pci_domain;
273 case PIPE_CAP_PCI_BUS:
274 return r300screen->info.pci_bus;
275 case PIPE_CAP_PCI_DEVICE:
276 return r300screen->info.pci_dev;
277 case PIPE_CAP_PCI_FUNCTION:
278 return r300screen->info.pci_func;
279 }
280 return 0;
281 }
282
283 static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
284 {
285 struct r300_screen* r300screen = r300_screen(pscreen);
286 boolean is_r400 = r300screen->caps.is_r400;
287 boolean is_r500 = r300screen->caps.is_r500;
288
289 switch (shader) {
290 case PIPE_SHADER_FRAGMENT:
291 switch (param)
292 {
293 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
294 return is_r500 || is_r400 ? 512 : 96;
295 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
296 return is_r500 || is_r400 ? 512 : 64;
297 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
298 return is_r500 || is_r400 ? 512 : 32;
299 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
300 return is_r500 ? 511 : 4;
301 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
302 return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
303 /* Fragment shader limits. */
304 case PIPE_SHADER_CAP_MAX_INPUTS:
305 /* 2 colors + 8 texcoords are always supported
306 * (minus fog and wpos).
307 *
308 * R500 has the ability to turn 3rd and 4th color into
309 * additional texcoords but there is no two-sided color
310 * selection then. However the facing bit can be used instead. */
311 return 10;
312 case PIPE_SHADER_CAP_MAX_OUTPUTS:
313 return 4;
314 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
315 return (is_r500 ? 256 : 32) * sizeof(float[4]);
316 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
317 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
318 return 1;
319 case PIPE_SHADER_CAP_MAX_TEMPS:
320 return is_r500 ? 128 : is_r400 ? 64 : 32;
321 case PIPE_SHADER_CAP_MAX_PREDS:
322 return 0; /* unused */
323 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
324 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
325 return r300screen->caps.num_tex_units;
326 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
327 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
328 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
329 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
330 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
331 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
332 case PIPE_SHADER_CAP_SUBROUTINES:
333 case PIPE_SHADER_CAP_INTEGERS:
334 case PIPE_SHADER_CAP_DOUBLES:
335 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
336 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
337 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
338 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
339 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
340 return 0;
341 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
342 return 32;
343 case PIPE_SHADER_CAP_PREFERRED_IR:
344 return PIPE_SHADER_IR_TGSI;
345 case PIPE_SHADER_CAP_SUPPORTED_IRS:
346 return 0;
347 }
348 break;
349 case PIPE_SHADER_VERTEX:
350 switch (param)
351 {
352 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
353 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
354 case PIPE_SHADER_CAP_SUBROUTINES:
355 return 0;
356 default:;
357 }
358
359 if (!r300screen->caps.has_tcl) {
360 return draw_get_shader_param(shader, param);
361 }
362
363 switch (param)
364 {
365 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
366 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
367 return is_r500 ? 1024 : 256;
368 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
369 return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
370 case PIPE_SHADER_CAP_MAX_INPUTS:
371 return 16;
372 case PIPE_SHADER_CAP_MAX_OUTPUTS:
373 return 10;
374 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
375 return 256 * sizeof(float[4]);
376 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
377 return 1;
378 case PIPE_SHADER_CAP_MAX_TEMPS:
379 return 32;
380 case PIPE_SHADER_CAP_MAX_PREDS:
381 return 0; /* unused */
382 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
383 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
384 return 1;
385 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
386 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
387 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
388 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
389 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
390 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
391 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
392 case PIPE_SHADER_CAP_SUBROUTINES:
393 case PIPE_SHADER_CAP_INTEGERS:
394 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
395 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
396 case PIPE_SHADER_CAP_DOUBLES:
397 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
398 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
399 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
400 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
401 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
402 return 0;
403 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
404 return 32;
405 case PIPE_SHADER_CAP_PREFERRED_IR:
406 return PIPE_SHADER_IR_TGSI;
407 case PIPE_SHADER_CAP_SUPPORTED_IRS:
408 return 0;
409 }
410 break;
411 }
412 return 0;
413 }
414
415 static float r300_get_paramf(struct pipe_screen* pscreen,
416 enum pipe_capf param)
417 {
418 struct r300_screen* r300screen = r300_screen(pscreen);
419
420 switch (param) {
421 case PIPE_CAPF_MAX_LINE_WIDTH:
422 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
423 case PIPE_CAPF_MAX_POINT_WIDTH:
424 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
425 /* The maximum dimensions of the colorbuffer are our practical
426 * rendering limits. 2048 pixels should be enough for anybody. */
427 if (r300screen->caps.is_r500) {
428 return 4096.0f;
429 } else if (r300screen->caps.is_r400) {
430 return 4021.0f;
431 } else {
432 return 2560.0f;
433 }
434 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
435 return 16.0f;
436 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
437 return 16.0f;
438 case PIPE_CAPF_GUARD_BAND_LEFT:
439 case PIPE_CAPF_GUARD_BAND_TOP:
440 case PIPE_CAPF_GUARD_BAND_RIGHT:
441 case PIPE_CAPF_GUARD_BAND_BOTTOM:
442 return 0.0f;
443 default:
444 debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
445 param);
446 return 0.0f;
447 }
448 }
449
450 static int r300_get_video_param(struct pipe_screen *screen,
451 enum pipe_video_profile profile,
452 enum pipe_video_entrypoint entrypoint,
453 enum pipe_video_cap param)
454 {
455 switch (param) {
456 case PIPE_VIDEO_CAP_SUPPORTED:
457 return vl_profile_supported(screen, profile, entrypoint);
458 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
459 return 0;
460 case PIPE_VIDEO_CAP_MAX_WIDTH:
461 case PIPE_VIDEO_CAP_MAX_HEIGHT:
462 return vl_video_buffer_max_size(screen);
463 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
464 return PIPE_FORMAT_NV12;
465 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
466 return false;
467 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
468 return false;
469 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
470 return true;
471 case PIPE_VIDEO_CAP_MAX_LEVEL:
472 return vl_level_supported(screen, profile);
473 default:
474 return 0;
475 }
476 }
477
478 /**
479 * Whether the format matches:
480 * PIPE_FORMAT_?10?10?10?2_UNORM
481 */
482 static inline boolean
483 util_format_is_rgba1010102_variant(const struct util_format_description *desc)
484 {
485 static const unsigned size[4] = {10, 10, 10, 2};
486 unsigned chan;
487
488 if (desc->block.width != 1 ||
489 desc->block.height != 1 ||
490 desc->block.bits != 32)
491 return FALSE;
492
493 for (chan = 0; chan < 4; ++chan) {
494 if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
495 desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
496 return FALSE;
497 if (desc->channel[chan].size != size[chan])
498 return FALSE;
499 }
500
501 return TRUE;
502 }
503
504 static bool r300_is_blending_supported(struct r300_screen *rscreen,
505 enum pipe_format format)
506 {
507 int c;
508 const struct util_format_description *desc =
509 util_format_description(format);
510
511 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
512 return false;
513
514 c = util_format_get_first_non_void_channel(format);
515
516 /* RGBA16F */
517 if (rscreen->caps.is_r500 &&
518 desc->nr_channels == 4 &&
519 desc->channel[c].size == 16 &&
520 desc->channel[c].type == UTIL_FORMAT_TYPE_FLOAT)
521 return true;
522
523 if (desc->channel[c].normalized &&
524 desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED &&
525 desc->channel[c].size >= 4 &&
526 desc->channel[c].size <= 10) {
527 /* RGB10_A2, RGBA8, RGB5_A1, RGBA4, RGB565 */
528 if (desc->nr_channels >= 3)
529 return true;
530
531 if (format == PIPE_FORMAT_R8G8_UNORM)
532 return true;
533
534 /* R8, I8, L8, A8 */
535 if (desc->nr_channels == 1)
536 return true;
537 }
538
539 return false;
540 }
541
542 static boolean r300_is_format_supported(struct pipe_screen* screen,
543 enum pipe_format format,
544 enum pipe_texture_target target,
545 unsigned sample_count,
546 unsigned usage)
547 {
548 uint32_t retval = 0;
549 boolean is_r500 = r300_screen(screen)->caps.is_r500;
550 boolean is_r400 = r300_screen(screen)->caps.is_r400;
551 boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
552 format == PIPE_FORMAT_R10G10B10X2_SNORM ||
553 format == PIPE_FORMAT_B10G10R10A2_UNORM ||
554 format == PIPE_FORMAT_B10G10R10X2_UNORM ||
555 format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
556 boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
557 format == PIPE_FORMAT_RGTC1_SNORM ||
558 format == PIPE_FORMAT_LATC1_UNORM ||
559 format == PIPE_FORMAT_LATC1_SNORM;
560 boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
561 format == PIPE_FORMAT_RGTC2_SNORM ||
562 format == PIPE_FORMAT_LATC2_UNORM ||
563 format == PIPE_FORMAT_LATC2_SNORM;
564 boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
565 format == PIPE_FORMAT_R16G16_FLOAT ||
566 format == PIPE_FORMAT_R16G16B16_FLOAT ||
567 format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
568 format == PIPE_FORMAT_R16G16B16X16_FLOAT;
569 const struct util_format_description *desc;
570
571 if (!util_format_is_supported(format, usage))
572 return FALSE;
573
574 /* Check multisampling support. */
575 switch (sample_count) {
576 case 0:
577 case 1:
578 break;
579 case 2:
580 case 4:
581 case 6:
582 /* No texturing and scanout. */
583 if (usage & (PIPE_BIND_SAMPLER_VIEW |
584 PIPE_BIND_DISPLAY_TARGET |
585 PIPE_BIND_SCANOUT)) {
586 return FALSE;
587 }
588
589 desc = util_format_description(format);
590
591 if (is_r500) {
592 /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
593 if (!util_format_is_depth_or_stencil(format) &&
594 !util_format_is_rgba8_variant(desc) &&
595 !util_format_is_rgba1010102_variant(desc) &&
596 format != PIPE_FORMAT_R16G16B16A16_FLOAT &&
597 format != PIPE_FORMAT_R16G16B16X16_FLOAT) {
598 return FALSE;
599 }
600 } else {
601 /* Only allow depth/stencil, RGBA8. */
602 if (!util_format_is_depth_or_stencil(format) &&
603 !util_format_is_rgba8_variant(desc)) {
604 return FALSE;
605 }
606 }
607 break;
608 default:
609 return FALSE;
610 }
611
612 /* Check sampler format support. */
613 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
614 /* these two are broken for an unknown reason */
615 format != PIPE_FORMAT_R8G8B8X8_SNORM &&
616 format != PIPE_FORMAT_R16G16B16X16_SNORM &&
617 /* ATI1N is r5xx-only. */
618 (is_r500 || !is_ati1n) &&
619 /* ATI2N is supported on r4xx-r5xx. */
620 (is_r400 || is_r500 || !is_ati2n) &&
621 r300_is_sampler_format_supported(format)) {
622 retval |= PIPE_BIND_SAMPLER_VIEW;
623 }
624
625 /* Check colorbuffer format support. */
626 if ((usage & (PIPE_BIND_RENDER_TARGET |
627 PIPE_BIND_DISPLAY_TARGET |
628 PIPE_BIND_SCANOUT |
629 PIPE_BIND_SHARED |
630 PIPE_BIND_BLENDABLE)) &&
631 /* 2101010 cannot be rendered to on non-r5xx. */
632 (!is_color2101010 || is_r500) &&
633 r300_is_colorbuffer_format_supported(format)) {
634 retval |= usage &
635 (PIPE_BIND_RENDER_TARGET |
636 PIPE_BIND_DISPLAY_TARGET |
637 PIPE_BIND_SCANOUT |
638 PIPE_BIND_SHARED);
639
640 if (r300_is_blending_supported(r300_screen(screen), format)) {
641 retval |= usage & PIPE_BIND_BLENDABLE;
642 }
643 }
644
645 /* Check depth-stencil format support. */
646 if (usage & PIPE_BIND_DEPTH_STENCIL &&
647 r300_is_zs_format_supported(format)) {
648 retval |= PIPE_BIND_DEPTH_STENCIL;
649 }
650
651 /* Check vertex buffer format support. */
652 if (usage & PIPE_BIND_VERTEX_BUFFER) {
653 if (r300_screen(screen)->caps.has_tcl) {
654 /* Half float is supported on >= R400. */
655 if ((is_r400 || is_r500 || !is_half_float) &&
656 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
657 retval |= PIPE_BIND_VERTEX_BUFFER;
658 }
659 } else {
660 /* SW TCL */
661 if (!util_format_is_pure_integer(format)) {
662 retval |= PIPE_BIND_VERTEX_BUFFER;
663 }
664 }
665 }
666
667 /* Transfers are always supported. */
668 if (usage & PIPE_BIND_TRANSFER_READ)
669 retval |= PIPE_BIND_TRANSFER_READ;
670 if (usage & PIPE_BIND_TRANSFER_WRITE)
671 retval |= PIPE_BIND_TRANSFER_WRITE;
672
673 return retval == usage;
674 }
675
676 static void r300_destroy_screen(struct pipe_screen* pscreen)
677 {
678 struct r300_screen* r300screen = r300_screen(pscreen);
679 struct radeon_winsys *rws = radeon_winsys(pscreen);
680
681 if (rws && !rws->unref(rws))
682 return;
683
684 pipe_mutex_destroy(r300screen->cmask_mutex);
685
686 if (rws)
687 rws->destroy(rws);
688
689 FREE(r300screen);
690 }
691
692 static void r300_fence_reference(struct pipe_screen *screen,
693 struct pipe_fence_handle **ptr,
694 struct pipe_fence_handle *fence)
695 {
696 struct radeon_winsys *rws = r300_screen(screen)->rws;
697
698 rws->fence_reference(ptr, fence);
699 }
700
701 static boolean r300_fence_finish(struct pipe_screen *screen,
702 struct pipe_context *ctx,
703 struct pipe_fence_handle *fence,
704 uint64_t timeout)
705 {
706 struct radeon_winsys *rws = r300_screen(screen)->rws;
707
708 return rws->fence_wait(rws, fence, timeout);
709 }
710
711 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws)
712 {
713 struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
714
715 if (!r300screen) {
716 FREE(r300screen);
717 return NULL;
718 }
719
720 rws->query_info(rws, &r300screen->info);
721
722 r300_init_debug(r300screen);
723 r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
724
725 if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
726 r300screen->caps.zmask_ram = 0;
727 if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
728 r300screen->caps.hiz_ram = 0;
729
730 r300screen->rws = rws;
731 r300screen->screen.destroy = r300_destroy_screen;
732 r300screen->screen.get_name = r300_get_name;
733 r300screen->screen.get_vendor = r300_get_vendor;
734 r300screen->screen.get_device_vendor = r300_get_device_vendor;
735 r300screen->screen.get_param = r300_get_param;
736 r300screen->screen.get_shader_param = r300_get_shader_param;
737 r300screen->screen.get_paramf = r300_get_paramf;
738 r300screen->screen.get_video_param = r300_get_video_param;
739 r300screen->screen.is_format_supported = r300_is_format_supported;
740 r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
741 r300screen->screen.context_create = r300_create_context;
742 r300screen->screen.fence_reference = r300_fence_reference;
743 r300screen->screen.fence_finish = r300_fence_finish;
744
745 r300_init_screen_resource_functions(r300screen);
746
747 util_format_s3tc_init();
748 pipe_mutex_init(r300screen->cmask_mutex);
749
750 return &r300screen->screen;
751 }