6177ab3a5478e5507aad8d63b25371c4052797fe
[mesa.git] / src / gallium / drivers / r300 / r300_state.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "draw/draw_context.h"
25
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/u_pack_color.h"
29
30 #include "tgsi/tgsi_parse.h"
31
32 #include "pipe/p_config.h"
33
34 #include "r300_cb.h"
35 #include "r300_context.h"
36 #include "r300_emit.h"
37 #include "r300_reg.h"
38 #include "r300_screen.h"
39 #include "r300_screen_buffer.h"
40 #include "r300_state_inlines.h"
41 #include "r300_fs.h"
42 #include "r300_texture.h"
43 #include "r300_vs.h"
44 #include "r300_winsys.h"
45
46 /* r300_state: Functions used to intialize state context by translating
47 * Gallium state objects into semi-native r300 state objects. */
48
49 #define UPDATE_STATE(cso, atom) \
50 if (cso != atom.state) { \
51 atom.state = cso; \
52 atom.dirty = TRUE; \
53 }
54
55 static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA,
56 unsigned dstRGB, unsigned dstA)
57 {
58 /* If the blend equation is ADD or REVERSE_SUBTRACT,
59 * SRC_ALPHA == 0, and the following state is set, the colorbuffer
60 * will not be changed.
61 * Notice that the dst factors are the src factors inverted. */
62 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
63 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
64 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
65 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
66 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
67 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
68 srcA == PIPE_BLENDFACTOR_ZERO) &&
69 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
70 dstRGB == PIPE_BLENDFACTOR_ONE) &&
71 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
72 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
73 dstA == PIPE_BLENDFACTOR_ONE);
74 }
75
76 static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA,
77 unsigned dstRGB, unsigned dstA)
78 {
79 /* If the blend equation is ADD or REVERSE_SUBTRACT,
80 * SRC_ALPHA == 1, and the following state is set, the colorbuffer
81 * will not be changed.
82 * Notice that the dst factors are the src factors inverted. */
83 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
84 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
85 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
86 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
87 srcA == PIPE_BLENDFACTOR_ZERO) &&
88 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
89 dstRGB == PIPE_BLENDFACTOR_ONE) &&
90 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
91 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
92 dstA == PIPE_BLENDFACTOR_ONE);
93 }
94
95 static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA,
96 unsigned dstRGB, unsigned dstA)
97 {
98 /* If the blend equation is ADD or REVERSE_SUBTRACT,
99 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer
100 * will not be changed.
101 * Notice that the dst factors are the src factors inverted. */
102 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
103 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
104 (srcA == PIPE_BLENDFACTOR_ZERO) &&
105 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
106 dstRGB == PIPE_BLENDFACTOR_ONE) &&
107 (dstA == PIPE_BLENDFACTOR_ONE);
108 }
109
110 static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA,
111 unsigned dstRGB, unsigned dstA)
112 {
113 /* If the blend equation is ADD or REVERSE_SUBTRACT,
114 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer
115 * will not be changed.
116 * Notice that the dst factors are the src factors inverted. */
117 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
118 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
119 (srcA == PIPE_BLENDFACTOR_ZERO) &&
120 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
121 dstRGB == PIPE_BLENDFACTOR_ONE) &&
122 (dstA == PIPE_BLENDFACTOR_ONE);
123 }
124
125 static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA,
126 unsigned dstRGB, unsigned dstA)
127 {
128 /* If the blend equation is ADD or REVERSE_SUBTRACT,
129 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set,
130 * the colorbuffer will not be changed.
131 * Notice that the dst factors are the src factors inverted. */
132 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
133 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
134 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
135 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
136 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
137 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
138 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
139 srcA == PIPE_BLENDFACTOR_ZERO) &&
140 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
141 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
142 dstRGB == PIPE_BLENDFACTOR_ONE) &&
143 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
144 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
145 dstA == PIPE_BLENDFACTOR_ONE);
146 }
147
148 static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA,
149 unsigned dstRGB, unsigned dstA)
150 {
151 /* If the blend equation is ADD or REVERSE_SUBTRACT,
152 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set,
153 * the colorbuffer will not be changed.
154 * Notice that the dst factors are the src factors inverted. */
155 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
156 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
157 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
158 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
159 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
160 srcA == PIPE_BLENDFACTOR_ZERO) &&
161 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
162 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
163 dstRGB == PIPE_BLENDFACTOR_ONE) &&
164 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
165 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
166 dstA == PIPE_BLENDFACTOR_ONE);
167 }
168
169 static unsigned bgra_cmask(unsigned mask)
170 {
171 /* Gallium uses RGBA color ordering while R300 expects BGRA. */
172
173 return ((mask & PIPE_MASK_R) << 2) |
174 ((mask & PIPE_MASK_B) >> 2) |
175 (mask & (PIPE_MASK_G | PIPE_MASK_A));
176 }
177
178 /* Create a new blend state based on the CSO blend state.
179 *
180 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
181 static void* r300_create_blend_state(struct pipe_context* pipe,
182 const struct pipe_blend_state* state)
183 {
184 struct r300_screen* r300screen = r300_screen(pipe->screen);
185 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
186 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */
187 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */
188 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */
189 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */
190 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */
191 CB_LOCALS;
192
193 if (state->rt[0].blend_enable)
194 {
195 unsigned eqRGB = state->rt[0].rgb_func;
196 unsigned srcRGB = state->rt[0].rgb_src_factor;
197 unsigned dstRGB = state->rt[0].rgb_dst_factor;
198
199 unsigned eqA = state->rt[0].alpha_func;
200 unsigned srcA = state->rt[0].alpha_src_factor;
201 unsigned dstA = state->rt[0].alpha_dst_factor;
202
203 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
204 * this is just the crappy D3D naming */
205 blend_control = R300_ALPHA_BLEND_ENABLE |
206 r300_translate_blend_function(eqRGB) |
207 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) |
208 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT);
209
210 /* Optimization: some operations do not require the destination color.
211 *
212 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled,
213 * otherwise blending gives incorrect results. It seems to be
214 * a hardware bug. */
215 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN ||
216 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX ||
217 dstRGB != PIPE_BLENDFACTOR_ZERO ||
218 dstA != PIPE_BLENDFACTOR_ZERO ||
219 srcRGB == PIPE_BLENDFACTOR_DST_COLOR ||
220 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA ||
221 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR ||
222 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
223 srcA == PIPE_BLENDFACTOR_DST_COLOR ||
224 srcA == PIPE_BLENDFACTOR_DST_ALPHA ||
225 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR ||
226 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
227 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) {
228 /* Enable reading from the colorbuffer. */
229 blend_control |= R300_READ_ENABLE;
230
231 if (r300screen->caps.is_r500) {
232 /* Optimization: Depending on incoming pixels, we can
233 * conditionally disable the reading in hardware... */
234 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN &&
235 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) {
236 /* Disable reading if SRC_ALPHA == 0. */
237 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
238 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
239 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
240 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
241 dstA == PIPE_BLENDFACTOR_ZERO)) {
242 blend_control |= R500_SRC_ALPHA_0_NO_READ;
243 }
244
245 /* Disable reading if SRC_ALPHA == 1. */
246 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
247 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
248 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
249 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
250 dstA == PIPE_BLENDFACTOR_ZERO)) {
251 blend_control |= R500_SRC_ALPHA_1_NO_READ;
252 }
253 }
254 }
255 }
256
257 /* Optimization: discard pixels which don't change the colorbuffer.
258 *
259 * The code below is non-trivial and some math is involved.
260 *
261 * Discarding pixels must be disabled when FP16 AA is enabled.
262 * This is a hardware bug. Also, this implementation wouldn't work
263 * with FP blending enabled and equation clamping disabled.
264 *
265 * Equations other than ADD are rarely used and therefore won't be
266 * optimized. */
267 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) &&
268 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) {
269 /* ADD: X+Y
270 * REVERSE_SUBTRACT: Y-X
271 *
272 * The idea is:
273 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1,
274 * then CB will not be changed.
275 *
276 * Given the srcFactor and dstFactor variables, we can derive
277 * what src and dst should be equal to and discard appropriate
278 * pixels.
279 */
280 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) {
281 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
282 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA,
283 dstRGB, dstA)) {
284 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1;
285 } else if (blend_discard_if_src_color_0(srcRGB, srcA,
286 dstRGB, dstA)) {
287 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0;
288 } else if (blend_discard_if_src_color_1(srcRGB, srcA,
289 dstRGB, dstA)) {
290 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1;
291 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA,
292 dstRGB, dstA)) {
293 blend_control |=
294 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0;
295 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA,
296 dstRGB, dstA)) {
297 blend_control |=
298 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1;
299 }
300 }
301
302 /* separate alpha */
303 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
304 blend_control |= R300_SEPARATE_ALPHA_ENABLE;
305 alpha_blend_control =
306 r300_translate_blend_function(eqA) |
307 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) |
308 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT);
309 }
310 }
311
312 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
313 if (state->logicop_enable) {
314 rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
315 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
316 }
317
318 /* Color channel masks for all MRTs. */
319 color_channel_mask = bgra_cmask(state->rt[0].colormask);
320 if (r300screen->caps.is_r500 && state->independent_blend_enable) {
321 if (state->rt[1].blend_enable) {
322 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4;
323 }
324 if (state->rt[2].blend_enable) {
325 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8;
326 }
327 if (state->rt[3].blend_enable) {
328 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12;
329 }
330 }
331
332 /* Neither fglrx nor classic r300 ever set this, regardless of dithering
333 * state. Since it's an optional implementation detail, we can leave it
334 * out and never dither.
335 *
336 * This could be revisited if we ever get quality or conformance hints.
337 *
338 if (state->dither) {
339 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
340 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
341 }
342 */
343
344 /* Build a command buffer. */
345 BEGIN_CB(blend->cb, 8);
346 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
347 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
348 OUT_CB(blend_control);
349 OUT_CB(alpha_blend_control);
350 OUT_CB(color_channel_mask);
351 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
352 END_CB;
353
354 /* The same as above, but with no colorbuffer reads and writes. */
355 BEGIN_CB(blend->cb_no_readwrite, 8);
356 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
357 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
358 OUT_CB(0);
359 OUT_CB(0);
360 OUT_CB(0);
361 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
362 END_CB;
363
364 return (void*)blend;
365 }
366
367 /* Bind blend state. */
368 static void r300_bind_blend_state(struct pipe_context* pipe,
369 void* state)
370 {
371 struct r300_context* r300 = r300_context(pipe);
372
373 UPDATE_STATE(state, r300->blend_state);
374 }
375
376 /* Free blend state. */
377 static void r300_delete_blend_state(struct pipe_context* pipe,
378 void* state)
379 {
380 FREE(state);
381 }
382
383 /* Convert float to 10bit integer */
384 static unsigned float_to_fixed10(float f)
385 {
386 return CLAMP((unsigned)(f * 1023.9f), 0, 1023);
387 }
388
389 /* Set blend color.
390 * Setup both R300 and R500 registers, figure out later which one to write. */
391 static void r300_set_blend_color(struct pipe_context* pipe,
392 const struct pipe_blend_color* color)
393 {
394 struct r300_context* r300 = r300_context(pipe);
395 struct r300_blend_color_state* state =
396 (struct r300_blend_color_state*)r300->blend_color_state.state;
397 CB_LOCALS;
398
399 if (r300->screen->caps.is_r500) {
400 /* XXX if FP16 blending is enabled, we should use the FP16 format */
401 BEGIN_CB(state->cb, 3);
402 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
403 OUT_CB(float_to_fixed10(color->color[0]) |
404 (float_to_fixed10(color->color[3]) << 16));
405 OUT_CB(float_to_fixed10(color->color[2]) |
406 (float_to_fixed10(color->color[1]) << 16));
407 END_CB;
408 } else {
409 union util_color uc;
410 util_pack_color(color->color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
411
412 BEGIN_CB(state->cb, 2);
413 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui);
414 END_CB;
415 }
416
417 r300->blend_color_state.dirty = TRUE;
418 }
419
420 static void r300_set_clip_state(struct pipe_context* pipe,
421 const struct pipe_clip_state* state)
422 {
423 struct r300_context* r300 = r300_context(pipe);
424 struct r300_clip_state *clip =
425 (struct r300_clip_state*)r300->clip_state.state;
426 CB_LOCALS;
427
428 clip->clip = *state;
429
430 if (r300->screen->caps.has_tcl) {
431 BEGIN_CB(clip->cb, 29);
432 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG,
433 (r300->screen->caps.is_r500 ?
434 R500_PVS_UCP_START : R300_PVS_UCP_START));
435 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
436 OUT_CB_TABLE(state->ucp, 6 * 4);
437 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) |
438 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
439 END_CB;
440
441 r300->clip_state.dirty = TRUE;
442 } else {
443 draw_flush(r300->draw);
444 draw_set_clip_state(r300->draw, state);
445 }
446 }
447
448 static void
449 r300_set_sample_mask(struct pipe_context *pipe,
450 unsigned sample_mask)
451 {
452 }
453
454
455 /* Create a new depth, stencil, and alpha state based on the CSO dsa state.
456 *
457 * This contains the depth buffer, stencil buffer, alpha test, and such.
458 * On the Radeon, depth and stencil buffer setup are intertwined, which is
459 * the reason for some of the strange-looking assignments across registers. */
460 static void*
461 r300_create_dsa_state(struct pipe_context* pipe,
462 const struct pipe_depth_stencil_alpha_state* state)
463 {
464 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps;
465 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state);
466 CB_LOCALS;
467
468 dsa->dsa = *state;
469
470 /* Depth test setup. */
471 if (state->depth.enabled) {
472 dsa->z_buffer_control |= R300_Z_ENABLE;
473
474 if (state->depth.writemask) {
475 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE;
476 }
477
478 dsa->z_stencil_control |=
479 (r300_translate_depth_stencil_function(state->depth.func) <<
480 R300_Z_FUNC_SHIFT);
481 }
482
483 /* Stencil buffer setup. */
484 if (state->stencil[0].enabled) {
485 dsa->z_buffer_control |= R300_STENCIL_ENABLE;
486 dsa->z_stencil_control |=
487 (r300_translate_depth_stencil_function(state->stencil[0].func) <<
488 R300_S_FRONT_FUNC_SHIFT) |
489 (r300_translate_stencil_op(state->stencil[0].fail_op) <<
490 R300_S_FRONT_SFAIL_OP_SHIFT) |
491 (r300_translate_stencil_op(state->stencil[0].zpass_op) <<
492 R300_S_FRONT_ZPASS_OP_SHIFT) |
493 (r300_translate_stencil_op(state->stencil[0].zfail_op) <<
494 R300_S_FRONT_ZFAIL_OP_SHIFT);
495
496 dsa->stencil_ref_mask =
497 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
498 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
499
500 if (state->stencil[1].enabled) {
501 dsa->two_sided = TRUE;
502
503 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK;
504 dsa->z_stencil_control |=
505 (r300_translate_depth_stencil_function(state->stencil[1].func) <<
506 R300_S_BACK_FUNC_SHIFT) |
507 (r300_translate_stencil_op(state->stencil[1].fail_op) <<
508 R300_S_BACK_SFAIL_OP_SHIFT) |
509 (r300_translate_stencil_op(state->stencil[1].zpass_op) <<
510 R300_S_BACK_ZPASS_OP_SHIFT) |
511 (r300_translate_stencil_op(state->stencil[1].zfail_op) <<
512 R300_S_BACK_ZFAIL_OP_SHIFT);
513
514 dsa->stencil_ref_bf =
515 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) |
516 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
517
518 if (caps->is_r500) {
519 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
520 } else {
521 dsa->two_sided_stencil_ref =
522 (state->stencil[0].valuemask != state->stencil[1].valuemask ||
523 state->stencil[0].writemask != state->stencil[1].writemask);
524 }
525 }
526 }
527
528 /* Alpha test setup. */
529 if (state->alpha.enabled) {
530 dsa->alpha_function =
531 r300_translate_alpha_function(state->alpha.func) |
532 R300_FG_ALPHA_FUNC_ENABLE;
533
534 /* We could use 10bit alpha ref but who needs that? */
535 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value);
536
537 if (caps->is_r500)
538 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT;
539 }
540
541 BEGIN_CB(&dsa->cb_begin, 8);
542 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
543 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
544 OUT_CB(dsa->z_buffer_control);
545 OUT_CB(dsa->z_stencil_control);
546 OUT_CB(dsa->stencil_ref_mask);
547 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
548 END_CB;
549
550 BEGIN_CB(dsa->cb_no_readwrite, 8);
551 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
552 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
553 OUT_CB(0);
554 OUT_CB(0);
555 OUT_CB(0);
556 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
557 END_CB;
558
559 return (void*)dsa;
560 }
561
562 static void r300_dsa_inject_stencilref(struct r300_context *r300)
563 {
564 struct r300_dsa_state *dsa =
565 (struct r300_dsa_state*)r300->dsa_state.state;
566
567 if (!dsa)
568 return;
569
570 dsa->stencil_ref_mask =
571 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) |
572 r300->stencil_ref.ref_value[0];
573 dsa->stencil_ref_bf =
574 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) |
575 r300->stencil_ref.ref_value[1];
576 }
577
578 /* Bind DSA state. */
579 static void r300_bind_dsa_state(struct pipe_context* pipe,
580 void* state)
581 {
582 struct r300_context* r300 = r300_context(pipe);
583
584 if (!state) {
585 return;
586 }
587
588 UPDATE_STATE(state, r300->dsa_state);
589
590 r300_dsa_inject_stencilref(r300);
591 }
592
593 /* Free DSA state. */
594 static void r300_delete_dsa_state(struct pipe_context* pipe,
595 void* state)
596 {
597 FREE(state);
598 }
599
600 static void r300_set_stencil_ref(struct pipe_context* pipe,
601 const struct pipe_stencil_ref* sr)
602 {
603 struct r300_context* r300 = r300_context(pipe);
604
605 r300->stencil_ref = *sr;
606
607 r300_dsa_inject_stencilref(r300);
608 r300->dsa_state.dirty = TRUE;
609 }
610
611 /* This switcheroo is needed just because of goddamned MACRO_SWITCH. */
612 static void r300_fb_set_tiling_flags(struct r300_context *r300,
613 const struct pipe_framebuffer_state *old_state,
614 const struct pipe_framebuffer_state *new_state)
615 {
616 struct r300_texture *tex;
617 unsigned i, level;
618
619 /* Set tiling flags for new surfaces. */
620 for (i = 0; i < new_state->nr_cbufs; i++) {
621 tex = r300_texture(new_state->cbufs[i]->texture);
622 level = new_state->cbufs[i]->level;
623
624 r300->rws->buffer_set_tiling(r300->rws, tex->buffer,
625 tex->pitch[0] * util_format_get_blocksize(tex->b.b.format),
626 tex->microtile,
627 tex->mip_macrotile[level]);
628 }
629 if (new_state->zsbuf) {
630 tex = r300_texture(new_state->zsbuf->texture);
631 level = new_state->zsbuf->level;
632
633 r300->rws->buffer_set_tiling(r300->rws, tex->buffer,
634 tex->pitch[0] * util_format_get_blocksize(tex->b.b.format),
635 tex->microtile,
636 tex->mip_macrotile[level]);
637 }
638 }
639
640 static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index,
641 const char *binding)
642 {
643 struct pipe_resource *tex = surf->texture;
644 struct r300_texture *rtex = r300_texture(tex);
645
646 fprintf(stderr,
647 "r300: %s[%i] Dim: %ix%i, Offset: %i, ZSlice: %i, "
648 "Face: %i, Level: %i, Format: %s\n"
649
650 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, "
651 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n",
652
653 binding, index, surf->width, surf->height, surf->offset,
654 surf->zslice, surf->face, surf->level,
655 util_format_short_name(surf->format),
656
657 rtex->macrotile ? "YES" : " NO", rtex->microtile ? "YES" : " NO",
658 rtex->hwpitch[0], tex->width0, tex->height0, tex->depth0,
659 tex->last_level, util_format_short_name(tex->format));
660 }
661
662 static void copy_framebuffer_state(struct pipe_framebuffer_state *dst,
663 const struct pipe_framebuffer_state *src)
664 {
665 unsigned i;
666
667 for (i = 0; i < src->nr_cbufs; i++) {
668 pipe_surface_reference(&dst->cbufs[i], src->cbufs[i]);
669 }
670 for (; i < dst->nr_cbufs; i++) {
671 pipe_surface_reference(&dst->cbufs[i], NULL);
672 }
673 pipe_surface_reference(&dst->zsbuf, src->zsbuf);
674
675 dst->nr_cbufs = src->nr_cbufs;
676 dst->width = src->width;
677 dst->height = src->height;
678 }
679
680 static void
681 r300_set_framebuffer_state(struct pipe_context* pipe,
682 const struct pipe_framebuffer_state* state)
683 {
684 struct r300_context* r300 = r300_context(pipe);
685 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
686 struct pipe_framebuffer_state *old_state = r300->fb_state.state;
687 unsigned max_width, max_height, i;
688 uint32_t zbuffer_bpp = 0;
689
690 if (r300->screen->caps.is_r500) {
691 max_width = max_height = 4096;
692 } else if (r300->screen->caps.is_r400) {
693 max_width = max_height = 4021;
694 } else {
695 max_width = max_height = 2560;
696 }
697
698 if (state->width > max_width || state->height > max_height) {
699 fprintf(stderr, "r300: Implementation error: Render targets are too "
700 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__);
701 return;
702 }
703
704 if (r300->draw) {
705 draw_flush(r300->draw);
706 }
707
708 r300->gpu_flush.dirty = TRUE;
709 r300->aa_state.dirty = TRUE;
710 r300->fb_state.dirty = TRUE;
711 r300->hyperz_state.dirty = TRUE;
712 r300->fb_state_pipelined.dirty = TRUE;
713
714 /* If nr_cbufs is changed from zero to non-zero or vice versa... */
715 if (!!old_state->nr_cbufs != !!state->nr_cbufs) {
716 r300->blend_state.dirty = TRUE;
717 }
718 /* If zsbuf is set from NULL to non-NULL or vice versa.. */
719 if (!!old_state->zsbuf != !!state->zsbuf) {
720 r300->dsa_state.dirty = TRUE;
721 }
722
723 /* The tiling flags are dependent on the surface miplevel, unfortunately. */
724 r300_fb_set_tiling_flags(r300, r300->fb_state.state, state);
725
726 copy_framebuffer_state(r300->fb_state.state, state);
727
728 r300->fb_state.size =
729 2 +
730 (8 * state->nr_cbufs) +
731 (state->zsbuf ? (r300->screen->caps.has_hiz ? 18 : 14) : 0);
732
733 /* Polygon offset depends on the zbuffer bit depth. */
734 if (state->zsbuf && r300->polygon_offset_enabled) {
735 switch (util_format_get_blocksize(state->zsbuf->texture->format)) {
736 case 2:
737 zbuffer_bpp = 16;
738 break;
739 case 4:
740 zbuffer_bpp = 24;
741 break;
742 }
743
744 if (r300->zbuffer_bpp != zbuffer_bpp) {
745 r300->zbuffer_bpp = zbuffer_bpp;
746 r300->rs_state.dirty = TRUE;
747 }
748 }
749
750 /* Set up AA config. */
751 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
752 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) {
753 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE;
754
755 switch (state->cbufs[0]->texture->nr_samples) {
756 case 2:
757 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2;
758 break;
759 case 3:
760 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3;
761 break;
762 case 4:
763 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4;
764 break;
765 case 6:
766 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6;
767 break;
768 }
769 } else {
770 aa->aa_config = 0;
771 }
772 }
773
774 if (DBG_ON(r300, DBG_FB)) {
775 fprintf(stderr, "r300: set_framebuffer_state:\n");
776 for (i = 0; i < state->nr_cbufs; i++) {
777 r300_print_fb_surf_info(state->cbufs[i], i, "CB");
778 }
779 if (state->zsbuf) {
780 r300_print_fb_surf_info(state->zsbuf, 0, "ZB");
781 }
782 }
783 }
784
785 /* Create fragment shader state. */
786 static void* r300_create_fs_state(struct pipe_context* pipe,
787 const struct pipe_shader_state* shader)
788 {
789 struct r300_fragment_shader* fs = NULL;
790
791 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader);
792
793 /* Copy state directly into shader. */
794 fs->state = *shader;
795 fs->state.tokens = tgsi_dup_tokens(shader->tokens);
796
797 return (void*)fs;
798 }
799
800 void r300_mark_fs_code_dirty(struct r300_context *r300)
801 {
802 struct r300_fragment_shader* fs = r300_fs(r300);
803
804 r300->fs.dirty = TRUE;
805 r300->fs_rc_constant_state.dirty = TRUE;
806 r300->fs_constants.dirty = TRUE;
807 r300->fs.size = fs->shader->cb_code_size;
808
809 if (r300->screen->caps.is_r500) {
810 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7;
811 r300->fs_constants.size = fs->shader->externals_count * 4 + 3;
812 } else {
813 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5;
814 r300->fs_constants.size = fs->shader->externals_count * 4 + 1;
815 }
816 }
817
818 /* Bind fragment shader state. */
819 static void r300_bind_fs_state(struct pipe_context* pipe, void* shader)
820 {
821 struct r300_context* r300 = r300_context(pipe);
822 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
823
824 if (fs == NULL) {
825 r300->fs.state = NULL;
826 return;
827 }
828
829 r300->fs.state = fs;
830 r300_pick_fragment_shader(r300);
831 r300_mark_fs_code_dirty(r300);
832
833 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */
834 }
835
836 /* Delete fragment shader state. */
837 static void r300_delete_fs_state(struct pipe_context* pipe, void* shader)
838 {
839 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
840 struct r300_fragment_shader_code *tmp, *ptr = fs->first;
841
842 while (ptr) {
843 tmp = ptr;
844 ptr = ptr->next;
845 rc_constants_destroy(&tmp->code.constants);
846 FREE(tmp->cb_code);
847 FREE(tmp);
848 }
849 FREE((void*)fs->state.tokens);
850 FREE(shader);
851 }
852
853 static void r300_set_polygon_stipple(struct pipe_context* pipe,
854 const struct pipe_poly_stipple* state)
855 {
856 /* XXX no idea how to set this up, but not terribly important */
857 }
858
859 /* Create a new rasterizer state based on the CSO rasterizer state.
860 *
861 * This is a very large chunk of state, and covers most of the graphics
862 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
863 *
864 * In a not entirely unironic sidenote, this state has nearly nothing to do
865 * with the actual block on the Radeon called the rasterizer (RS). */
866 static void* r300_create_rs_state(struct pipe_context* pipe,
867 const struct pipe_rasterizer_state* state)
868 {
869 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state);
870 int i;
871 float psiz;
872 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */
873 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */
874 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */
875 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */
876 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */
877 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */
878 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */
879 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */
880 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */
881 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */
882
883 /* Specifies top of Raster pipe specific enable controls,
884 * i.e. texture coordinates stuffing for points, lines, triangles */
885 uint32_t stuffing_enable; /* R300_GB_ENABLE: 0x4008 */
886
887 /* Point sprites texture coordinates, 0: lower left, 1: upper right */
888 float point_texcoord_left; /* R300_GA_POINT_S0: 0x4200 */
889 float point_texcoord_bottom; /* R300_GA_POINT_T0: 0x4204 */
890 float point_texcoord_right; /* R300_GA_POINT_S1: 0x4208 */
891 float point_texcoord_top; /* R300_GA_POINT_T1: 0x420c */
892 CB_LOCALS;
893
894 /* Copy rasterizer state. */
895 rs->rs = *state;
896 rs->rs_draw = *state;
897
898 /* Override some states for Draw. */
899 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */
900
901 #ifdef PIPE_ARCH_LITTLE_ENDIAN
902 vap_control_status = R300_VC_NO_SWAP;
903 #else
904 vap_control_status = R300_VC_32BIT_SWAP;
905 #endif
906
907 /* If no TCL engine is present, turn off the HW TCL. */
908 if (!r300_screen(pipe->screen)->caps.has_tcl) {
909 vap_control_status |= R300_VAP_TCL_BYPASS;
910 }
911
912 /* Point size width and height. */
913 point_size =
914 pack_float_16_6x(state->point_size) |
915 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT);
916
917 /* Point size clamping. */
918 if (state->point_size_per_vertex) {
919 /* Per-vertex point size.
920 * Clamp to [0, max FB size] */
921 psiz = pipe->screen->get_paramf(pipe->screen,
922 PIPE_CAP_MAX_POINT_WIDTH);
923 point_minmax =
924 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT;
925 } else {
926 /* We cannot disable the point-size vertex output,
927 * so clamp it. */
928 psiz = state->point_size;
929 point_minmax =
930 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) |
931 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT);
932 }
933
934 /* Line control. */
935 line_control = pack_float_16_6x(state->line_width) |
936 R300_GA_LINE_CNTL_END_TYPE_COMP;
937
938 /* Enable polygon mode */
939 polygon_mode = 0;
940 if (state->fill_front != PIPE_POLYGON_MODE_FILL ||
941 state->fill_back != PIPE_POLYGON_MODE_FILL) {
942 polygon_mode = R300_GA_POLY_MODE_DUAL;
943 }
944
945 /* Front face */
946 if (state->front_ccw)
947 cull_mode = R300_FRONT_FACE_CCW;
948 else
949 cull_mode = R300_FRONT_FACE_CW;
950
951 /* Polygon offset */
952 polygon_offset_enable = 0;
953 if (util_get_offset(state, state->fill_front)) {
954 polygon_offset_enable |= R300_FRONT_ENABLE;
955 }
956 if (util_get_offset(state, state->fill_back)) {
957 polygon_offset_enable |= R300_BACK_ENABLE;
958 }
959
960 rs->polygon_offset_enable = polygon_offset_enable != 0;
961
962 /* Polygon mode */
963 if (polygon_mode) {
964 polygon_mode |=
965 r300_translate_polygon_mode_front(state->fill_front);
966 polygon_mode |=
967 r300_translate_polygon_mode_back(state->fill_back);
968 }
969
970 if (state->cull_face & PIPE_FACE_FRONT) {
971 cull_mode |= R300_CULL_FRONT;
972 }
973 if (state->cull_face & PIPE_FACE_BACK) {
974 cull_mode |= R300_CULL_BACK;
975 }
976
977 if (state->line_stipple_enable) {
978 line_stipple_config =
979 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE |
980 (fui((float)state->line_stipple_factor) &
981 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK);
982 /* XXX this might need to be scaled up */
983 line_stipple_value = state->line_stipple_pattern;
984 }
985
986 if (state->flatshade) {
987 rs->color_control = R300_SHADE_MODEL_FLAT;
988 } else {
989 rs->color_control = R300_SHADE_MODEL_SMOOTH;
990 }
991
992 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
993
994 /* Point sprites */
995 stuffing_enable = 0;
996 if (state->sprite_coord_enable) {
997 stuffing_enable = R300_GB_POINT_STUFF_ENABLE;
998 for (i = 0; i < 8; i++) {
999 if (state->sprite_coord_enable & (1 << i))
1000 stuffing_enable |=
1001 R300_GB_TEX_STR << (R300_GB_TEX0_SOURCE_SHIFT + (i*2));
1002 }
1003
1004 point_texcoord_left = 0.0f;
1005 point_texcoord_right = 1.0f;
1006
1007 switch (state->sprite_coord_mode) {
1008 case PIPE_SPRITE_COORD_UPPER_LEFT:
1009 point_texcoord_top = 0.0f;
1010 point_texcoord_bottom = 1.0f;
1011 break;
1012 case PIPE_SPRITE_COORD_LOWER_LEFT:
1013 point_texcoord_top = 1.0f;
1014 point_texcoord_bottom = 0.0f;
1015 break;
1016 }
1017 }
1018
1019 /* Build the main command buffer. */
1020 BEGIN_CB(rs->cb_main, 25);
1021 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status);
1022 OUT_CB_REG(R300_GA_POINT_SIZE, point_size);
1023 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2);
1024 OUT_CB(point_minmax);
1025 OUT_CB(line_control);
1026 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
1027 OUT_CB(polygon_offset_enable);
1028 rs->cull_mode_index = 25 - cs_count;
1029 OUT_CB(cull_mode);
1030 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config);
1031 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value);
1032 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode);
1033 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule);
1034 OUT_CB_REG(R300_GB_ENABLE, stuffing_enable);
1035 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4);
1036 OUT_CB_32F(point_texcoord_left);
1037 OUT_CB_32F(point_texcoord_bottom);
1038 OUT_CB_32F(point_texcoord_right);
1039 OUT_CB_32F(point_texcoord_top);
1040 END_CB;
1041
1042 /* Build the two command buffers for polygon offset setup. */
1043 if (polygon_offset_enable) {
1044 float scale = state->offset_scale * 12;
1045 float offset = state->offset_units * 4;
1046
1047 BEGIN_CB(rs->cb_poly_offset_zb16, 5);
1048 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1049 OUT_CB_32F(scale);
1050 OUT_CB_32F(offset);
1051 OUT_CB_32F(scale);
1052 OUT_CB_32F(offset);
1053 END_CB;
1054
1055 offset = state->offset_units * 2;
1056
1057 BEGIN_CB(rs->cb_poly_offset_zb24, 5);
1058 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1059 OUT_CB_32F(scale);
1060 OUT_CB_32F(offset);
1061 OUT_CB_32F(scale);
1062 OUT_CB_32F(offset);
1063 END_CB;
1064 }
1065
1066 return (void*)rs;
1067 }
1068
1069 /* Bind rasterizer state. */
1070 static void r300_bind_rs_state(struct pipe_context* pipe, void* state)
1071 {
1072 struct r300_context* r300 = r300_context(pipe);
1073 struct r300_rs_state* rs = (struct r300_rs_state*)state;
1074 int last_sprite_coord_enable = r300->sprite_coord_enable;
1075 boolean last_two_sided_color = r300->two_sided_color;
1076
1077 if (r300->draw && rs) {
1078 draw_flush(r300->draw);
1079 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state);
1080 }
1081
1082 if (rs) {
1083 r300->polygon_offset_enabled = (rs->rs.offset_point ||
1084 rs->rs.offset_line ||
1085 rs->rs.offset_tri);
1086 r300->sprite_coord_enable = rs->rs.sprite_coord_enable;
1087 r300->two_sided_color = rs->rs.light_twoside;
1088 } else {
1089 r300->polygon_offset_enabled = FALSE;
1090 r300->sprite_coord_enable = 0;
1091 r300->two_sided_color = FALSE;
1092 }
1093
1094 UPDATE_STATE(state, r300->rs_state);
1095 r300->rs_state.size = 25 + (r300->polygon_offset_enabled ? 5 : 0);
1096
1097 if (last_sprite_coord_enable != r300->sprite_coord_enable ||
1098 last_two_sided_color != r300->two_sided_color) {
1099 r300->rs_block_state.dirty = TRUE;
1100 }
1101 }
1102
1103 /* Free rasterizer state. */
1104 static void r300_delete_rs_state(struct pipe_context* pipe, void* state)
1105 {
1106 FREE(state);
1107 }
1108
1109 static void*
1110 r300_create_sampler_state(struct pipe_context* pipe,
1111 const struct pipe_sampler_state* state)
1112 {
1113 struct r300_context* r300 = r300_context(pipe);
1114 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
1115 boolean is_r500 = r300->screen->caps.is_r500;
1116 int lod_bias;
1117 union util_color uc;
1118
1119 sampler->state = *state;
1120
1121 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG
1122 * or MIN filter is NEAREST. Since texwrap produces same results
1123 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */
1124 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST ||
1125 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) {
1126 /* Wrap S. */
1127 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP)
1128 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1129 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP)
1130 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1131
1132 /* Wrap T. */
1133 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP)
1134 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1135 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP)
1136 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1137
1138 /* Wrap R. */
1139 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP)
1140 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1141 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP)
1142 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1143 }
1144
1145 sampler->filter0 |=
1146 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) |
1147 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) |
1148 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT);
1149
1150 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter,
1151 state->mag_img_filter,
1152 state->min_mip_filter,
1153 state->max_anisotropy > 0);
1154
1155 sampler->filter0 |= r300_anisotropy(state->max_anisotropy);
1156
1157 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */
1158 /* We must pass these to the merge function to clamp them properly. */
1159 sampler->min_lod = MAX2((unsigned)state->min_lod, 0);
1160 sampler->max_lod = MAX2((unsigned)ceilf(state->max_lod), 0);
1161
1162 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1);
1163
1164 sampler->filter1 |= lod_bias << R300_LOD_BIAS_SHIFT;
1165
1166 /* This is very high quality anisotropic filtering for R5xx.
1167 * It's good for benchmarking the performance of texturing but
1168 * in practice we don't want to slow down the driver because it's
1169 * a pretty good performance killer. Feel free to play with it. */
1170 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) {
1171 sampler->filter1 |= r500_anisotropy(state->max_anisotropy);
1172 }
1173
1174 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1175 sampler->border_color = uc.ui;
1176
1177 /* R500-specific fixups and optimizations */
1178 if (r300->screen->caps.is_r500) {
1179 sampler->filter1 |= R500_BORDER_FIX;
1180 }
1181
1182 return (void*)sampler;
1183 }
1184
1185 static void r300_bind_sampler_states(struct pipe_context* pipe,
1186 unsigned count,
1187 void** states)
1188 {
1189 struct r300_context* r300 = r300_context(pipe);
1190 struct r300_textures_state* state =
1191 (struct r300_textures_state*)r300->textures_state.state;
1192 unsigned tex_units = r300->screen->caps.num_tex_units;
1193
1194 if (count > tex_units) {
1195 return;
1196 }
1197
1198 memcpy(state->sampler_states, states, sizeof(void*) * count);
1199 state->sampler_state_count = count;
1200
1201 r300->textures_state.dirty = TRUE;
1202 }
1203
1204 static void r300_lacks_vertex_textures(struct pipe_context* pipe,
1205 unsigned count,
1206 void** states)
1207 {
1208 }
1209
1210 static void r300_delete_sampler_state(struct pipe_context* pipe, void* state)
1211 {
1212 FREE(state);
1213 }
1214
1215 static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num)
1216 {
1217 /* This looks like a hack, but I believe it's suppose to work like
1218 * that. To illustrate how this works, let's assume you have 5 textures.
1219 * From docs, 5 and the successive numbers are:
1220 *
1221 * FOURTH_1 = 5
1222 * FOURTH_2 = 6
1223 * FOURTH_3 = 7
1224 * EIGHTH_0 = 8
1225 * EIGHTH_1 = 9
1226 *
1227 * First 3 textures will get 3/4 of size of the cache, divived evenly
1228 * between them. The last 1/4 of the cache must be divided between
1229 * the last 2 textures, each will therefore get 1/8 of the cache.
1230 * Why not just to use "5 + texture_index" ?
1231 *
1232 * This simple trick works for all "num" <= 16.
1233 */
1234 if (num <= 1)
1235 return R300_TX_CACHE(R300_TX_CACHE_WHOLE);
1236 else
1237 return R300_TX_CACHE(num + index);
1238 }
1239
1240 static void r300_set_fragment_sampler_views(struct pipe_context* pipe,
1241 unsigned count,
1242 struct pipe_sampler_view** views)
1243 {
1244 struct r300_context* r300 = r300_context(pipe);
1245 struct r300_textures_state* state =
1246 (struct r300_textures_state*)r300->textures_state.state;
1247 struct r300_texture *texture;
1248 unsigned i, real_num_views = 0, view_index = 0;
1249 unsigned tex_units = r300->screen->caps.num_tex_units;
1250 boolean dirty_tex = FALSE;
1251
1252 if (count > tex_units) {
1253 return;
1254 }
1255
1256 /* Calculate the real number of views. */
1257 for (i = 0; i < count; i++) {
1258 if (views[i])
1259 real_num_views++;
1260 }
1261
1262 for (i = 0; i < count; i++) {
1263 if (&state->sampler_views[i]->base != views[i]) {
1264 pipe_sampler_view_reference(
1265 (struct pipe_sampler_view**)&state->sampler_views[i],
1266 views[i]);
1267
1268 if (!views[i]) {
1269 continue;
1270 }
1271
1272 /* A new sampler view (= texture)... */
1273 dirty_tex = TRUE;
1274
1275 /* Set the texrect factor in the fragment shader.
1276 * Needed for RECT and NPOT fallback. */
1277 texture = r300_texture(views[i]->texture);
1278 if (texture->uses_pitch) {
1279 r300->fs_rc_constant_state.dirty = TRUE;
1280 }
1281
1282 state->sampler_views[i]->texcache_region =
1283 r300_assign_texture_cache_region(view_index, real_num_views);
1284 view_index++;
1285 }
1286 }
1287
1288 for (i = count; i < tex_units; i++) {
1289 if (state->sampler_views[i]) {
1290 pipe_sampler_view_reference(
1291 (struct pipe_sampler_view**)&state->sampler_views[i],
1292 NULL);
1293 }
1294 }
1295
1296 state->sampler_view_count = count;
1297
1298 r300->textures_state.dirty = TRUE;
1299
1300 if (dirty_tex) {
1301 r300->texture_cache_inval.dirty = TRUE;
1302 }
1303 }
1304
1305 static struct pipe_sampler_view *
1306 r300_create_sampler_view(struct pipe_context *pipe,
1307 struct pipe_resource *texture,
1308 const struct pipe_sampler_view *templ)
1309 {
1310 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view);
1311 struct r300_texture *tex = r300_texture(texture);
1312
1313 if (view) {
1314 view->base = *templ;
1315 view->base.reference.count = 1;
1316 view->base.context = pipe;
1317 view->base.texture = NULL;
1318 pipe_resource_reference(&view->base.texture, texture);
1319
1320 view->swizzle[0] = templ->swizzle_r;
1321 view->swizzle[1] = templ->swizzle_g;
1322 view->swizzle[2] = templ->swizzle_b;
1323 view->swizzle[3] = templ->swizzle_a;
1324
1325 view->format = tex->tx_format;
1326 view->format.format1 |= r300_translate_texformat(templ->format,
1327 view->swizzle);
1328 if (r300_screen(pipe->screen)->caps.is_r500) {
1329 view->format.format2 |= r500_tx_format_msb_bit(templ->format);
1330 }
1331 }
1332
1333 return (struct pipe_sampler_view*)view;
1334 }
1335
1336 static void
1337 r300_sampler_view_destroy(struct pipe_context *pipe,
1338 struct pipe_sampler_view *view)
1339 {
1340 pipe_resource_reference(&view->texture, NULL);
1341 FREE(view);
1342 }
1343
1344 static void r300_set_scissor_state(struct pipe_context* pipe,
1345 const struct pipe_scissor_state* state)
1346 {
1347 struct r300_context* r300 = r300_context(pipe);
1348
1349 memcpy(r300->scissor_state.state, state,
1350 sizeof(struct pipe_scissor_state));
1351
1352 r300->scissor_state.dirty = TRUE;
1353 }
1354
1355 static void r300_set_viewport_state(struct pipe_context* pipe,
1356 const struct pipe_viewport_state* state)
1357 {
1358 struct r300_context* r300 = r300_context(pipe);
1359 struct r300_viewport_state* viewport =
1360 (struct r300_viewport_state*)r300->viewport_state.state;
1361
1362 r300->viewport = *state;
1363
1364 if (r300->draw) {
1365 draw_flush(r300->draw);
1366 draw_set_viewport_state(r300->draw, state);
1367 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT;
1368 return;
1369 }
1370
1371 /* Do the transform in HW. */
1372 viewport->vte_control = R300_VTX_W0_FMT;
1373
1374 if (state->scale[0] != 1.0f) {
1375 viewport->xscale = state->scale[0];
1376 viewport->vte_control |= R300_VPORT_X_SCALE_ENA;
1377 }
1378 if (state->scale[1] != 1.0f) {
1379 viewport->yscale = state->scale[1];
1380 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA;
1381 }
1382 if (state->scale[2] != 1.0f) {
1383 viewport->zscale = state->scale[2];
1384 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA;
1385 }
1386 if (state->translate[0] != 0.0f) {
1387 viewport->xoffset = state->translate[0];
1388 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA;
1389 }
1390 if (state->translate[1] != 0.0f) {
1391 viewport->yoffset = state->translate[1];
1392 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA;
1393 }
1394 if (state->translate[2] != 0.0f) {
1395 viewport->zoffset = state->translate[2];
1396 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA;
1397 }
1398
1399 r300->viewport_state.dirty = TRUE;
1400 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) {
1401 r300->fs_rc_constant_state.dirty = TRUE;
1402 }
1403 }
1404
1405 static void r300_set_vertex_buffers(struct pipe_context* pipe,
1406 unsigned count,
1407 const struct pipe_vertex_buffer* buffers)
1408 {
1409 struct r300_context* r300 = r300_context(pipe);
1410 struct pipe_vertex_buffer *vbo;
1411 unsigned i, max_index = (1 << 24) - 1;
1412 boolean any_user_buffer = FALSE;
1413
1414 if (count == r300->vertex_buffer_count &&
1415 memcmp(r300->vertex_buffer, buffers,
1416 sizeof(struct pipe_vertex_buffer) * count) == 0) {
1417 return;
1418 }
1419
1420 if (r300->screen->caps.has_tcl) {
1421 /* HW TCL. */
1422 r300->incompatible_vb_layout = FALSE;
1423
1424 /* Check if the strides and offsets are aligned to the size of DWORD. */
1425 for (i = 0; i < count; i++) {
1426 if (buffers[i].buffer) {
1427 if (buffers[i].stride % 4 != 0 ||
1428 buffers[i].buffer_offset % 4 != 0) {
1429 r300->incompatible_vb_layout = TRUE;
1430 break;
1431 }
1432 }
1433 }
1434
1435 for (i = 0; i < count; i++) {
1436 /* Why, yes, I AM casting away constness. How did you know? */
1437 vbo = (struct pipe_vertex_buffer*)&buffers[i];
1438
1439 /* Skip NULL buffers */
1440 if (!buffers[i].buffer) {
1441 continue;
1442 }
1443
1444 if (r300_buffer_is_user_buffer(vbo->buffer)) {
1445 any_user_buffer = TRUE;
1446 }
1447
1448 if (vbo->max_index == ~0) {
1449 /* if no VBO stride then only one vertex value so max index is 1 */
1450 /* should think about converting to VS constants like svga does */
1451 if (!vbo->stride)
1452 vbo->max_index = 1;
1453 else
1454 vbo->max_index =
1455 (vbo->buffer->width0 - vbo->buffer_offset) / vbo->stride;
1456 }
1457
1458 max_index = MIN2(vbo->max_index, max_index);
1459 }
1460
1461 r300->any_user_vbs = any_user_buffer;
1462 r300->vertex_buffer_max_index = max_index;
1463
1464 } else {
1465 /* SW TCL. */
1466 draw_flush(r300->draw);
1467 draw_set_vertex_buffers(r300->draw, count, buffers);
1468 }
1469
1470 /* Common code. */
1471 for (i = 0; i < count; i++) {
1472 /* Reference our buffer. */
1473 pipe_resource_reference(&r300->vertex_buffer[i].buffer, buffers[i].buffer);
1474 }
1475 for (; i < r300->vertex_buffer_count; i++) {
1476 /* Dereference any old buffers. */
1477 pipe_resource_reference(&r300->vertex_buffer[i].buffer, NULL);
1478 }
1479
1480 memcpy(r300->vertex_buffer, buffers,
1481 sizeof(struct pipe_vertex_buffer) * count);
1482 r300->vertex_buffer_count = count;
1483 }
1484
1485 /* Initialize the PSC tables. */
1486 static void r300_vertex_psc(struct r300_vertex_element_state *velems)
1487 {
1488 struct r300_vertex_stream_state *vstream = &velems->vertex_stream;
1489 uint16_t type, swizzle;
1490 enum pipe_format format;
1491 unsigned i;
1492
1493 if (velems->count > 16) {
1494 fprintf(stderr, "r300: More than 16 vertex elements are not supported,"
1495 " requested %i, using 16.\n", velems->count);
1496 velems->count = 16;
1497 }
1498
1499 /* Vertex shaders have no semantics on their inputs,
1500 * so PSC should just route stuff based on the vertex elements,
1501 * and not on attrib information. */
1502 for (i = 0; i < velems->count; i++) {
1503 format = velems->hw_format[i];
1504
1505 type = r300_translate_vertex_data_type(format);
1506 if (type == R300_INVALID_FORMAT) {
1507 fprintf(stderr, "r300: Bad vertex format %s.\n",
1508 util_format_short_name(format));
1509 assert(0);
1510 abort();
1511 }
1512
1513 type |= i << R300_DST_VEC_LOC_SHIFT;
1514 swizzle = r300_translate_vertex_data_swizzle(format);
1515
1516 if (i & 1) {
1517 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16;
1518 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16;
1519 } else {
1520 vstream->vap_prog_stream_cntl[i >> 1] |= type;
1521 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle;
1522 }
1523 }
1524
1525 /* Set the last vector in the PSC. */
1526 if (i) {
1527 i -= 1;
1528 }
1529 vstream->vap_prog_stream_cntl[i >> 1] |=
1530 (R300_LAST_VEC << (i & 1 ? 16 : 0));
1531
1532 vstream->count = (i >> 1) + 1;
1533 }
1534
1535 #define FORMAT_REPLACE(what, withwhat) \
1536 case PIPE_FORMAT_##what: *format = PIPE_FORMAT_##withwhat; break
1537
1538 static void* r300_create_vertex_elements_state(struct pipe_context* pipe,
1539 unsigned count,
1540 const struct pipe_vertex_element* attribs)
1541 {
1542 struct r300_vertex_element_state *velems;
1543 unsigned i;
1544 enum pipe_format *format;
1545
1546 assert(count <= PIPE_MAX_ATTRIBS);
1547 velems = CALLOC_STRUCT(r300_vertex_element_state);
1548 if (velems != NULL) {
1549 velems->count = count;
1550 memcpy(velems->velem, attribs, sizeof(struct pipe_vertex_element) * count);
1551
1552 if (r300_screen(pipe->screen)->caps.has_tcl) {
1553 /* Set the best hw format in case the original format is not
1554 * supported by hw. */
1555 for (i = 0; i < count; i++) {
1556 velems->hw_format[i] = velems->velem[i].src_format;
1557 format = &velems->hw_format[i];
1558
1559 /* This is basically the list of unsupported formats.
1560 * For now we don't care about the alignment, that's going to
1561 * be sorted out after the PSC setup. */
1562 switch (*format) {
1563 FORMAT_REPLACE(R64_FLOAT, R32_FLOAT);
1564 FORMAT_REPLACE(R64G64_FLOAT, R32G32_FLOAT);
1565 FORMAT_REPLACE(R64G64B64_FLOAT, R32G32B32_FLOAT);
1566 FORMAT_REPLACE(R64G64B64A64_FLOAT, R32G32B32A32_FLOAT);
1567
1568 FORMAT_REPLACE(R32_UNORM, R32_FLOAT);
1569 FORMAT_REPLACE(R32G32_UNORM, R32G32_FLOAT);
1570 FORMAT_REPLACE(R32G32B32_UNORM, R32G32B32_FLOAT);
1571 FORMAT_REPLACE(R32G32B32A32_UNORM, R32G32B32A32_FLOAT);
1572
1573 FORMAT_REPLACE(R32_USCALED, R32_FLOAT);
1574 FORMAT_REPLACE(R32G32_USCALED, R32G32_FLOAT);
1575 FORMAT_REPLACE(R32G32B32_USCALED, R32G32B32_FLOAT);
1576 FORMAT_REPLACE(R32G32B32A32_USCALED,R32G32B32A32_FLOAT);
1577
1578 FORMAT_REPLACE(R32_SNORM, R32_FLOAT);
1579 FORMAT_REPLACE(R32G32_SNORM, R32G32_FLOAT);
1580 FORMAT_REPLACE(R32G32B32_SNORM, R32G32B32_FLOAT);
1581 FORMAT_REPLACE(R32G32B32A32_SNORM, R32G32B32A32_FLOAT);
1582
1583 FORMAT_REPLACE(R32_SSCALED, R32_FLOAT);
1584 FORMAT_REPLACE(R32G32_SSCALED, R32G32_FLOAT);
1585 FORMAT_REPLACE(R32G32B32_SSCALED, R32G32B32_FLOAT);
1586 FORMAT_REPLACE(R32G32B32A32_SSCALED,R32G32B32A32_FLOAT);
1587
1588 FORMAT_REPLACE(R32_FIXED, R32_FLOAT);
1589 FORMAT_REPLACE(R32G32_FIXED, R32G32_FLOAT);
1590 FORMAT_REPLACE(R32G32B32_FIXED, R32G32B32_FLOAT);
1591 FORMAT_REPLACE(R32G32B32A32_FIXED, R32G32B32A32_FLOAT);
1592
1593 default:;
1594 }
1595
1596 velems->incompatible_layout =
1597 velems->incompatible_layout ||
1598 velems->velem[i].src_format != velems->hw_format[i] ||
1599 velems->velem[i].src_offset % 4 != 0;
1600 }
1601
1602 /* Now setup PSC.
1603 * The unused components will be replaced by (..., 0, 1). */
1604 r300_vertex_psc(velems);
1605
1606 /* Align the formats to the size of DWORD.
1607 * We only care about the blocksizes of the formats since
1608 * swizzles are already set up.
1609 * Also compute the vertex size. */
1610 for (i = 0; i < count; i++) {
1611 /* This is OK because we check for aligned strides too. */
1612 velems->hw_format_size[i] =
1613 align(util_format_get_blocksize(velems->hw_format[i]), 4);
1614 velems->vertex_size_dwords += velems->hw_format_size[i] / 4;
1615 }
1616 }
1617 }
1618 return velems;
1619 }
1620
1621 static void r300_bind_vertex_elements_state(struct pipe_context *pipe,
1622 void *state)
1623 {
1624 struct r300_context *r300 = r300_context(pipe);
1625 struct r300_vertex_element_state *velems = state;
1626
1627 if (velems == NULL) {
1628 return;
1629 }
1630
1631 r300->velems = velems;
1632
1633 if (r300->draw) {
1634 draw_flush(r300->draw);
1635 draw_set_vertex_elements(r300->draw, velems->count, velems->velem);
1636 return;
1637 }
1638
1639 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state);
1640 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2;
1641 }
1642
1643 static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state)
1644 {
1645 FREE(state);
1646 }
1647
1648 static void* r300_create_vs_state(struct pipe_context* pipe,
1649 const struct pipe_shader_state* shader)
1650 {
1651 struct r300_context* r300 = r300_context(pipe);
1652 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader);
1653
1654 /* Copy state directly into shader. */
1655 vs->state = *shader;
1656 vs->state.tokens = tgsi_dup_tokens(shader->tokens);
1657
1658 if (r300->screen->caps.has_tcl) {
1659 r300_init_vs_outputs(vs);
1660 r300_translate_vertex_shader(r300, vs);
1661 } else {
1662 r300_draw_init_vertex_shader(r300->draw, vs);
1663 }
1664
1665 return vs;
1666 }
1667
1668 static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
1669 {
1670 struct r300_context* r300 = r300_context(pipe);
1671 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1672
1673 if (vs == NULL) {
1674 r300->vs_state.state = NULL;
1675 return;
1676 }
1677 if (vs == r300->vs_state.state) {
1678 return;
1679 }
1680 r300->vs_state.state = vs;
1681
1682 /* The majority of the RS block bits is dependent on the vertex shader. */
1683 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */
1684
1685 if (r300->screen->caps.has_tcl) {
1686 r300->vs_state.dirty = TRUE;
1687 r300->vs_state.size =
1688 vs->code.length + 9 +
1689 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0);
1690
1691 if (vs->externals_count) {
1692 r300->vs_constants.dirty = TRUE;
1693 r300->vs_constants.size = vs->externals_count * 4 + 3;
1694 } else {
1695 r300->vs_constants.size = 0;
1696 }
1697
1698 r300->pvs_flush.dirty = TRUE;
1699 } else {
1700 draw_flush(r300->draw);
1701 draw_bind_vertex_shader(r300->draw,
1702 (struct draw_vertex_shader*)vs->draw_vs);
1703 }
1704 }
1705
1706 static void r300_delete_vs_state(struct pipe_context* pipe, void* shader)
1707 {
1708 struct r300_context* r300 = r300_context(pipe);
1709 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1710
1711 if (r300->screen->caps.has_tcl) {
1712 rc_constants_destroy(&vs->code.constants);
1713 } else {
1714 draw_delete_vertex_shader(r300->draw,
1715 (struct draw_vertex_shader*)vs->draw_vs);
1716 }
1717
1718 FREE((void*)vs->state.tokens);
1719 FREE(shader);
1720 }
1721
1722 static void r300_set_constant_buffer(struct pipe_context *pipe,
1723 uint shader, uint index,
1724 struct pipe_resource *buf)
1725 {
1726 struct r300_context* r300 = r300_context(pipe);
1727 struct r300_constant_buffer *cbuf;
1728 struct pipe_transfer *tr;
1729 float *mapped;
1730 int max_size = 0, max_size_bytes = 0, clamped_size = 0;
1731
1732 switch (shader) {
1733 case PIPE_SHADER_VERTEX:
1734 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state;
1735 max_size = 256;
1736 break;
1737 case PIPE_SHADER_FRAGMENT:
1738 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state;
1739 if (r300->screen->caps.is_r500) {
1740 max_size = 256;
1741 } else {
1742 max_size = 32;
1743 }
1744 break;
1745 default:
1746 assert(0);
1747 return;
1748 }
1749 max_size_bytes = max_size * 4 * sizeof(float);
1750
1751 if (buf == NULL || buf->width0 == 0 ||
1752 (mapped = pipe_buffer_map(pipe, buf, PIPE_TRANSFER_READ, &tr)) == NULL)
1753 {
1754 cbuf->count = 0;
1755 return;
1756 }
1757
1758 if (shader == PIPE_SHADER_FRAGMENT ||
1759 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) {
1760 assert((buf->width0 % (4 * sizeof(float))) == 0);
1761
1762 /* Check the size of the constant buffer. */
1763 /* XXX Subtract immediates and RC_STATE_* variables. */
1764 if (buf->width0 > max_size_bytes) {
1765 fprintf(stderr, "r300: Max size of the constant buffer is "
1766 "%i*4 floats.\n", max_size);
1767 }
1768
1769 clamped_size = MIN2(buf->width0, max_size_bytes);
1770 cbuf->count = clamped_size / (4 * sizeof(float));
1771
1772 if (shader == PIPE_SHADER_FRAGMENT && !r300->screen->caps.is_r500) {
1773 unsigned i,j;
1774
1775 /* Convert constants to float24. */
1776 for (i = 0; i < cbuf->count; i++)
1777 for (j = 0; j < 4; j++)
1778 cbuf->constants[i][j] = pack_float24(mapped[i*4+j]);
1779 } else {
1780 memcpy(cbuf->constants, mapped, clamped_size);
1781 }
1782 }
1783
1784 if (shader == PIPE_SHADER_VERTEX) {
1785 if (r300->screen->caps.has_tcl) {
1786 if (r300->vs_constants.size) {
1787 r300->vs_constants.dirty = TRUE;
1788 }
1789 r300->pvs_flush.dirty = TRUE;
1790 } else if (r300->draw) {
1791 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX,
1792 0, mapped, buf->width0);
1793 }
1794 } else if (shader == PIPE_SHADER_FRAGMENT) {
1795 r300->fs_constants.dirty = TRUE;
1796 }
1797
1798 pipe_buffer_unmap(pipe, buf, tr);
1799 }
1800
1801 void r300_init_state_functions(struct r300_context* r300)
1802 {
1803 r300->context.create_blend_state = r300_create_blend_state;
1804 r300->context.bind_blend_state = r300_bind_blend_state;
1805 r300->context.delete_blend_state = r300_delete_blend_state;
1806
1807 r300->context.set_blend_color = r300_set_blend_color;
1808
1809 r300->context.set_clip_state = r300_set_clip_state;
1810 r300->context.set_sample_mask = r300_set_sample_mask;
1811
1812 r300->context.set_constant_buffer = r300_set_constant_buffer;
1813
1814 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state;
1815 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
1816 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
1817
1818 r300->context.set_stencil_ref = r300_set_stencil_ref;
1819
1820 r300->context.set_framebuffer_state = r300_set_framebuffer_state;
1821
1822 r300->context.create_fs_state = r300_create_fs_state;
1823 r300->context.bind_fs_state = r300_bind_fs_state;
1824 r300->context.delete_fs_state = r300_delete_fs_state;
1825
1826 r300->context.set_polygon_stipple = r300_set_polygon_stipple;
1827
1828 r300->context.create_rasterizer_state = r300_create_rs_state;
1829 r300->context.bind_rasterizer_state = r300_bind_rs_state;
1830 r300->context.delete_rasterizer_state = r300_delete_rs_state;
1831
1832 r300->context.create_sampler_state = r300_create_sampler_state;
1833 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states;
1834 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures;
1835 r300->context.delete_sampler_state = r300_delete_sampler_state;
1836
1837 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views;
1838 r300->context.create_sampler_view = r300_create_sampler_view;
1839 r300->context.sampler_view_destroy = r300_sampler_view_destroy;
1840
1841 r300->context.set_scissor_state = r300_set_scissor_state;
1842
1843 r300->context.set_viewport_state = r300_set_viewport_state;
1844
1845 r300->context.set_vertex_buffers = r300_set_vertex_buffers;
1846
1847 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state;
1848 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state;
1849 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state;
1850
1851 r300->context.create_vs_state = r300_create_vs_state;
1852 r300->context.bind_vs_state = r300_bind_vs_state;
1853 r300->context.delete_vs_state = r300_delete_vs_state;
1854 }