b0722cb95f694a51e13088673a44709ba297fc9b
[mesa.git] / src / gallium / drivers / r300 / r300_state.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "draw/draw_context.h"
25
26 #include "util/u_blitter.h"
27 #include "util/u_math.h"
28 #include "util/u_memory.h"
29 #include "util/u_pack_color.h"
30
31 #include "tgsi/tgsi_parse.h"
32
33 #include "pipe/p_config.h"
34
35 #include "r300_cb.h"
36 #include "r300_context.h"
37 #include "r300_emit.h"
38 #include "r300_reg.h"
39 #include "r300_screen.h"
40 #include "r300_screen_buffer.h"
41 #include "r300_state_inlines.h"
42 #include "r300_fs.h"
43 #include "r300_texture.h"
44 #include "r300_vs.h"
45 #include "r300_winsys.h"
46
47 /* r300_state: Functions used to intialize state context by translating
48 * Gallium state objects into semi-native r300 state objects. */
49
50 #define UPDATE_STATE(cso, atom) \
51 if (cso != atom.state) { \
52 atom.state = cso; \
53 atom.dirty = TRUE; \
54 }
55
56 static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA,
57 unsigned dstRGB, unsigned dstA)
58 {
59 /* If the blend equation is ADD or REVERSE_SUBTRACT,
60 * SRC_ALPHA == 0, and the following state is set, the colorbuffer
61 * will not be changed.
62 * Notice that the dst factors are the src factors inverted. */
63 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
64 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
65 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
66 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
67 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
68 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
69 srcA == PIPE_BLENDFACTOR_ZERO) &&
70 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
71 dstRGB == PIPE_BLENDFACTOR_ONE) &&
72 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
73 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
74 dstA == PIPE_BLENDFACTOR_ONE);
75 }
76
77 static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA,
78 unsigned dstRGB, unsigned dstA)
79 {
80 /* If the blend equation is ADD or REVERSE_SUBTRACT,
81 * SRC_ALPHA == 1, and the following state is set, the colorbuffer
82 * will not be changed.
83 * Notice that the dst factors are the src factors inverted. */
84 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
85 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
86 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
87 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
88 srcA == PIPE_BLENDFACTOR_ZERO) &&
89 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
90 dstRGB == PIPE_BLENDFACTOR_ONE) &&
91 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
92 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
93 dstA == PIPE_BLENDFACTOR_ONE);
94 }
95
96 static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA,
97 unsigned dstRGB, unsigned dstA)
98 {
99 /* If the blend equation is ADD or REVERSE_SUBTRACT,
100 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer
101 * will not be changed.
102 * Notice that the dst factors are the src factors inverted. */
103 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
104 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
105 (srcA == PIPE_BLENDFACTOR_ZERO) &&
106 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
107 dstRGB == PIPE_BLENDFACTOR_ONE) &&
108 (dstA == PIPE_BLENDFACTOR_ONE);
109 }
110
111 static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA,
112 unsigned dstRGB, unsigned dstA)
113 {
114 /* If the blend equation is ADD or REVERSE_SUBTRACT,
115 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer
116 * will not be changed.
117 * Notice that the dst factors are the src factors inverted. */
118 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
119 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
120 (srcA == PIPE_BLENDFACTOR_ZERO) &&
121 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
122 dstRGB == PIPE_BLENDFACTOR_ONE) &&
123 (dstA == PIPE_BLENDFACTOR_ONE);
124 }
125
126 static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA,
127 unsigned dstRGB, unsigned dstA)
128 {
129 /* If the blend equation is ADD or REVERSE_SUBTRACT,
130 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set,
131 * the colorbuffer will not be changed.
132 * Notice that the dst factors are the src factors inverted. */
133 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
134 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
135 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
136 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
137 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
138 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
139 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
140 srcA == PIPE_BLENDFACTOR_ZERO) &&
141 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
142 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
143 dstRGB == PIPE_BLENDFACTOR_ONE) &&
144 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
145 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
146 dstA == PIPE_BLENDFACTOR_ONE);
147 }
148
149 static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA,
150 unsigned dstRGB, unsigned dstA)
151 {
152 /* If the blend equation is ADD or REVERSE_SUBTRACT,
153 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set,
154 * the colorbuffer will not be changed.
155 * Notice that the dst factors are the src factors inverted. */
156 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
157 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
158 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
159 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
160 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
161 srcA == PIPE_BLENDFACTOR_ZERO) &&
162 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
163 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
164 dstRGB == PIPE_BLENDFACTOR_ONE) &&
165 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
166 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
167 dstA == PIPE_BLENDFACTOR_ONE);
168 }
169
170 static unsigned bgra_cmask(unsigned mask)
171 {
172 /* Gallium uses RGBA color ordering while R300 expects BGRA. */
173
174 return ((mask & PIPE_MASK_R) << 2) |
175 ((mask & PIPE_MASK_B) >> 2) |
176 (mask & (PIPE_MASK_G | PIPE_MASK_A));
177 }
178
179 /* Create a new blend state based on the CSO blend state.
180 *
181 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
182 static void* r300_create_blend_state(struct pipe_context* pipe,
183 const struct pipe_blend_state* state)
184 {
185 struct r300_screen* r300screen = r300_screen(pipe->screen);
186 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
187 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */
188 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */
189 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */
190 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */
191 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */
192 CB_LOCALS;
193
194 if (state->rt[0].blend_enable)
195 {
196 unsigned eqRGB = state->rt[0].rgb_func;
197 unsigned srcRGB = state->rt[0].rgb_src_factor;
198 unsigned dstRGB = state->rt[0].rgb_dst_factor;
199
200 unsigned eqA = state->rt[0].alpha_func;
201 unsigned srcA = state->rt[0].alpha_src_factor;
202 unsigned dstA = state->rt[0].alpha_dst_factor;
203
204 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
205 * this is just the crappy D3D naming */
206 blend_control = R300_ALPHA_BLEND_ENABLE |
207 r300_translate_blend_function(eqRGB) |
208 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) |
209 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT);
210
211 /* Optimization: some operations do not require the destination color.
212 *
213 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled,
214 * otherwise blending gives incorrect results. It seems to be
215 * a hardware bug. */
216 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN ||
217 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX ||
218 dstRGB != PIPE_BLENDFACTOR_ZERO ||
219 dstA != PIPE_BLENDFACTOR_ZERO ||
220 srcRGB == PIPE_BLENDFACTOR_DST_COLOR ||
221 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA ||
222 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR ||
223 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
224 srcA == PIPE_BLENDFACTOR_DST_COLOR ||
225 srcA == PIPE_BLENDFACTOR_DST_ALPHA ||
226 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR ||
227 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
228 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) {
229 /* Enable reading from the colorbuffer. */
230 blend_control |= R300_READ_ENABLE;
231
232 if (r300screen->caps.is_r500) {
233 /* Optimization: Depending on incoming pixels, we can
234 * conditionally disable the reading in hardware... */
235 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN &&
236 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) {
237 /* Disable reading if SRC_ALPHA == 0. */
238 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
239 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
240 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
241 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
242 dstA == PIPE_BLENDFACTOR_ZERO)) {
243 blend_control |= R500_SRC_ALPHA_0_NO_READ;
244 }
245
246 /* Disable reading if SRC_ALPHA == 1. */
247 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
248 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
249 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
250 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
251 dstA == PIPE_BLENDFACTOR_ZERO)) {
252 blend_control |= R500_SRC_ALPHA_1_NO_READ;
253 }
254 }
255 }
256 }
257
258 /* Optimization: discard pixels which don't change the colorbuffer.
259 *
260 * The code below is non-trivial and some math is involved.
261 *
262 * Discarding pixels must be disabled when FP16 AA is enabled.
263 * This is a hardware bug. Also, this implementation wouldn't work
264 * with FP blending enabled and equation clamping disabled.
265 *
266 * Equations other than ADD are rarely used and therefore won't be
267 * optimized. */
268 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) &&
269 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) {
270 /* ADD: X+Y
271 * REVERSE_SUBTRACT: Y-X
272 *
273 * The idea is:
274 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1,
275 * then CB will not be changed.
276 *
277 * Given the srcFactor and dstFactor variables, we can derive
278 * what src and dst should be equal to and discard appropriate
279 * pixels.
280 */
281 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) {
282 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
283 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA,
284 dstRGB, dstA)) {
285 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1;
286 } else if (blend_discard_if_src_color_0(srcRGB, srcA,
287 dstRGB, dstA)) {
288 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0;
289 } else if (blend_discard_if_src_color_1(srcRGB, srcA,
290 dstRGB, dstA)) {
291 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1;
292 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA,
293 dstRGB, dstA)) {
294 blend_control |=
295 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0;
296 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA,
297 dstRGB, dstA)) {
298 blend_control |=
299 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1;
300 }
301 }
302
303 /* separate alpha */
304 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
305 blend_control |= R300_SEPARATE_ALPHA_ENABLE;
306 alpha_blend_control =
307 r300_translate_blend_function(eqA) |
308 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) |
309 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT);
310 }
311 }
312
313 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
314 if (state->logicop_enable) {
315 rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
316 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
317 }
318
319 /* Color channel masks for all MRTs. */
320 color_channel_mask = bgra_cmask(state->rt[0].colormask);
321 if (r300screen->caps.is_r500 && state->independent_blend_enable) {
322 if (state->rt[1].blend_enable) {
323 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4;
324 }
325 if (state->rt[2].blend_enable) {
326 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8;
327 }
328 if (state->rt[3].blend_enable) {
329 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12;
330 }
331 }
332
333 /* Neither fglrx nor classic r300 ever set this, regardless of dithering
334 * state. Since it's an optional implementation detail, we can leave it
335 * out and never dither.
336 *
337 * This could be revisited if we ever get quality or conformance hints.
338 *
339 if (state->dither) {
340 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
341 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
342 }
343 */
344
345 /* Build a command buffer. */
346 BEGIN_CB(blend->cb, 8);
347 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
348 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
349 OUT_CB(blend_control);
350 OUT_CB(alpha_blend_control);
351 OUT_CB(color_channel_mask);
352 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
353 END_CB;
354
355 /* The same as above, but with no colorbuffer reads and writes. */
356 BEGIN_CB(blend->cb_no_readwrite, 8);
357 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
358 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
359 OUT_CB(0);
360 OUT_CB(0);
361 OUT_CB(0);
362 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
363 END_CB;
364
365 return (void*)blend;
366 }
367
368 /* Bind blend state. */
369 static void r300_bind_blend_state(struct pipe_context* pipe,
370 void* state)
371 {
372 struct r300_context* r300 = r300_context(pipe);
373
374 UPDATE_STATE(state, r300->blend_state);
375 }
376
377 /* Free blend state. */
378 static void r300_delete_blend_state(struct pipe_context* pipe,
379 void* state)
380 {
381 FREE(state);
382 }
383
384 /* Convert float to 10bit integer */
385 static unsigned float_to_fixed10(float f)
386 {
387 return CLAMP((unsigned)(f * 1023.9f), 0, 1023);
388 }
389
390 /* Set blend color.
391 * Setup both R300 and R500 registers, figure out later which one to write. */
392 static void r300_set_blend_color(struct pipe_context* pipe,
393 const struct pipe_blend_color* color)
394 {
395 struct r300_context* r300 = r300_context(pipe);
396 struct r300_blend_color_state* state =
397 (struct r300_blend_color_state*)r300->blend_color_state.state;
398 CB_LOCALS;
399
400 if (r300->screen->caps.is_r500) {
401 /* XXX if FP16 blending is enabled, we should use the FP16 format */
402 BEGIN_CB(state->cb, 3);
403 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
404 OUT_CB(float_to_fixed10(color->color[0]) |
405 (float_to_fixed10(color->color[3]) << 16));
406 OUT_CB(float_to_fixed10(color->color[2]) |
407 (float_to_fixed10(color->color[1]) << 16));
408 END_CB;
409 } else {
410 union util_color uc;
411 util_pack_color(color->color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
412
413 BEGIN_CB(state->cb, 2);
414 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui);
415 END_CB;
416 }
417
418 r300->blend_color_state.dirty = TRUE;
419 }
420
421 static void r300_set_clip_state(struct pipe_context* pipe,
422 const struct pipe_clip_state* state)
423 {
424 struct r300_context* r300 = r300_context(pipe);
425 struct r300_clip_state *clip =
426 (struct r300_clip_state*)r300->clip_state.state;
427 CB_LOCALS;
428
429 clip->clip = *state;
430
431 if (r300->screen->caps.has_tcl) {
432 BEGIN_CB(clip->cb, 29);
433 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG,
434 (r300->screen->caps.is_r500 ?
435 R500_PVS_UCP_START : R300_PVS_UCP_START));
436 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
437 OUT_CB_TABLE(state->ucp, 6 * 4);
438 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) |
439 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
440 END_CB;
441
442 r300->clip_state.dirty = TRUE;
443 } else {
444 draw_flush(r300->draw);
445 draw_set_clip_state(r300->draw, state);
446 }
447 }
448
449 static void
450 r300_set_sample_mask(struct pipe_context *pipe,
451 unsigned sample_mask)
452 {
453 }
454
455
456 /* Create a new depth, stencil, and alpha state based on the CSO dsa state.
457 *
458 * This contains the depth buffer, stencil buffer, alpha test, and such.
459 * On the Radeon, depth and stencil buffer setup are intertwined, which is
460 * the reason for some of the strange-looking assignments across registers. */
461 static void*
462 r300_create_dsa_state(struct pipe_context* pipe,
463 const struct pipe_depth_stencil_alpha_state* state)
464 {
465 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps;
466 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state);
467 CB_LOCALS;
468
469 dsa->dsa = *state;
470
471 /* Depth test setup. */
472 if (state->depth.enabled) {
473 dsa->z_buffer_control |= R300_Z_ENABLE;
474
475 if (state->depth.writemask) {
476 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE;
477 }
478
479 dsa->z_stencil_control |=
480 (r300_translate_depth_stencil_function(state->depth.func) <<
481 R300_Z_FUNC_SHIFT);
482 }
483
484 /* Stencil buffer setup. */
485 if (state->stencil[0].enabled) {
486 dsa->z_buffer_control |= R300_STENCIL_ENABLE;
487 dsa->z_stencil_control |=
488 (r300_translate_depth_stencil_function(state->stencil[0].func) <<
489 R300_S_FRONT_FUNC_SHIFT) |
490 (r300_translate_stencil_op(state->stencil[0].fail_op) <<
491 R300_S_FRONT_SFAIL_OP_SHIFT) |
492 (r300_translate_stencil_op(state->stencil[0].zpass_op) <<
493 R300_S_FRONT_ZPASS_OP_SHIFT) |
494 (r300_translate_stencil_op(state->stencil[0].zfail_op) <<
495 R300_S_FRONT_ZFAIL_OP_SHIFT);
496
497 dsa->stencil_ref_mask =
498 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
499 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
500
501 if (state->stencil[1].enabled) {
502 dsa->two_sided = TRUE;
503
504 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK;
505 dsa->z_stencil_control |=
506 (r300_translate_depth_stencil_function(state->stencil[1].func) <<
507 R300_S_BACK_FUNC_SHIFT) |
508 (r300_translate_stencil_op(state->stencil[1].fail_op) <<
509 R300_S_BACK_SFAIL_OP_SHIFT) |
510 (r300_translate_stencil_op(state->stencil[1].zpass_op) <<
511 R300_S_BACK_ZPASS_OP_SHIFT) |
512 (r300_translate_stencil_op(state->stencil[1].zfail_op) <<
513 R300_S_BACK_ZFAIL_OP_SHIFT);
514
515 dsa->stencil_ref_bf =
516 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) |
517 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
518
519 if (caps->is_r500) {
520 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
521 } else {
522 dsa->two_sided_stencil_ref =
523 (state->stencil[0].valuemask != state->stencil[1].valuemask ||
524 state->stencil[0].writemask != state->stencil[1].writemask);
525 }
526 }
527 }
528
529 /* Alpha test setup. */
530 if (state->alpha.enabled) {
531 dsa->alpha_function =
532 r300_translate_alpha_function(state->alpha.func) |
533 R300_FG_ALPHA_FUNC_ENABLE;
534
535 /* We could use 10bit alpha ref but who needs that? */
536 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value);
537
538 if (caps->is_r500)
539 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT;
540 }
541
542 BEGIN_CB(&dsa->cb_begin, 8);
543 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
544 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
545 OUT_CB(dsa->z_buffer_control);
546 OUT_CB(dsa->z_stencil_control);
547 OUT_CB(dsa->stencil_ref_mask);
548 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
549 END_CB;
550
551 BEGIN_CB(dsa->cb_no_readwrite, 8);
552 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
553 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
554 OUT_CB(0);
555 OUT_CB(0);
556 OUT_CB(0);
557 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
558 END_CB;
559
560 return (void*)dsa;
561 }
562
563 static void r300_dsa_inject_stencilref(struct r300_context *r300)
564 {
565 struct r300_dsa_state *dsa =
566 (struct r300_dsa_state*)r300->dsa_state.state;
567
568 if (!dsa)
569 return;
570
571 dsa->stencil_ref_mask =
572 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) |
573 r300->stencil_ref.ref_value[0];
574 dsa->stencil_ref_bf =
575 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) |
576 r300->stencil_ref.ref_value[1];
577 }
578
579 /* Bind DSA state. */
580 static void r300_bind_dsa_state(struct pipe_context* pipe,
581 void* state)
582 {
583 struct r300_context* r300 = r300_context(pipe);
584
585 if (!state) {
586 return;
587 }
588
589 UPDATE_STATE(state, r300->dsa_state);
590
591 r300_dsa_inject_stencilref(r300);
592 }
593
594 /* Free DSA state. */
595 static void r300_delete_dsa_state(struct pipe_context* pipe,
596 void* state)
597 {
598 FREE(state);
599 }
600
601 static void r300_set_stencil_ref(struct pipe_context* pipe,
602 const struct pipe_stencil_ref* sr)
603 {
604 struct r300_context* r300 = r300_context(pipe);
605
606 r300->stencil_ref = *sr;
607
608 r300_dsa_inject_stencilref(r300);
609 r300->dsa_state.dirty = TRUE;
610 }
611
612 static void r300_tex_set_tiling_flags(struct r300_context *r300,
613 struct r300_texture *tex, unsigned level)
614 {
615 /* Check if the macrotile flag needs to be changed.
616 * Skip changing the flags otherwise. */
617 if (tex->mip_macrotile[tex->surface_level] != tex->mip_macrotile[level]) {
618 /* Tiling determines how DRM treats the buffer data.
619 * We must flush CS when changing it if the buffer is referenced. */
620 if (r300->rws->is_buffer_referenced(r300->rws, tex->buffer, R300_REF_CS))
621 r300->context.flush(&r300->context, 0, NULL);
622
623 r300->rws->buffer_set_tiling(r300->rws, tex->buffer,
624 tex->pitch[0] * util_format_get_blocksize(tex->b.b.format),
625 tex->microtile,
626 tex->mip_macrotile[level]);
627
628 tex->surface_level = level;
629 }
630 }
631
632 /* This switcheroo is needed just because of goddamned MACRO_SWITCH. */
633 static void r300_fb_set_tiling_flags(struct r300_context *r300,
634 const struct pipe_framebuffer_state *state)
635 {
636 unsigned i;
637
638 /* Set tiling flags for new surfaces. */
639 for (i = 0; i < state->nr_cbufs; i++) {
640 r300_tex_set_tiling_flags(r300,
641 r300_texture(state->cbufs[i]->texture),
642 state->cbufs[i]->level);
643 }
644 if (state->zsbuf) {
645 r300_tex_set_tiling_flags(r300,
646 r300_texture(state->zsbuf->texture),
647 state->zsbuf->level);
648 }
649 }
650
651 static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index,
652 const char *binding)
653 {
654 struct pipe_resource *tex = surf->texture;
655 struct r300_texture *rtex = r300_texture(tex);
656
657 fprintf(stderr,
658 "r300: %s[%i] Dim: %ix%i, Offset: %i, ZSlice: %i, "
659 "Face: %i, Level: %i, Format: %s\n"
660
661 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, "
662 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n",
663
664 binding, index, surf->width, surf->height, surf->offset,
665 surf->zslice, surf->face, surf->level,
666 util_format_short_name(surf->format),
667
668 rtex->macrotile ? "YES" : " NO", rtex->microtile ? "YES" : " NO",
669 rtex->hwpitch[0], tex->width0, tex->height0, tex->depth0,
670 tex->last_level, util_format_short_name(tex->format));
671 }
672
673 void r300_mark_fb_state_dirty(struct r300_context *r300,
674 enum r300_fb_state_change change)
675 {
676 struct pipe_framebuffer_state *state = r300->fb_state.state;
677
678 /* What is marked as dirty depends on the enum r300_fb_state_change. */
679 r300->gpu_flush.dirty = TRUE;
680 r300->fb_state.dirty = TRUE;
681 r300->hyperz_state.dirty = TRUE;
682
683 if (change == R300_CHANGED_FB_STATE) {
684 r300->aa_state.dirty = TRUE;
685 r300->fb_state_pipelined.dirty = TRUE;
686 }
687
688 /* Now compute the fb_state atom size. */
689 r300->fb_state.size = 2 + (8 * state->nr_cbufs);
690
691 if (state->zsbuf)
692 r300->fb_state.size += r300->screen->caps.has_hiz ? 18 : 14;
693
694 /* The size of the rest of atoms stays the same. */
695 }
696
697 static void
698 r300_set_framebuffer_state(struct pipe_context* pipe,
699 const struct pipe_framebuffer_state* state)
700 {
701 struct r300_context* r300 = r300_context(pipe);
702 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
703 struct pipe_framebuffer_state *old_state = r300->fb_state.state;
704 unsigned max_width, max_height, i;
705 uint32_t zbuffer_bpp = 0;
706
707 if (r300->screen->caps.is_r500) {
708 max_width = max_height = 4096;
709 } else if (r300->screen->caps.is_r400) {
710 max_width = max_height = 4021;
711 } else {
712 max_width = max_height = 2560;
713 }
714
715 if (state->width > max_width || state->height > max_height) {
716 fprintf(stderr, "r300: Implementation error: Render targets are too "
717 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__);
718 return;
719 }
720
721 if (r300->draw) {
722 draw_flush(r300->draw);
723 }
724
725 /* If nr_cbufs is changed from zero to non-zero or vice versa... */
726 if (!!old_state->nr_cbufs != !!state->nr_cbufs) {
727 r300->blend_state.dirty = TRUE;
728 }
729 /* If zsbuf is set from NULL to non-NULL or vice versa.. */
730 if (!!old_state->zsbuf != !!state->zsbuf) {
731 r300->dsa_state.dirty = TRUE;
732 }
733
734 /* The tiling flags are dependent on the surface miplevel, unfortunately. */
735 r300_fb_set_tiling_flags(r300, state);
736
737 util_assign_framebuffer_state(r300->fb_state.state, state);
738
739 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE);
740
741 /* Polygon offset depends on the zbuffer bit depth. */
742 if (state->zsbuf && r300->polygon_offset_enabled) {
743 switch (util_format_get_blocksize(state->zsbuf->texture->format)) {
744 case 2:
745 zbuffer_bpp = 16;
746 break;
747 case 4:
748 zbuffer_bpp = 24;
749 break;
750 }
751
752 if (r300->zbuffer_bpp != zbuffer_bpp) {
753 r300->zbuffer_bpp = zbuffer_bpp;
754 r300->rs_state.dirty = TRUE;
755 }
756 }
757
758 /* Set up AA config. */
759 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
760 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) {
761 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE;
762
763 switch (state->cbufs[0]->texture->nr_samples) {
764 case 2:
765 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2;
766 break;
767 case 3:
768 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3;
769 break;
770 case 4:
771 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4;
772 break;
773 case 6:
774 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6;
775 break;
776 }
777 } else {
778 aa->aa_config = 0;
779 }
780 }
781
782 if (DBG_ON(r300, DBG_FB)) {
783 fprintf(stderr, "r300: set_framebuffer_state:\n");
784 for (i = 0; i < state->nr_cbufs; i++) {
785 r300_print_fb_surf_info(state->cbufs[i], i, "CB");
786 }
787 if (state->zsbuf) {
788 r300_print_fb_surf_info(state->zsbuf, 0, "ZB");
789 }
790 }
791 }
792
793 /* Create fragment shader state. */
794 static void* r300_create_fs_state(struct pipe_context* pipe,
795 const struct pipe_shader_state* shader)
796 {
797 struct r300_fragment_shader* fs = NULL;
798
799 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader);
800
801 /* Copy state directly into shader. */
802 fs->state = *shader;
803 fs->state.tokens = tgsi_dup_tokens(shader->tokens);
804
805 return (void*)fs;
806 }
807
808 void r300_mark_fs_code_dirty(struct r300_context *r300)
809 {
810 struct r300_fragment_shader* fs = r300_fs(r300);
811
812 r300->fs.dirty = TRUE;
813 r300->fs_rc_constant_state.dirty = TRUE;
814 r300->fs_constants.dirty = TRUE;
815 r300->fs.size = fs->shader->cb_code_size;
816
817 if (r300->screen->caps.is_r500) {
818 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7;
819 r300->fs_constants.size = fs->shader->externals_count * 4 + 3;
820 } else {
821 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5;
822 r300->fs_constants.size = fs->shader->externals_count * 4 + 1;
823 }
824 }
825
826 /* Bind fragment shader state. */
827 static void r300_bind_fs_state(struct pipe_context* pipe, void* shader)
828 {
829 struct r300_context* r300 = r300_context(pipe);
830 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
831
832 if (fs == NULL) {
833 r300->fs.state = NULL;
834 return;
835 }
836
837 r300->fs.state = fs;
838 r300_pick_fragment_shader(r300);
839 r300_mark_fs_code_dirty(r300);
840
841 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */
842 }
843
844 /* Delete fragment shader state. */
845 static void r300_delete_fs_state(struct pipe_context* pipe, void* shader)
846 {
847 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
848 struct r300_fragment_shader_code *tmp, *ptr = fs->first;
849
850 while (ptr) {
851 tmp = ptr;
852 ptr = ptr->next;
853 rc_constants_destroy(&tmp->code.constants);
854 FREE(tmp->cb_code);
855 FREE(tmp);
856 }
857 FREE((void*)fs->state.tokens);
858 FREE(shader);
859 }
860
861 static void r300_set_polygon_stipple(struct pipe_context* pipe,
862 const struct pipe_poly_stipple* state)
863 {
864 /* XXX no idea how to set this up, but not terribly important */
865 }
866
867 /* Create a new rasterizer state based on the CSO rasterizer state.
868 *
869 * This is a very large chunk of state, and covers most of the graphics
870 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
871 *
872 * In a not entirely unironic sidenote, this state has nearly nothing to do
873 * with the actual block on the Radeon called the rasterizer (RS). */
874 static void* r300_create_rs_state(struct pipe_context* pipe,
875 const struct pipe_rasterizer_state* state)
876 {
877 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state);
878 int i;
879 float psiz;
880 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */
881 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */
882 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */
883 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */
884 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */
885 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */
886 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */
887 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */
888 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */
889 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */
890
891 /* Specifies top of Raster pipe specific enable controls,
892 * i.e. texture coordinates stuffing for points, lines, triangles */
893 uint32_t stuffing_enable; /* R300_GB_ENABLE: 0x4008 */
894
895 /* Point sprites texture coordinates, 0: lower left, 1: upper right */
896 float point_texcoord_left; /* R300_GA_POINT_S0: 0x4200 */
897 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */
898 float point_texcoord_right; /* R300_GA_POINT_S1: 0x4208 */
899 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */
900 CB_LOCALS;
901
902 /* Copy rasterizer state. */
903 rs->rs = *state;
904 rs->rs_draw = *state;
905
906 /* Override some states for Draw. */
907 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */
908
909 #ifdef PIPE_ARCH_LITTLE_ENDIAN
910 vap_control_status = R300_VC_NO_SWAP;
911 #else
912 vap_control_status = R300_VC_32BIT_SWAP;
913 #endif
914
915 /* If no TCL engine is present, turn off the HW TCL. */
916 if (!r300_screen(pipe->screen)->caps.has_tcl) {
917 vap_control_status |= R300_VAP_TCL_BYPASS;
918 }
919
920 /* Point size width and height. */
921 point_size =
922 pack_float_16_6x(state->point_size) |
923 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT);
924
925 /* Point size clamping. */
926 if (state->point_size_per_vertex) {
927 /* Per-vertex point size.
928 * Clamp to [0, max FB size] */
929 psiz = pipe->screen->get_paramf(pipe->screen,
930 PIPE_CAP_MAX_POINT_WIDTH);
931 point_minmax =
932 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT;
933 } else {
934 /* We cannot disable the point-size vertex output,
935 * so clamp it. */
936 psiz = state->point_size;
937 point_minmax =
938 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) |
939 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT);
940 }
941
942 /* Line control. */
943 line_control = pack_float_16_6x(state->line_width) |
944 R300_GA_LINE_CNTL_END_TYPE_COMP;
945
946 /* Enable polygon mode */
947 polygon_mode = 0;
948 if (state->fill_front != PIPE_POLYGON_MODE_FILL ||
949 state->fill_back != PIPE_POLYGON_MODE_FILL) {
950 polygon_mode = R300_GA_POLY_MODE_DUAL;
951 }
952
953 /* Front face */
954 if (state->front_ccw)
955 cull_mode = R300_FRONT_FACE_CCW;
956 else
957 cull_mode = R300_FRONT_FACE_CW;
958
959 /* Polygon offset */
960 polygon_offset_enable = 0;
961 if (util_get_offset(state, state->fill_front)) {
962 polygon_offset_enable |= R300_FRONT_ENABLE;
963 }
964 if (util_get_offset(state, state->fill_back)) {
965 polygon_offset_enable |= R300_BACK_ENABLE;
966 }
967
968 rs->polygon_offset_enable = polygon_offset_enable != 0;
969
970 /* Polygon mode */
971 if (polygon_mode) {
972 polygon_mode |=
973 r300_translate_polygon_mode_front(state->fill_front);
974 polygon_mode |=
975 r300_translate_polygon_mode_back(state->fill_back);
976 }
977
978 if (state->cull_face & PIPE_FACE_FRONT) {
979 cull_mode |= R300_CULL_FRONT;
980 }
981 if (state->cull_face & PIPE_FACE_BACK) {
982 cull_mode |= R300_CULL_BACK;
983 }
984
985 if (state->line_stipple_enable) {
986 line_stipple_config =
987 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE |
988 (fui((float)state->line_stipple_factor) &
989 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK);
990 /* XXX this might need to be scaled up */
991 line_stipple_value = state->line_stipple_pattern;
992 } else {
993 line_stipple_config = 0;
994 line_stipple_value = 0;
995 }
996
997 if (state->flatshade) {
998 rs->color_control = R300_SHADE_MODEL_FLAT;
999 } else {
1000 rs->color_control = R300_SHADE_MODEL_SMOOTH;
1001 }
1002
1003 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
1004
1005 /* Point sprites */
1006 stuffing_enable = 0;
1007 if (state->sprite_coord_enable) {
1008 stuffing_enable = R300_GB_POINT_STUFF_ENABLE;
1009 for (i = 0; i < 8; i++) {
1010 if (state->sprite_coord_enable & (1 << i))
1011 stuffing_enable |=
1012 R300_GB_TEX_STR << (R300_GB_TEX0_SOURCE_SHIFT + (i*2));
1013 }
1014
1015 point_texcoord_left = 0.0f;
1016 point_texcoord_right = 1.0f;
1017
1018 switch (state->sprite_coord_mode) {
1019 case PIPE_SPRITE_COORD_UPPER_LEFT:
1020 point_texcoord_top = 0.0f;
1021 point_texcoord_bottom = 1.0f;
1022 break;
1023 case PIPE_SPRITE_COORD_LOWER_LEFT:
1024 point_texcoord_top = 1.0f;
1025 point_texcoord_bottom = 0.0f;
1026 break;
1027 }
1028 }
1029
1030 /* Build the main command buffer. */
1031 BEGIN_CB(rs->cb_main, 25);
1032 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status);
1033 OUT_CB_REG(R300_GA_POINT_SIZE, point_size);
1034 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2);
1035 OUT_CB(point_minmax);
1036 OUT_CB(line_control);
1037 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
1038 OUT_CB(polygon_offset_enable);
1039 rs->cull_mode_index = 9;
1040 OUT_CB(cull_mode);
1041 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config);
1042 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value);
1043 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode);
1044 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule);
1045 OUT_CB_REG(R300_GB_ENABLE, stuffing_enable);
1046 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4);
1047 OUT_CB_32F(point_texcoord_left);
1048 OUT_CB_32F(point_texcoord_bottom);
1049 OUT_CB_32F(point_texcoord_right);
1050 OUT_CB_32F(point_texcoord_top);
1051 END_CB;
1052
1053 /* Build the two command buffers for polygon offset setup. */
1054 if (polygon_offset_enable) {
1055 float scale = state->offset_scale * 12;
1056 float offset = state->offset_units * 4;
1057
1058 BEGIN_CB(rs->cb_poly_offset_zb16, 5);
1059 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1060 OUT_CB_32F(scale);
1061 OUT_CB_32F(offset);
1062 OUT_CB_32F(scale);
1063 OUT_CB_32F(offset);
1064 END_CB;
1065
1066 offset = state->offset_units * 2;
1067
1068 BEGIN_CB(rs->cb_poly_offset_zb24, 5);
1069 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1070 OUT_CB_32F(scale);
1071 OUT_CB_32F(offset);
1072 OUT_CB_32F(scale);
1073 OUT_CB_32F(offset);
1074 END_CB;
1075 }
1076
1077 return (void*)rs;
1078 }
1079
1080 /* Bind rasterizer state. */
1081 static void r300_bind_rs_state(struct pipe_context* pipe, void* state)
1082 {
1083 struct r300_context* r300 = r300_context(pipe);
1084 struct r300_rs_state* rs = (struct r300_rs_state*)state;
1085 int last_sprite_coord_enable = r300->sprite_coord_enable;
1086 boolean last_two_sided_color = r300->two_sided_color;
1087
1088 if (r300->draw && rs) {
1089 draw_flush(r300->draw);
1090 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state);
1091 }
1092
1093 if (rs) {
1094 r300->polygon_offset_enabled = (rs->rs.offset_point ||
1095 rs->rs.offset_line ||
1096 rs->rs.offset_tri);
1097 r300->sprite_coord_enable = rs->rs.sprite_coord_enable;
1098 r300->two_sided_color = rs->rs.light_twoside;
1099 } else {
1100 r300->polygon_offset_enabled = FALSE;
1101 r300->sprite_coord_enable = 0;
1102 r300->two_sided_color = FALSE;
1103 }
1104
1105 UPDATE_STATE(state, r300->rs_state);
1106 r300->rs_state.size = 25 + (r300->polygon_offset_enabled ? 5 : 0);
1107
1108 if (last_sprite_coord_enable != r300->sprite_coord_enable ||
1109 last_two_sided_color != r300->two_sided_color) {
1110 r300->rs_block_state.dirty = TRUE;
1111 }
1112 }
1113
1114 /* Free rasterizer state. */
1115 static void r300_delete_rs_state(struct pipe_context* pipe, void* state)
1116 {
1117 FREE(state);
1118 }
1119
1120 static void*
1121 r300_create_sampler_state(struct pipe_context* pipe,
1122 const struct pipe_sampler_state* state)
1123 {
1124 struct r300_context* r300 = r300_context(pipe);
1125 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
1126 boolean is_r500 = r300->screen->caps.is_r500;
1127 int lod_bias;
1128 union util_color uc;
1129
1130 sampler->state = *state;
1131
1132 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG
1133 * or MIN filter is NEAREST. Since texwrap produces same results
1134 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */
1135 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST ||
1136 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) {
1137 /* Wrap S. */
1138 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP)
1139 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1140 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP)
1141 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1142
1143 /* Wrap T. */
1144 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP)
1145 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1146 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP)
1147 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1148
1149 /* Wrap R. */
1150 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP)
1151 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1152 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP)
1153 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1154 }
1155
1156 sampler->filter0 |=
1157 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) |
1158 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) |
1159 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT);
1160
1161 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter,
1162 state->mag_img_filter,
1163 state->min_mip_filter,
1164 state->max_anisotropy > 0);
1165
1166 sampler->filter0 |= r300_anisotropy(state->max_anisotropy);
1167
1168 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */
1169 /* We must pass these to the merge function to clamp them properly. */
1170 sampler->min_lod = MAX2((unsigned)state->min_lod, 0);
1171 sampler->max_lod = MAX2((unsigned)ceilf(state->max_lod), 0);
1172
1173 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1);
1174
1175 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK;
1176
1177 /* This is very high quality anisotropic filtering for R5xx.
1178 * It's good for benchmarking the performance of texturing but
1179 * in practice we don't want to slow down the driver because it's
1180 * a pretty good performance killer. Feel free to play with it. */
1181 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) {
1182 sampler->filter1 |= r500_anisotropy(state->max_anisotropy);
1183 }
1184
1185 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1186 sampler->border_color = uc.ui;
1187
1188 /* R500-specific fixups and optimizations */
1189 if (r300->screen->caps.is_r500) {
1190 sampler->filter1 |= R500_BORDER_FIX;
1191 }
1192
1193 return (void*)sampler;
1194 }
1195
1196 static void r300_bind_sampler_states(struct pipe_context* pipe,
1197 unsigned count,
1198 void** states)
1199 {
1200 struct r300_context* r300 = r300_context(pipe);
1201 struct r300_textures_state* state =
1202 (struct r300_textures_state*)r300->textures_state.state;
1203 unsigned tex_units = r300->screen->caps.num_tex_units;
1204
1205 if (count > tex_units) {
1206 return;
1207 }
1208
1209 memcpy(state->sampler_states, states, sizeof(void*) * count);
1210 state->sampler_state_count = count;
1211
1212 r300->textures_state.dirty = TRUE;
1213 }
1214
1215 static void r300_lacks_vertex_textures(struct pipe_context* pipe,
1216 unsigned count,
1217 void** states)
1218 {
1219 }
1220
1221 static void r300_delete_sampler_state(struct pipe_context* pipe, void* state)
1222 {
1223 FREE(state);
1224 }
1225
1226 static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num)
1227 {
1228 /* This looks like a hack, but I believe it's suppose to work like
1229 * that. To illustrate how this works, let's assume you have 5 textures.
1230 * From docs, 5 and the successive numbers are:
1231 *
1232 * FOURTH_1 = 5
1233 * FOURTH_2 = 6
1234 * FOURTH_3 = 7
1235 * EIGHTH_0 = 8
1236 * EIGHTH_1 = 9
1237 *
1238 * First 3 textures will get 3/4 of size of the cache, divived evenly
1239 * between them. The last 1/4 of the cache must be divided between
1240 * the last 2 textures, each will therefore get 1/8 of the cache.
1241 * Why not just to use "5 + texture_index" ?
1242 *
1243 * This simple trick works for all "num" <= 16.
1244 */
1245 if (num <= 1)
1246 return R300_TX_CACHE(R300_TX_CACHE_WHOLE);
1247 else
1248 return R300_TX_CACHE(num + index);
1249 }
1250
1251 static void r300_set_fragment_sampler_views(struct pipe_context* pipe,
1252 unsigned count,
1253 struct pipe_sampler_view** views)
1254 {
1255 struct r300_context* r300 = r300_context(pipe);
1256 struct r300_textures_state* state =
1257 (struct r300_textures_state*)r300->textures_state.state;
1258 struct r300_texture *texture;
1259 unsigned i, real_num_views = 0, view_index = 0;
1260 unsigned tex_units = r300->screen->caps.num_tex_units;
1261 boolean dirty_tex = FALSE;
1262
1263 if (count > tex_units) {
1264 return;
1265 }
1266
1267 /* Calculate the real number of views. */
1268 for (i = 0; i < count; i++) {
1269 if (views[i])
1270 real_num_views++;
1271 }
1272
1273 for (i = 0; i < count; i++) {
1274 if (&state->sampler_views[i]->base != views[i]) {
1275 pipe_sampler_view_reference(
1276 (struct pipe_sampler_view**)&state->sampler_views[i],
1277 views[i]);
1278
1279 if (!views[i]) {
1280 continue;
1281 }
1282
1283 /* A new sampler view (= texture)... */
1284 dirty_tex = TRUE;
1285
1286 /* Set the texrect factor in the fragment shader.
1287 * Needed for RECT and NPOT fallback. */
1288 texture = r300_texture(views[i]->texture);
1289 if (texture->uses_pitch) {
1290 r300->fs_rc_constant_state.dirty = TRUE;
1291 }
1292
1293 state->sampler_views[i]->texcache_region =
1294 r300_assign_texture_cache_region(view_index, real_num_views);
1295 view_index++;
1296 }
1297 }
1298
1299 for (i = count; i < tex_units; i++) {
1300 if (state->sampler_views[i]) {
1301 pipe_sampler_view_reference(
1302 (struct pipe_sampler_view**)&state->sampler_views[i],
1303 NULL);
1304 }
1305 }
1306
1307 state->sampler_view_count = count;
1308
1309 r300->textures_state.dirty = TRUE;
1310
1311 if (dirty_tex) {
1312 r300->texture_cache_inval.dirty = TRUE;
1313 }
1314 }
1315
1316 static struct pipe_sampler_view *
1317 r300_create_sampler_view(struct pipe_context *pipe,
1318 struct pipe_resource *texture,
1319 const struct pipe_sampler_view *templ)
1320 {
1321 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view);
1322 struct r300_texture *tex = r300_texture(texture);
1323
1324 if (view) {
1325 view->base = *templ;
1326 view->base.reference.count = 1;
1327 view->base.context = pipe;
1328 view->base.texture = NULL;
1329 pipe_resource_reference(&view->base.texture, texture);
1330
1331 view->swizzle[0] = templ->swizzle_r;
1332 view->swizzle[1] = templ->swizzle_g;
1333 view->swizzle[2] = templ->swizzle_b;
1334 view->swizzle[3] = templ->swizzle_a;
1335
1336 view->format = tex->tx_format;
1337 view->format.format1 |= r300_translate_texformat(templ->format,
1338 view->swizzle);
1339 if (r300_screen(pipe->screen)->caps.is_r500) {
1340 view->format.format2 |= r500_tx_format_msb_bit(templ->format);
1341 }
1342 }
1343
1344 return (struct pipe_sampler_view*)view;
1345 }
1346
1347 static void
1348 r300_sampler_view_destroy(struct pipe_context *pipe,
1349 struct pipe_sampler_view *view)
1350 {
1351 pipe_resource_reference(&view->texture, NULL);
1352 FREE(view);
1353 }
1354
1355 static void r300_set_scissor_state(struct pipe_context* pipe,
1356 const struct pipe_scissor_state* state)
1357 {
1358 struct r300_context* r300 = r300_context(pipe);
1359
1360 memcpy(r300->scissor_state.state, state,
1361 sizeof(struct pipe_scissor_state));
1362
1363 r300->scissor_state.dirty = TRUE;
1364 }
1365
1366 static void r300_set_viewport_state(struct pipe_context* pipe,
1367 const struct pipe_viewport_state* state)
1368 {
1369 struct r300_context* r300 = r300_context(pipe);
1370 struct r300_viewport_state* viewport =
1371 (struct r300_viewport_state*)r300->viewport_state.state;
1372
1373 r300->viewport = *state;
1374
1375 if (r300->draw) {
1376 draw_flush(r300->draw);
1377 draw_set_viewport_state(r300->draw, state);
1378 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT;
1379 return;
1380 }
1381
1382 /* Do the transform in HW. */
1383 viewport->vte_control = R300_VTX_W0_FMT;
1384
1385 if (state->scale[0] != 1.0f) {
1386 viewport->xscale = state->scale[0];
1387 viewport->vte_control |= R300_VPORT_X_SCALE_ENA;
1388 }
1389 if (state->scale[1] != 1.0f) {
1390 viewport->yscale = state->scale[1];
1391 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA;
1392 }
1393 if (state->scale[2] != 1.0f) {
1394 viewport->zscale = state->scale[2];
1395 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA;
1396 }
1397 if (state->translate[0] != 0.0f) {
1398 viewport->xoffset = state->translate[0];
1399 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA;
1400 }
1401 if (state->translate[1] != 0.0f) {
1402 viewport->yoffset = state->translate[1];
1403 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA;
1404 }
1405 if (state->translate[2] != 0.0f) {
1406 viewport->zoffset = state->translate[2];
1407 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA;
1408 }
1409
1410 r300->viewport_state.dirty = TRUE;
1411 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) {
1412 r300->fs_rc_constant_state.dirty = TRUE;
1413 }
1414 }
1415
1416 static void r300_set_vertex_buffers(struct pipe_context* pipe,
1417 unsigned count,
1418 const struct pipe_vertex_buffer* buffers)
1419 {
1420 struct r300_context* r300 = r300_context(pipe);
1421 struct pipe_vertex_buffer *vbo;
1422 unsigned i, max_index = (1 << 24) - 1;
1423 boolean any_user_buffer = FALSE;
1424
1425 if (count == r300->vertex_buffer_count &&
1426 memcmp(r300->vertex_buffer, buffers,
1427 sizeof(struct pipe_vertex_buffer) * count) == 0) {
1428 return;
1429 }
1430
1431 if (r300->screen->caps.has_tcl) {
1432 /* HW TCL. */
1433 r300->incompatible_vb_layout = FALSE;
1434
1435 /* Check if the strides and offsets are aligned to the size of DWORD. */
1436 for (i = 0; i < count; i++) {
1437 if (buffers[i].buffer) {
1438 if (buffers[i].stride % 4 != 0 ||
1439 buffers[i].buffer_offset % 4 != 0) {
1440 r300->incompatible_vb_layout = TRUE;
1441 break;
1442 }
1443 }
1444 }
1445
1446 for (i = 0; i < count; i++) {
1447 /* Why, yes, I AM casting away constness. How did you know? */
1448 vbo = (struct pipe_vertex_buffer*)&buffers[i];
1449
1450 /* Skip NULL buffers */
1451 if (!buffers[i].buffer) {
1452 continue;
1453 }
1454
1455 if (r300_buffer_is_user_buffer(vbo->buffer)) {
1456 any_user_buffer = TRUE;
1457 }
1458
1459 if (vbo->max_index == ~0) {
1460 /* if no VBO stride then only one vertex value so max index is 1 */
1461 /* should think about converting to VS constants like svga does */
1462 if (!vbo->stride)
1463 vbo->max_index = 1;
1464 else
1465 vbo->max_index =
1466 (vbo->buffer->width0 - vbo->buffer_offset) / vbo->stride;
1467 }
1468
1469 max_index = MIN2(vbo->max_index, max_index);
1470 }
1471
1472 r300->any_user_vbs = any_user_buffer;
1473 r300->vertex_buffer_max_index = max_index;
1474
1475 } else {
1476 /* SW TCL. */
1477 draw_flush(r300->draw);
1478 draw_set_vertex_buffers(r300->draw, count, buffers);
1479 }
1480
1481 /* Common code. */
1482 for (i = 0; i < count; i++) {
1483 /* Reference our buffer. */
1484 pipe_resource_reference(&r300->vertex_buffer[i].buffer, buffers[i].buffer);
1485 }
1486 for (; i < r300->vertex_buffer_count; i++) {
1487 /* Dereference any old buffers. */
1488 pipe_resource_reference(&r300->vertex_buffer[i].buffer, NULL);
1489 }
1490
1491 memcpy(r300->vertex_buffer, buffers,
1492 sizeof(struct pipe_vertex_buffer) * count);
1493 r300->vertex_buffer_count = count;
1494 }
1495
1496 /* Initialize the PSC tables. */
1497 static void r300_vertex_psc(struct r300_vertex_element_state *velems)
1498 {
1499 struct r300_vertex_stream_state *vstream = &velems->vertex_stream;
1500 uint16_t type, swizzle;
1501 enum pipe_format format;
1502 unsigned i;
1503
1504 if (velems->count > 16) {
1505 fprintf(stderr, "r300: More than 16 vertex elements are not supported,"
1506 " requested %i, using 16.\n", velems->count);
1507 velems->count = 16;
1508 }
1509
1510 /* Vertex shaders have no semantics on their inputs,
1511 * so PSC should just route stuff based on the vertex elements,
1512 * and not on attrib information. */
1513 for (i = 0; i < velems->count; i++) {
1514 format = velems->hw_format[i];
1515
1516 type = r300_translate_vertex_data_type(format);
1517 if (type == R300_INVALID_FORMAT) {
1518 fprintf(stderr, "r300: Bad vertex format %s.\n",
1519 util_format_short_name(format));
1520 assert(0);
1521 abort();
1522 }
1523
1524 type |= i << R300_DST_VEC_LOC_SHIFT;
1525 swizzle = r300_translate_vertex_data_swizzle(format);
1526
1527 if (i & 1) {
1528 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16;
1529 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16;
1530 } else {
1531 vstream->vap_prog_stream_cntl[i >> 1] |= type;
1532 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle;
1533 }
1534 }
1535
1536 /* Set the last vector in the PSC. */
1537 if (i) {
1538 i -= 1;
1539 }
1540 vstream->vap_prog_stream_cntl[i >> 1] |=
1541 (R300_LAST_VEC << (i & 1 ? 16 : 0));
1542
1543 vstream->count = (i >> 1) + 1;
1544 }
1545
1546 #define FORMAT_REPLACE(what, withwhat) \
1547 case PIPE_FORMAT_##what: *format = PIPE_FORMAT_##withwhat; break
1548
1549 static void* r300_create_vertex_elements_state(struct pipe_context* pipe,
1550 unsigned count,
1551 const struct pipe_vertex_element* attribs)
1552 {
1553 struct r300_vertex_element_state *velems;
1554 unsigned i;
1555 enum pipe_format *format;
1556
1557 assert(count <= PIPE_MAX_ATTRIBS);
1558 velems = CALLOC_STRUCT(r300_vertex_element_state);
1559 if (velems != NULL) {
1560 velems->count = count;
1561 memcpy(velems->velem, attribs, sizeof(struct pipe_vertex_element) * count);
1562
1563 if (r300_screen(pipe->screen)->caps.has_tcl) {
1564 /* Set the best hw format in case the original format is not
1565 * supported by hw. */
1566 for (i = 0; i < count; i++) {
1567 velems->hw_format[i] = velems->velem[i].src_format;
1568 format = &velems->hw_format[i];
1569
1570 /* This is basically the list of unsupported formats.
1571 * For now we don't care about the alignment, that's going to
1572 * be sorted out after the PSC setup. */
1573 switch (*format) {
1574 FORMAT_REPLACE(R64_FLOAT, R32_FLOAT);
1575 FORMAT_REPLACE(R64G64_FLOAT, R32G32_FLOAT);
1576 FORMAT_REPLACE(R64G64B64_FLOAT, R32G32B32_FLOAT);
1577 FORMAT_REPLACE(R64G64B64A64_FLOAT, R32G32B32A32_FLOAT);
1578
1579 FORMAT_REPLACE(R32_UNORM, R32_FLOAT);
1580 FORMAT_REPLACE(R32G32_UNORM, R32G32_FLOAT);
1581 FORMAT_REPLACE(R32G32B32_UNORM, R32G32B32_FLOAT);
1582 FORMAT_REPLACE(R32G32B32A32_UNORM, R32G32B32A32_FLOAT);
1583
1584 FORMAT_REPLACE(R32_USCALED, R32_FLOAT);
1585 FORMAT_REPLACE(R32G32_USCALED, R32G32_FLOAT);
1586 FORMAT_REPLACE(R32G32B32_USCALED, R32G32B32_FLOAT);
1587 FORMAT_REPLACE(R32G32B32A32_USCALED,R32G32B32A32_FLOAT);
1588
1589 FORMAT_REPLACE(R32_SNORM, R32_FLOAT);
1590 FORMAT_REPLACE(R32G32_SNORM, R32G32_FLOAT);
1591 FORMAT_REPLACE(R32G32B32_SNORM, R32G32B32_FLOAT);
1592 FORMAT_REPLACE(R32G32B32A32_SNORM, R32G32B32A32_FLOAT);
1593
1594 FORMAT_REPLACE(R32_SSCALED, R32_FLOAT);
1595 FORMAT_REPLACE(R32G32_SSCALED, R32G32_FLOAT);
1596 FORMAT_REPLACE(R32G32B32_SSCALED, R32G32B32_FLOAT);
1597 FORMAT_REPLACE(R32G32B32A32_SSCALED,R32G32B32A32_FLOAT);
1598
1599 FORMAT_REPLACE(R32_FIXED, R32_FLOAT);
1600 FORMAT_REPLACE(R32G32_FIXED, R32G32_FLOAT);
1601 FORMAT_REPLACE(R32G32B32_FIXED, R32G32B32_FLOAT);
1602 FORMAT_REPLACE(R32G32B32A32_FIXED, R32G32B32A32_FLOAT);
1603
1604 default:;
1605 }
1606
1607 velems->incompatible_layout =
1608 velems->incompatible_layout ||
1609 velems->velem[i].src_format != velems->hw_format[i] ||
1610 velems->velem[i].src_offset % 4 != 0;
1611 }
1612
1613 /* Now setup PSC.
1614 * The unused components will be replaced by (..., 0, 1). */
1615 r300_vertex_psc(velems);
1616
1617 /* Align the formats to the size of DWORD.
1618 * We only care about the blocksizes of the formats since
1619 * swizzles are already set up.
1620 * Also compute the vertex size. */
1621 for (i = 0; i < count; i++) {
1622 /* This is OK because we check for aligned strides too. */
1623 velems->hw_format_size[i] =
1624 align(util_format_get_blocksize(velems->hw_format[i]), 4);
1625 velems->vertex_size_dwords += velems->hw_format_size[i] / 4;
1626 }
1627 }
1628 }
1629 return velems;
1630 }
1631
1632 static void r300_bind_vertex_elements_state(struct pipe_context *pipe,
1633 void *state)
1634 {
1635 struct r300_context *r300 = r300_context(pipe);
1636 struct r300_vertex_element_state *velems = state;
1637
1638 if (velems == NULL) {
1639 return;
1640 }
1641
1642 r300->velems = velems;
1643
1644 if (r300->draw) {
1645 draw_flush(r300->draw);
1646 draw_set_vertex_elements(r300->draw, velems->count, velems->velem);
1647 return;
1648 }
1649
1650 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state);
1651 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2;
1652 }
1653
1654 static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state)
1655 {
1656 FREE(state);
1657 }
1658
1659 static void* r300_create_vs_state(struct pipe_context* pipe,
1660 const struct pipe_shader_state* shader)
1661 {
1662 struct r300_context* r300 = r300_context(pipe);
1663 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader);
1664
1665 /* Copy state directly into shader. */
1666 vs->state = *shader;
1667 vs->state.tokens = tgsi_dup_tokens(shader->tokens);
1668
1669 if (r300->screen->caps.has_tcl) {
1670 r300_init_vs_outputs(vs);
1671 r300_translate_vertex_shader(r300, vs);
1672 } else {
1673 r300_draw_init_vertex_shader(r300->draw, vs);
1674 }
1675
1676 return vs;
1677 }
1678
1679 static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
1680 {
1681 struct r300_context* r300 = r300_context(pipe);
1682 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1683
1684 if (vs == NULL) {
1685 r300->vs_state.state = NULL;
1686 return;
1687 }
1688 if (vs == r300->vs_state.state) {
1689 return;
1690 }
1691 r300->vs_state.state = vs;
1692
1693 /* The majority of the RS block bits is dependent on the vertex shader. */
1694 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */
1695
1696 if (r300->screen->caps.has_tcl) {
1697 r300->vs_state.dirty = TRUE;
1698 r300->vs_state.size =
1699 vs->code.length + 9 +
1700 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0);
1701
1702 if (vs->externals_count) {
1703 r300->vs_constants.dirty = TRUE;
1704 r300->vs_constants.size = vs->externals_count * 4 + 3;
1705 } else {
1706 r300->vs_constants.size = 0;
1707 }
1708
1709 r300->pvs_flush.dirty = TRUE;
1710 } else {
1711 draw_flush(r300->draw);
1712 draw_bind_vertex_shader(r300->draw,
1713 (struct draw_vertex_shader*)vs->draw_vs);
1714 }
1715 }
1716
1717 static void r300_delete_vs_state(struct pipe_context* pipe, void* shader)
1718 {
1719 struct r300_context* r300 = r300_context(pipe);
1720 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1721
1722 if (r300->screen->caps.has_tcl) {
1723 rc_constants_destroy(&vs->code.constants);
1724 } else {
1725 draw_delete_vertex_shader(r300->draw,
1726 (struct draw_vertex_shader*)vs->draw_vs);
1727 }
1728
1729 FREE((void*)vs->state.tokens);
1730 FREE(shader);
1731 }
1732
1733 static void r300_set_constant_buffer(struct pipe_context *pipe,
1734 uint shader, uint index,
1735 struct pipe_resource *buf)
1736 {
1737 struct r300_context* r300 = r300_context(pipe);
1738 struct r300_constant_buffer *cbuf;
1739 struct pipe_transfer *tr;
1740 float *mapped;
1741 int max_size = 0, max_size_bytes = 0, clamped_size = 0;
1742
1743 switch (shader) {
1744 case PIPE_SHADER_VERTEX:
1745 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state;
1746 max_size = 256;
1747 break;
1748 case PIPE_SHADER_FRAGMENT:
1749 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state;
1750 if (r300->screen->caps.is_r500) {
1751 max_size = 256;
1752 } else {
1753 max_size = 32;
1754 }
1755 break;
1756 default:
1757 assert(0);
1758 return;
1759 }
1760 max_size_bytes = max_size * 4 * sizeof(float);
1761
1762 if (buf == NULL || buf->width0 == 0 ||
1763 (mapped = pipe_buffer_map(pipe, buf, PIPE_TRANSFER_READ, &tr)) == NULL)
1764 {
1765 cbuf->count = 0;
1766 return;
1767 }
1768
1769 if (shader == PIPE_SHADER_FRAGMENT ||
1770 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) {
1771 assert((buf->width0 % (4 * sizeof(float))) == 0);
1772
1773 /* Check the size of the constant buffer. */
1774 /* XXX Subtract immediates and RC_STATE_* variables. */
1775 if (buf->width0 > max_size_bytes) {
1776 fprintf(stderr, "r300: Max size of the constant buffer is "
1777 "%i*4 floats.\n", max_size);
1778 }
1779
1780 clamped_size = MIN2(buf->width0, max_size_bytes);
1781 cbuf->count = clamped_size / (4 * sizeof(float));
1782
1783 if (shader == PIPE_SHADER_FRAGMENT && !r300->screen->caps.is_r500) {
1784 unsigned i,j;
1785
1786 /* Convert constants to float24. */
1787 for (i = 0; i < cbuf->count; i++)
1788 for (j = 0; j < 4; j++)
1789 cbuf->constants[i][j] = pack_float24(mapped[i*4+j]);
1790 } else {
1791 memcpy(cbuf->constants, mapped, clamped_size);
1792 }
1793 }
1794
1795 if (shader == PIPE_SHADER_VERTEX) {
1796 if (r300->screen->caps.has_tcl) {
1797 if (r300->vs_constants.size) {
1798 r300->vs_constants.dirty = TRUE;
1799 }
1800 r300->pvs_flush.dirty = TRUE;
1801 } else if (r300->draw) {
1802 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX,
1803 0, mapped, buf->width0);
1804 }
1805 } else if (shader == PIPE_SHADER_FRAGMENT) {
1806 r300->fs_constants.dirty = TRUE;
1807 }
1808
1809 pipe_buffer_unmap(pipe, buf, tr);
1810 }
1811
1812 void r300_init_state_functions(struct r300_context* r300)
1813 {
1814 r300->context.create_blend_state = r300_create_blend_state;
1815 r300->context.bind_blend_state = r300_bind_blend_state;
1816 r300->context.delete_blend_state = r300_delete_blend_state;
1817
1818 r300->context.set_blend_color = r300_set_blend_color;
1819
1820 r300->context.set_clip_state = r300_set_clip_state;
1821 r300->context.set_sample_mask = r300_set_sample_mask;
1822
1823 r300->context.set_constant_buffer = r300_set_constant_buffer;
1824
1825 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state;
1826 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
1827 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
1828
1829 r300->context.set_stencil_ref = r300_set_stencil_ref;
1830
1831 r300->context.set_framebuffer_state = r300_set_framebuffer_state;
1832
1833 r300->context.create_fs_state = r300_create_fs_state;
1834 r300->context.bind_fs_state = r300_bind_fs_state;
1835 r300->context.delete_fs_state = r300_delete_fs_state;
1836
1837 r300->context.set_polygon_stipple = r300_set_polygon_stipple;
1838
1839 r300->context.create_rasterizer_state = r300_create_rs_state;
1840 r300->context.bind_rasterizer_state = r300_bind_rs_state;
1841 r300->context.delete_rasterizer_state = r300_delete_rs_state;
1842
1843 r300->context.create_sampler_state = r300_create_sampler_state;
1844 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states;
1845 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures;
1846 r300->context.delete_sampler_state = r300_delete_sampler_state;
1847
1848 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views;
1849 r300->context.create_sampler_view = r300_create_sampler_view;
1850 r300->context.sampler_view_destroy = r300_sampler_view_destroy;
1851
1852 r300->context.set_scissor_state = r300_set_scissor_state;
1853
1854 r300->context.set_viewport_state = r300_set_viewport_state;
1855
1856 r300->context.set_vertex_buffers = r300_set_vertex_buffers;
1857
1858 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state;
1859 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state;
1860 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state;
1861
1862 r300->context.create_vs_state = r300_create_vs_state;
1863 r300->context.bind_vs_state = r300_bind_vs_state;
1864 r300->context.delete_vs_state = r300_delete_vs_state;
1865 }