r300/compiler: Implement the CONT opcode.
[mesa.git] / src / gallium / drivers / r300 / r300_state.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "draw/draw_context.h"
25
26 #include "util/u_blitter.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
31
32 #include "tgsi/tgsi_parse.h"
33
34 #include "pipe/p_config.h"
35
36 #include "r300_cb.h"
37 #include "r300_context.h"
38 #include "r300_emit.h"
39 #include "r300_reg.h"
40 #include "r300_screen.h"
41 #include "r300_screen_buffer.h"
42 #include "r300_state_inlines.h"
43 #include "r300_fs.h"
44 #include "r300_texture.h"
45 #include "r300_vs.h"
46 #include "r300_winsys.h"
47 #include "r300_hyperz.h"
48
49 /* r300_state: Functions used to intialize state context by translating
50 * Gallium state objects into semi-native r300 state objects. */
51
52 #define UPDATE_STATE(cso, atom) \
53 if (cso != atom.state) { \
54 atom.state = cso; \
55 atom.dirty = TRUE; \
56 }
57
58 static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA,
59 unsigned dstRGB, unsigned dstA)
60 {
61 /* If the blend equation is ADD or REVERSE_SUBTRACT,
62 * SRC_ALPHA == 0, and the following state is set, the colorbuffer
63 * will not be changed.
64 * Notice that the dst factors are the src factors inverted. */
65 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
66 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
67 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
68 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
69 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
70 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
71 srcA == PIPE_BLENDFACTOR_ZERO) &&
72 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
73 dstRGB == PIPE_BLENDFACTOR_ONE) &&
74 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
75 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
76 dstA == PIPE_BLENDFACTOR_ONE);
77 }
78
79 static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA,
80 unsigned dstRGB, unsigned dstA)
81 {
82 /* If the blend equation is ADD or REVERSE_SUBTRACT,
83 * SRC_ALPHA == 1, and the following state is set, the colorbuffer
84 * will not be changed.
85 * Notice that the dst factors are the src factors inverted. */
86 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
87 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
88 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
89 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
90 srcA == PIPE_BLENDFACTOR_ZERO) &&
91 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
92 dstRGB == PIPE_BLENDFACTOR_ONE) &&
93 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
94 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
95 dstA == PIPE_BLENDFACTOR_ONE);
96 }
97
98 static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA,
99 unsigned dstRGB, unsigned dstA)
100 {
101 /* If the blend equation is ADD or REVERSE_SUBTRACT,
102 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer
103 * will not be changed.
104 * Notice that the dst factors are the src factors inverted. */
105 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
106 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
107 (srcA == PIPE_BLENDFACTOR_ZERO) &&
108 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
109 dstRGB == PIPE_BLENDFACTOR_ONE) &&
110 (dstA == PIPE_BLENDFACTOR_ONE);
111 }
112
113 static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA,
114 unsigned dstRGB, unsigned dstA)
115 {
116 /* If the blend equation is ADD or REVERSE_SUBTRACT,
117 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer
118 * will not be changed.
119 * Notice that the dst factors are the src factors inverted. */
120 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
121 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
122 (srcA == PIPE_BLENDFACTOR_ZERO) &&
123 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
124 dstRGB == PIPE_BLENDFACTOR_ONE) &&
125 (dstA == PIPE_BLENDFACTOR_ONE);
126 }
127
128 static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA,
129 unsigned dstRGB, unsigned dstA)
130 {
131 /* If the blend equation is ADD or REVERSE_SUBTRACT,
132 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set,
133 * the colorbuffer will not be changed.
134 * Notice that the dst factors are the src factors inverted. */
135 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
136 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
137 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
138 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
139 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
140 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
141 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
142 srcA == PIPE_BLENDFACTOR_ZERO) &&
143 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
144 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
145 dstRGB == PIPE_BLENDFACTOR_ONE) &&
146 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
147 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
148 dstA == PIPE_BLENDFACTOR_ONE);
149 }
150
151 static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA,
152 unsigned dstRGB, unsigned dstA)
153 {
154 /* If the blend equation is ADD or REVERSE_SUBTRACT,
155 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set,
156 * the colorbuffer will not be changed.
157 * Notice that the dst factors are the src factors inverted. */
158 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
159 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
160 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
161 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
162 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
163 srcA == PIPE_BLENDFACTOR_ZERO) &&
164 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
165 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
166 dstRGB == PIPE_BLENDFACTOR_ONE) &&
167 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
168 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
169 dstA == PIPE_BLENDFACTOR_ONE);
170 }
171
172 static unsigned bgra_cmask(unsigned mask)
173 {
174 /* Gallium uses RGBA color ordering while R300 expects BGRA. */
175
176 return ((mask & PIPE_MASK_R) << 2) |
177 ((mask & PIPE_MASK_B) >> 2) |
178 (mask & (PIPE_MASK_G | PIPE_MASK_A));
179 }
180
181 /* Create a new blend state based on the CSO blend state.
182 *
183 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
184 static void* r300_create_blend_state(struct pipe_context* pipe,
185 const struct pipe_blend_state* state)
186 {
187 struct r300_screen* r300screen = r300_screen(pipe->screen);
188 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
189 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */
190 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */
191 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */
192 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */
193 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */
194 CB_LOCALS;
195
196 if (state->rt[0].blend_enable)
197 {
198 unsigned eqRGB = state->rt[0].rgb_func;
199 unsigned srcRGB = state->rt[0].rgb_src_factor;
200 unsigned dstRGB = state->rt[0].rgb_dst_factor;
201
202 unsigned eqA = state->rt[0].alpha_func;
203 unsigned srcA = state->rt[0].alpha_src_factor;
204 unsigned dstA = state->rt[0].alpha_dst_factor;
205
206 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
207 * this is just the crappy D3D naming */
208 blend_control = R300_ALPHA_BLEND_ENABLE |
209 r300_translate_blend_function(eqRGB) |
210 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) |
211 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT);
212
213 /* Optimization: some operations do not require the destination color.
214 *
215 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled,
216 * otherwise blending gives incorrect results. It seems to be
217 * a hardware bug. */
218 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN ||
219 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX ||
220 dstRGB != PIPE_BLENDFACTOR_ZERO ||
221 dstA != PIPE_BLENDFACTOR_ZERO ||
222 srcRGB == PIPE_BLENDFACTOR_DST_COLOR ||
223 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA ||
224 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR ||
225 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
226 srcA == PIPE_BLENDFACTOR_DST_COLOR ||
227 srcA == PIPE_BLENDFACTOR_DST_ALPHA ||
228 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR ||
229 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
230 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) {
231 /* Enable reading from the colorbuffer. */
232 blend_control |= R300_READ_ENABLE;
233
234 if (r300screen->caps.is_r500) {
235 /* Optimization: Depending on incoming pixels, we can
236 * conditionally disable the reading in hardware... */
237 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN &&
238 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) {
239 /* Disable reading if SRC_ALPHA == 0. */
240 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
241 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
242 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
243 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
244 dstA == PIPE_BLENDFACTOR_ZERO)) {
245 blend_control |= R500_SRC_ALPHA_0_NO_READ;
246 }
247
248 /* Disable reading if SRC_ALPHA == 1. */
249 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
250 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
251 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
252 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
253 dstA == PIPE_BLENDFACTOR_ZERO)) {
254 blend_control |= R500_SRC_ALPHA_1_NO_READ;
255 }
256 }
257 }
258 }
259
260 /* Optimization: discard pixels which don't change the colorbuffer.
261 *
262 * The code below is non-trivial and some math is involved.
263 *
264 * Discarding pixels must be disabled when FP16 AA is enabled.
265 * This is a hardware bug. Also, this implementation wouldn't work
266 * with FP blending enabled and equation clamping disabled.
267 *
268 * Equations other than ADD are rarely used and therefore won't be
269 * optimized. */
270 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) &&
271 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) {
272 /* ADD: X+Y
273 * REVERSE_SUBTRACT: Y-X
274 *
275 * The idea is:
276 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1,
277 * then CB will not be changed.
278 *
279 * Given the srcFactor and dstFactor variables, we can derive
280 * what src and dst should be equal to and discard appropriate
281 * pixels.
282 */
283 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) {
284 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
285 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA,
286 dstRGB, dstA)) {
287 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1;
288 } else if (blend_discard_if_src_color_0(srcRGB, srcA,
289 dstRGB, dstA)) {
290 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0;
291 } else if (blend_discard_if_src_color_1(srcRGB, srcA,
292 dstRGB, dstA)) {
293 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1;
294 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA,
295 dstRGB, dstA)) {
296 blend_control |=
297 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0;
298 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA,
299 dstRGB, dstA)) {
300 blend_control |=
301 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1;
302 }
303 }
304
305 /* separate alpha */
306 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
307 blend_control |= R300_SEPARATE_ALPHA_ENABLE;
308 alpha_blend_control =
309 r300_translate_blend_function(eqA) |
310 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) |
311 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT);
312 }
313 }
314
315 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
316 if (state->logicop_enable) {
317 rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
318 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
319 }
320
321 /* Color channel masks for all MRTs. */
322 color_channel_mask = bgra_cmask(state->rt[0].colormask);
323 if (r300screen->caps.is_r500 && state->independent_blend_enable) {
324 if (state->rt[1].blend_enable) {
325 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4;
326 }
327 if (state->rt[2].blend_enable) {
328 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8;
329 }
330 if (state->rt[3].blend_enable) {
331 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12;
332 }
333 }
334
335 /* Neither fglrx nor classic r300 ever set this, regardless of dithering
336 * state. Since it's an optional implementation detail, we can leave it
337 * out and never dither.
338 *
339 * This could be revisited if we ever get quality or conformance hints.
340 *
341 if (state->dither) {
342 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
343 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
344 }
345 */
346
347 /* Build a command buffer. */
348 BEGIN_CB(blend->cb, 8);
349 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
350 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
351 OUT_CB(blend_control);
352 OUT_CB(alpha_blend_control);
353 OUT_CB(color_channel_mask);
354 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
355 END_CB;
356
357 /* The same as above, but with no colorbuffer reads and writes. */
358 BEGIN_CB(blend->cb_no_readwrite, 8);
359 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
360 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
361 OUT_CB(0);
362 OUT_CB(0);
363 OUT_CB(0);
364 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
365 END_CB;
366
367 return (void*)blend;
368 }
369
370 /* Bind blend state. */
371 static void r300_bind_blend_state(struct pipe_context* pipe,
372 void* state)
373 {
374 struct r300_context* r300 = r300_context(pipe);
375
376 UPDATE_STATE(state, r300->blend_state);
377 }
378
379 /* Free blend state. */
380 static void r300_delete_blend_state(struct pipe_context* pipe,
381 void* state)
382 {
383 FREE(state);
384 }
385
386 /* Convert float to 10bit integer */
387 static unsigned float_to_fixed10(float f)
388 {
389 return CLAMP((unsigned)(f * 1023.9f), 0, 1023);
390 }
391
392 /* Set blend color.
393 * Setup both R300 and R500 registers, figure out later which one to write. */
394 static void r300_set_blend_color(struct pipe_context* pipe,
395 const struct pipe_blend_color* color)
396 {
397 struct r300_context* r300 = r300_context(pipe);
398 struct r300_blend_color_state* state =
399 (struct r300_blend_color_state*)r300->blend_color_state.state;
400 CB_LOCALS;
401
402 if (r300->screen->caps.is_r500) {
403 /* XXX if FP16 blending is enabled, we should use the FP16 format */
404 BEGIN_CB(state->cb, 3);
405 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
406 OUT_CB(float_to_fixed10(color->color[0]) |
407 (float_to_fixed10(color->color[3]) << 16));
408 OUT_CB(float_to_fixed10(color->color[2]) |
409 (float_to_fixed10(color->color[1]) << 16));
410 END_CB;
411 } else {
412 union util_color uc;
413 util_pack_color(color->color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
414
415 BEGIN_CB(state->cb, 2);
416 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui);
417 END_CB;
418 }
419
420 r300->blend_color_state.dirty = TRUE;
421 }
422
423 static void r300_set_clip_state(struct pipe_context* pipe,
424 const struct pipe_clip_state* state)
425 {
426 struct r300_context* r300 = r300_context(pipe);
427 struct r300_clip_state *clip =
428 (struct r300_clip_state*)r300->clip_state.state;
429 CB_LOCALS;
430
431 clip->clip = *state;
432
433 if (r300->screen->caps.has_tcl) {
434 r300->clip_state.size = 2 + !!state->nr * 3 + state->nr * 4;
435
436 BEGIN_CB(clip->cb, r300->clip_state.size);
437 if (state->nr) {
438 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG,
439 (r300->screen->caps.is_r500 ?
440 R500_PVS_UCP_START : R300_PVS_UCP_START));
441 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, state->nr * 4);
442 OUT_CB_TABLE(state->ucp, state->nr * 4);
443 }
444 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) |
445 R300_PS_UCP_MODE_CLIP_AS_TRIFAN |
446 (state->depth_clamp ? R300_CLIP_DISABLE : 0));
447 END_CB;
448
449 r300->clip_state.dirty = TRUE;
450 } else {
451 draw_set_clip_state(r300->draw, state);
452 }
453 }
454
455 static void
456 r300_set_sample_mask(struct pipe_context *pipe,
457 unsigned sample_mask)
458 {
459 }
460
461
462 /* Create a new depth, stencil, and alpha state based on the CSO dsa state.
463 *
464 * This contains the depth buffer, stencil buffer, alpha test, and such.
465 * On the Radeon, depth and stencil buffer setup are intertwined, which is
466 * the reason for some of the strange-looking assignments across registers. */
467 static void*
468 r300_create_dsa_state(struct pipe_context* pipe,
469 const struct pipe_depth_stencil_alpha_state* state)
470 {
471 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps;
472 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state);
473 CB_LOCALS;
474
475 dsa->dsa = *state;
476
477 /* Depth test setup. - separate write mask depth for decomp flush */
478 if (state->depth.writemask) {
479 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE;
480 }
481
482 if (state->depth.enabled) {
483 dsa->z_buffer_control |= R300_Z_ENABLE;
484
485 dsa->z_stencil_control |=
486 (r300_translate_depth_stencil_function(state->depth.func) <<
487 R300_Z_FUNC_SHIFT);
488 }
489
490 /* Stencil buffer setup. */
491 if (state->stencil[0].enabled) {
492 dsa->z_buffer_control |= R300_STENCIL_ENABLE;
493 dsa->z_stencil_control |=
494 (r300_translate_depth_stencil_function(state->stencil[0].func) <<
495 R300_S_FRONT_FUNC_SHIFT) |
496 (r300_translate_stencil_op(state->stencil[0].fail_op) <<
497 R300_S_FRONT_SFAIL_OP_SHIFT) |
498 (r300_translate_stencil_op(state->stencil[0].zpass_op) <<
499 R300_S_FRONT_ZPASS_OP_SHIFT) |
500 (r300_translate_stencil_op(state->stencil[0].zfail_op) <<
501 R300_S_FRONT_ZFAIL_OP_SHIFT);
502
503 dsa->stencil_ref_mask =
504 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
505 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
506
507 if (state->stencil[1].enabled) {
508 dsa->two_sided = TRUE;
509
510 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK;
511 dsa->z_stencil_control |=
512 (r300_translate_depth_stencil_function(state->stencil[1].func) <<
513 R300_S_BACK_FUNC_SHIFT) |
514 (r300_translate_stencil_op(state->stencil[1].fail_op) <<
515 R300_S_BACK_SFAIL_OP_SHIFT) |
516 (r300_translate_stencil_op(state->stencil[1].zpass_op) <<
517 R300_S_BACK_ZPASS_OP_SHIFT) |
518 (r300_translate_stencil_op(state->stencil[1].zfail_op) <<
519 R300_S_BACK_ZFAIL_OP_SHIFT);
520
521 dsa->stencil_ref_bf =
522 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) |
523 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
524
525 if (caps->is_r500) {
526 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
527 } else {
528 dsa->two_sided_stencil_ref =
529 (state->stencil[0].valuemask != state->stencil[1].valuemask ||
530 state->stencil[0].writemask != state->stencil[1].writemask);
531 }
532 }
533 }
534
535 /* Alpha test setup. */
536 if (state->alpha.enabled) {
537 dsa->alpha_function =
538 r300_translate_alpha_function(state->alpha.func) |
539 R300_FG_ALPHA_FUNC_ENABLE;
540
541 /* We could use 10bit alpha ref but who needs that? */
542 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value);
543
544 if (caps->is_r500)
545 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT;
546 }
547
548 BEGIN_CB(&dsa->cb_begin, 8);
549 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
550 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
551 OUT_CB(dsa->z_buffer_control);
552 OUT_CB(dsa->z_stencil_control);
553 OUT_CB(dsa->stencil_ref_mask);
554 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
555 END_CB;
556
557 BEGIN_CB(dsa->cb_no_readwrite, 8);
558 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
559 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
560 OUT_CB(0);
561 OUT_CB(0);
562 OUT_CB(0);
563 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
564 END_CB;
565
566 return (void*)dsa;
567 }
568
569 static void r300_dsa_inject_stencilref(struct r300_context *r300)
570 {
571 struct r300_dsa_state *dsa =
572 (struct r300_dsa_state*)r300->dsa_state.state;
573
574 if (!dsa)
575 return;
576
577 dsa->stencil_ref_mask =
578 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) |
579 r300->stencil_ref.ref_value[0];
580 dsa->stencil_ref_bf =
581 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) |
582 r300->stencil_ref.ref_value[1];
583 }
584
585 /* Bind DSA state. */
586 static void r300_bind_dsa_state(struct pipe_context* pipe,
587 void* state)
588 {
589 struct r300_context* r300 = r300_context(pipe);
590
591 if (!state) {
592 return;
593 }
594
595 UPDATE_STATE(state, r300->dsa_state);
596
597 r300->hyperz_state.dirty = TRUE; /* Will be updated before the emission. */
598 r300_dsa_inject_stencilref(r300);
599 }
600
601 /* Free DSA state. */
602 static void r300_delete_dsa_state(struct pipe_context* pipe,
603 void* state)
604 {
605 FREE(state);
606 }
607
608 static void r300_set_stencil_ref(struct pipe_context* pipe,
609 const struct pipe_stencil_ref* sr)
610 {
611 struct r300_context* r300 = r300_context(pipe);
612
613 r300->stencil_ref = *sr;
614
615 r300_dsa_inject_stencilref(r300);
616 r300->dsa_state.dirty = TRUE;
617 }
618
619 static void r300_tex_set_tiling_flags(struct r300_context *r300,
620 struct r300_texture *tex, unsigned level)
621 {
622 /* Check if the macrotile flag needs to be changed.
623 * Skip changing the flags otherwise. */
624 if (tex->desc.macrotile[tex->surface_level] !=
625 tex->desc.macrotile[level]) {
626 /* Tiling determines how DRM treats the buffer data.
627 * We must flush CS when changing it if the buffer is referenced. */
628 if (r300->rws->cs_is_buffer_referenced(r300->cs,
629 tex->buffer, R300_REF_CS))
630 r300->context.flush(&r300->context, 0, NULL);
631
632 r300->rws->buffer_set_tiling(r300->rws, tex->buffer,
633 tex->desc.microtile, tex->desc.macrotile[level],
634 tex->desc.stride_in_bytes[0]);
635
636 tex->surface_level = level;
637 }
638 }
639
640 /* This switcheroo is needed just because of goddamned MACRO_SWITCH. */
641 static void r300_fb_set_tiling_flags(struct r300_context *r300,
642 const struct pipe_framebuffer_state *state)
643 {
644 unsigned i;
645
646 /* Set tiling flags for new surfaces. */
647 for (i = 0; i < state->nr_cbufs; i++) {
648 r300_tex_set_tiling_flags(r300,
649 r300_texture(state->cbufs[i]->texture),
650 state->cbufs[i]->level);
651 }
652 if (state->zsbuf) {
653 r300_tex_set_tiling_flags(r300,
654 r300_texture(state->zsbuf->texture),
655 state->zsbuf->level);
656 }
657 }
658
659 static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index,
660 const char *binding)
661 {
662 struct pipe_resource *tex = surf->texture;
663 struct r300_texture *rtex = r300_texture(tex);
664
665 fprintf(stderr,
666 "r300: %s[%i] Dim: %ix%i, Offset: %i, ZSlice: %i, "
667 "Face: %i, Level: %i, Format: %s\n"
668
669 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, "
670 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n",
671
672 binding, index, surf->width, surf->height, surf->offset,
673 surf->zslice, surf->face, surf->level,
674 util_format_short_name(surf->format),
675
676 rtex->desc.macrotile[0] ? "YES" : " NO",
677 rtex->desc.microtile ? "YES" : " NO",
678 rtex->desc.stride_in_pixels[0],
679 tex->width0, tex->height0, tex->depth0,
680 tex->last_level, util_format_short_name(tex->format));
681 }
682
683 void r300_mark_fb_state_dirty(struct r300_context *r300,
684 enum r300_fb_state_change change)
685 {
686 struct pipe_framebuffer_state *state = r300->fb_state.state;
687 boolean has_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
688
689 /* What is marked as dirty depends on the enum r300_fb_state_change. */
690 r300->gpu_flush.dirty = TRUE;
691 r300->fb_state.dirty = TRUE;
692 r300->hyperz_state.dirty = TRUE;
693
694 if (change == R300_CHANGED_FB_STATE) {
695 r300->aa_state.dirty = TRUE;
696 r300->fb_state_pipelined.dirty = TRUE;
697 }
698
699 /* Now compute the fb_state atom size. */
700 r300->fb_state.size = 2 + (8 * state->nr_cbufs);
701
702 if (r300->cbzb_clear)
703 r300->fb_state.size += 10;
704 else if (state->zsbuf) {
705 r300->fb_state.size += 10;
706 if (has_hyperz)
707 r300->fb_state.size += r300->screen->caps.hiz_ram ? 8 : 4;
708 }
709
710 /* The size of the rest of atoms stays the same. */
711 }
712
713 static void
714 r300_set_framebuffer_state(struct pipe_context* pipe,
715 const struct pipe_framebuffer_state* state)
716 {
717 struct r300_context* r300 = r300_context(pipe);
718 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
719 struct pipe_framebuffer_state *old_state = r300->fb_state.state;
720 boolean has_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
721 unsigned max_width, max_height, i;
722 uint32_t zbuffer_bpp = 0;
723 int blocksize;
724
725 if (r300->screen->caps.is_r500) {
726 max_width = max_height = 4096;
727 } else if (r300->screen->caps.is_r400) {
728 max_width = max_height = 4021;
729 } else {
730 max_width = max_height = 2560;
731 }
732
733 if (state->width > max_width || state->height > max_height) {
734 fprintf(stderr, "r300: Implementation error: Render targets are too "
735 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__);
736 return;
737 }
738
739 /* If nr_cbufs is changed from zero to non-zero or vice versa... */
740 if (!!old_state->nr_cbufs != !!state->nr_cbufs) {
741 r300->blend_state.dirty = TRUE;
742 }
743 /* If zsbuf is set from NULL to non-NULL or vice versa.. */
744 if (!!old_state->zsbuf != !!state->zsbuf) {
745 r300->dsa_state.dirty = TRUE;
746 }
747
748 /* The tiling flags are dependent on the surface miplevel, unfortunately. */
749 r300_fb_set_tiling_flags(r300, state);
750
751 util_assign_framebuffer_state(r300->fb_state.state, state);
752
753 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE);
754
755 r300->hiz_enable = false;
756 r300->z_fastfill = false;
757 r300->z_compression = false;
758
759 if (state->zsbuf) {
760 blocksize = util_format_get_blocksize(state->zsbuf->texture->format);
761 switch (blocksize) {
762 case 2:
763 zbuffer_bpp = 16;
764 break;
765 case 4:
766 zbuffer_bpp = 24;
767 break;
768 }
769 if (has_hyperz) {
770 struct r300_surface *zs_surf = r300_surface(state->zsbuf);
771 struct r300_texture *tex;
772 int compress = r300->screen->caps.is_rv350 ? RV350_Z_COMPRESS_88 : R300_Z_COMPRESS_44;
773 int level = zs_surf->base.level;
774
775 tex = r300_texture(zs_surf->base.texture);
776
777 /* work out whether we can support hiz on this buffer */
778 r300_hiz_alloc_block(r300, zs_surf);
779
780 /* work out whether we can support zmask features on this buffer */
781 r300_zmask_alloc_block(r300, zs_surf, compress);
782
783 if (tex->hiz_mem[level]) {
784 r300->hiz_enable = 1;
785 }
786
787 if (tex->zmask_mem[level]) {
788 r300->z_fastfill = 1;
789 /* compression causes hangs on 16-bit */
790 if (zbuffer_bpp == 24)
791 r300->z_compression = compress;
792 }
793 DBG(r300, DBG_HYPERZ,
794 "hyper-z features: hiz: %d @ %08x z-compression: %d z-fastfill: %d @ %08x\n", r300->hiz_enable,
795 tex->hiz_mem[level] ? tex->hiz_mem[level]->ofs : 0xdeadbeef,
796 r300->z_compression, r300->z_fastfill,
797 tex->zmask_mem[level] ? tex->zmask_mem[level]->ofs : 0xdeadbeef);
798 }
799
800 /* Polygon offset depends on the zbuffer bit depth. */
801 if (r300->zbuffer_bpp != zbuffer_bpp) {
802 r300->zbuffer_bpp = zbuffer_bpp;
803
804 if (r300->polygon_offset_enabled)
805 r300->rs_state.dirty = TRUE;
806 }
807 }
808
809 /* Set up AA config. */
810 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
811 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) {
812 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE;
813
814 switch (state->cbufs[0]->texture->nr_samples) {
815 case 2:
816 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2;
817 break;
818 case 3:
819 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3;
820 break;
821 case 4:
822 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4;
823 break;
824 case 6:
825 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6;
826 break;
827 }
828 } else {
829 aa->aa_config = 0;
830 }
831 }
832
833 if (DBG_ON(r300, DBG_FB)) {
834 fprintf(stderr, "r300: set_framebuffer_state:\n");
835 for (i = 0; i < state->nr_cbufs; i++) {
836 r300_print_fb_surf_info(state->cbufs[i], i, "CB");
837 }
838 if (state->zsbuf) {
839 r300_print_fb_surf_info(state->zsbuf, 0, "ZB");
840 }
841 }
842 }
843
844 /* Create fragment shader state. */
845 static void* r300_create_fs_state(struct pipe_context* pipe,
846 const struct pipe_shader_state* shader)
847 {
848 struct r300_fragment_shader* fs = NULL;
849
850 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader);
851
852 /* Copy state directly into shader. */
853 fs->state = *shader;
854 fs->state.tokens = tgsi_dup_tokens(shader->tokens);
855
856 return (void*)fs;
857 }
858
859 void r300_mark_fs_code_dirty(struct r300_context *r300)
860 {
861 struct r300_fragment_shader* fs = r300_fs(r300);
862
863 r300->fs.dirty = TRUE;
864 r300->fs_rc_constant_state.dirty = TRUE;
865 r300->fs_constants.dirty = TRUE;
866 r300->fs.size = fs->shader->cb_code_size;
867
868 if (r300->screen->caps.is_r500) {
869 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7;
870 r300->fs_constants.size = fs->shader->externals_count * 4 + 3;
871 } else {
872 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5;
873 r300->fs_constants.size = fs->shader->externals_count * 4 + 1;
874 }
875 }
876
877 /* Bind fragment shader state. */
878 static void r300_bind_fs_state(struct pipe_context* pipe, void* shader)
879 {
880 struct r300_context* r300 = r300_context(pipe);
881 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
882
883 if (fs == NULL) {
884 r300->fs.state = NULL;
885 return;
886 }
887
888 r300->fs.state = fs;
889 r300_pick_fragment_shader(r300);
890 r300_mark_fs_code_dirty(r300);
891
892 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */
893 }
894
895 /* Delete fragment shader state. */
896 static void r300_delete_fs_state(struct pipe_context* pipe, void* shader)
897 {
898 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
899 struct r300_fragment_shader_code *tmp, *ptr = fs->first;
900
901 while (ptr) {
902 tmp = ptr;
903 ptr = ptr->next;
904 rc_constants_destroy(&tmp->code.constants);
905 FREE(tmp->cb_code);
906 FREE(tmp);
907 }
908 FREE((void*)fs->state.tokens);
909 FREE(shader);
910 }
911
912 static void r300_set_polygon_stipple(struct pipe_context* pipe,
913 const struct pipe_poly_stipple* state)
914 {
915 /* XXX no idea how to set this up, but not terribly important */
916 }
917
918 /* Create a new rasterizer state based on the CSO rasterizer state.
919 *
920 * This is a very large chunk of state, and covers most of the graphics
921 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
922 *
923 * In a not entirely unironic sidenote, this state has nearly nothing to do
924 * with the actual block on the Radeon called the rasterizer (RS). */
925 static void* r300_create_rs_state(struct pipe_context* pipe,
926 const struct pipe_rasterizer_state* state)
927 {
928 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state);
929 int i;
930 float psiz;
931 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */
932 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */
933 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */
934 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */
935 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */
936 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */
937 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */
938 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */
939 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */
940 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */
941
942 /* Specifies top of Raster pipe specific enable controls,
943 * i.e. texture coordinates stuffing for points, lines, triangles */
944 uint32_t stuffing_enable; /* R300_GB_ENABLE: 0x4008 */
945
946 /* Point sprites texture coordinates, 0: lower left, 1: upper right */
947 float point_texcoord_left; /* R300_GA_POINT_S0: 0x4200 */
948 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */
949 float point_texcoord_right; /* R300_GA_POINT_S1: 0x4208 */
950 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */
951 CB_LOCALS;
952
953 /* Copy rasterizer state. */
954 rs->rs = *state;
955 rs->rs_draw = *state;
956
957 /* Override some states for Draw. */
958 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */
959
960 #ifdef PIPE_ARCH_LITTLE_ENDIAN
961 vap_control_status = R300_VC_NO_SWAP;
962 #else
963 vap_control_status = R300_VC_32BIT_SWAP;
964 #endif
965
966 /* If no TCL engine is present, turn off the HW TCL. */
967 if (!r300_screen(pipe->screen)->caps.has_tcl) {
968 vap_control_status |= R300_VAP_TCL_BYPASS;
969 }
970
971 /* Point size width and height. */
972 point_size =
973 pack_float_16_6x(state->point_size) |
974 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT);
975
976 /* Point size clamping. */
977 if (state->point_size_per_vertex) {
978 /* Per-vertex point size.
979 * Clamp to [0, max FB size] */
980 psiz = pipe->screen->get_paramf(pipe->screen,
981 PIPE_CAP_MAX_POINT_WIDTH);
982 point_minmax =
983 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT;
984 } else {
985 /* We cannot disable the point-size vertex output,
986 * so clamp it. */
987 psiz = state->point_size;
988 point_minmax =
989 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) |
990 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT);
991 }
992
993 /* Line control. */
994 line_control = pack_float_16_6x(state->line_width) |
995 R300_GA_LINE_CNTL_END_TYPE_COMP;
996
997 /* Enable polygon mode */
998 polygon_mode = 0;
999 if (state->fill_front != PIPE_POLYGON_MODE_FILL ||
1000 state->fill_back != PIPE_POLYGON_MODE_FILL) {
1001 polygon_mode = R300_GA_POLY_MODE_DUAL;
1002 }
1003
1004 /* Front face */
1005 if (state->front_ccw)
1006 cull_mode = R300_FRONT_FACE_CCW;
1007 else
1008 cull_mode = R300_FRONT_FACE_CW;
1009
1010 /* Polygon offset */
1011 polygon_offset_enable = 0;
1012 if (util_get_offset(state, state->fill_front)) {
1013 polygon_offset_enable |= R300_FRONT_ENABLE;
1014 }
1015 if (util_get_offset(state, state->fill_back)) {
1016 polygon_offset_enable |= R300_BACK_ENABLE;
1017 }
1018
1019 rs->polygon_offset_enable = polygon_offset_enable != 0;
1020
1021 /* Polygon mode */
1022 if (polygon_mode) {
1023 polygon_mode |=
1024 r300_translate_polygon_mode_front(state->fill_front);
1025 polygon_mode |=
1026 r300_translate_polygon_mode_back(state->fill_back);
1027 }
1028
1029 if (state->cull_face & PIPE_FACE_FRONT) {
1030 cull_mode |= R300_CULL_FRONT;
1031 }
1032 if (state->cull_face & PIPE_FACE_BACK) {
1033 cull_mode |= R300_CULL_BACK;
1034 }
1035
1036 if (state->line_stipple_enable) {
1037 line_stipple_config =
1038 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE |
1039 (fui((float)state->line_stipple_factor) &
1040 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK);
1041 /* XXX this might need to be scaled up */
1042 line_stipple_value = state->line_stipple_pattern;
1043 } else {
1044 line_stipple_config = 0;
1045 line_stipple_value = 0;
1046 }
1047
1048 if (state->flatshade) {
1049 rs->color_control = R300_SHADE_MODEL_FLAT;
1050 } else {
1051 rs->color_control = R300_SHADE_MODEL_SMOOTH;
1052 }
1053
1054 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
1055
1056 /* Point sprites */
1057 stuffing_enable = 0;
1058 if (state->sprite_coord_enable) {
1059 stuffing_enable = R300_GB_POINT_STUFF_ENABLE;
1060 for (i = 0; i < 8; i++) {
1061 if (state->sprite_coord_enable & (1 << i))
1062 stuffing_enable |=
1063 R300_GB_TEX_ST << (R300_GB_TEX0_SOURCE_SHIFT + (i*2));
1064 }
1065
1066 point_texcoord_left = 0.0f;
1067 point_texcoord_right = 1.0f;
1068
1069 switch (state->sprite_coord_mode) {
1070 case PIPE_SPRITE_COORD_UPPER_LEFT:
1071 point_texcoord_top = 0.0f;
1072 point_texcoord_bottom = 1.0f;
1073 break;
1074 case PIPE_SPRITE_COORD_LOWER_LEFT:
1075 point_texcoord_top = 1.0f;
1076 point_texcoord_bottom = 0.0f;
1077 break;
1078 }
1079 }
1080
1081 /* Build the main command buffer. */
1082 BEGIN_CB(rs->cb_main, 25);
1083 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status);
1084 OUT_CB_REG(R300_GA_POINT_SIZE, point_size);
1085 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2);
1086 OUT_CB(point_minmax);
1087 OUT_CB(line_control);
1088 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
1089 OUT_CB(polygon_offset_enable);
1090 rs->cull_mode_index = 9;
1091 OUT_CB(cull_mode);
1092 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config);
1093 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value);
1094 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode);
1095 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule);
1096 OUT_CB_REG(R300_GB_ENABLE, stuffing_enable);
1097 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4);
1098 OUT_CB_32F(point_texcoord_left);
1099 OUT_CB_32F(point_texcoord_bottom);
1100 OUT_CB_32F(point_texcoord_right);
1101 OUT_CB_32F(point_texcoord_top);
1102 END_CB;
1103
1104 /* Build the two command buffers for polygon offset setup. */
1105 if (polygon_offset_enable) {
1106 float scale = state->offset_scale * 12;
1107 float offset = state->offset_units * 4;
1108
1109 BEGIN_CB(rs->cb_poly_offset_zb16, 5);
1110 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1111 OUT_CB_32F(scale);
1112 OUT_CB_32F(offset);
1113 OUT_CB_32F(scale);
1114 OUT_CB_32F(offset);
1115 END_CB;
1116
1117 offset = state->offset_units * 2;
1118
1119 BEGIN_CB(rs->cb_poly_offset_zb24, 5);
1120 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1121 OUT_CB_32F(scale);
1122 OUT_CB_32F(offset);
1123 OUT_CB_32F(scale);
1124 OUT_CB_32F(offset);
1125 END_CB;
1126 }
1127
1128 return (void*)rs;
1129 }
1130
1131 /* Bind rasterizer state. */
1132 static void r300_bind_rs_state(struct pipe_context* pipe, void* state)
1133 {
1134 struct r300_context* r300 = r300_context(pipe);
1135 struct r300_rs_state* rs = (struct r300_rs_state*)state;
1136 int last_sprite_coord_enable = r300->sprite_coord_enable;
1137 boolean last_two_sided_color = r300->two_sided_color;
1138
1139 if (r300->draw && rs) {
1140 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state);
1141 }
1142
1143 if (rs) {
1144 r300->polygon_offset_enabled = rs->polygon_offset_enable;
1145 r300->sprite_coord_enable = rs->rs.sprite_coord_enable;
1146 r300->two_sided_color = rs->rs.light_twoside;
1147 } else {
1148 r300->polygon_offset_enabled = FALSE;
1149 r300->sprite_coord_enable = 0;
1150 r300->two_sided_color = FALSE;
1151 }
1152
1153 UPDATE_STATE(state, r300->rs_state);
1154 r300->rs_state.size = 25 + (r300->polygon_offset_enabled ? 5 : 0);
1155
1156 if (last_sprite_coord_enable != r300->sprite_coord_enable ||
1157 last_two_sided_color != r300->two_sided_color) {
1158 r300->rs_block_state.dirty = TRUE;
1159 }
1160 }
1161
1162 /* Free rasterizer state. */
1163 static void r300_delete_rs_state(struct pipe_context* pipe, void* state)
1164 {
1165 FREE(state);
1166 }
1167
1168 static void*
1169 r300_create_sampler_state(struct pipe_context* pipe,
1170 const struct pipe_sampler_state* state)
1171 {
1172 struct r300_context* r300 = r300_context(pipe);
1173 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
1174 boolean is_r500 = r300->screen->caps.is_r500;
1175 int lod_bias;
1176 union util_color uc;
1177
1178 sampler->state = *state;
1179
1180 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG
1181 * or MIN filter is NEAREST. Since texwrap produces same results
1182 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */
1183 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST ||
1184 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) {
1185 /* Wrap S. */
1186 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP)
1187 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1188 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP)
1189 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1190
1191 /* Wrap T. */
1192 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP)
1193 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1194 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP)
1195 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1196
1197 /* Wrap R. */
1198 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP)
1199 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1200 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP)
1201 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1202 }
1203
1204 sampler->filter0 |=
1205 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) |
1206 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) |
1207 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT);
1208
1209 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter,
1210 state->mag_img_filter,
1211 state->min_mip_filter,
1212 state->max_anisotropy > 0);
1213
1214 sampler->filter0 |= r300_anisotropy(state->max_anisotropy);
1215
1216 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */
1217 /* We must pass these to the merge function to clamp them properly. */
1218 sampler->min_lod = MAX2((unsigned)state->min_lod, 0);
1219 sampler->max_lod = MAX2((unsigned)ceilf(state->max_lod), 0);
1220
1221 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1);
1222
1223 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK;
1224
1225 /* This is very high quality anisotropic filtering for R5xx.
1226 * It's good for benchmarking the performance of texturing but
1227 * in practice we don't want to slow down the driver because it's
1228 * a pretty good performance killer. Feel free to play with it. */
1229 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) {
1230 sampler->filter1 |= r500_anisotropy(state->max_anisotropy);
1231 }
1232
1233 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1234 sampler->border_color = uc.ui;
1235
1236 /* R500-specific fixups and optimizations */
1237 if (r300->screen->caps.is_r500) {
1238 sampler->filter1 |= R500_BORDER_FIX;
1239 }
1240
1241 return (void*)sampler;
1242 }
1243
1244 static void r300_bind_sampler_states(struct pipe_context* pipe,
1245 unsigned count,
1246 void** states)
1247 {
1248 struct r300_context* r300 = r300_context(pipe);
1249 struct r300_textures_state* state =
1250 (struct r300_textures_state*)r300->textures_state.state;
1251 unsigned tex_units = r300->screen->caps.num_tex_units;
1252
1253 if (count > tex_units) {
1254 return;
1255 }
1256
1257 memcpy(state->sampler_states, states, sizeof(void*) * count);
1258 state->sampler_state_count = count;
1259
1260 r300->textures_state.dirty = TRUE;
1261 }
1262
1263 static void r300_lacks_vertex_textures(struct pipe_context* pipe,
1264 unsigned count,
1265 void** states)
1266 {
1267 }
1268
1269 static void r300_delete_sampler_state(struct pipe_context* pipe, void* state)
1270 {
1271 FREE(state);
1272 }
1273
1274 static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num)
1275 {
1276 /* This looks like a hack, but I believe it's suppose to work like
1277 * that. To illustrate how this works, let's assume you have 5 textures.
1278 * From docs, 5 and the successive numbers are:
1279 *
1280 * FOURTH_1 = 5
1281 * FOURTH_2 = 6
1282 * FOURTH_3 = 7
1283 * EIGHTH_0 = 8
1284 * EIGHTH_1 = 9
1285 *
1286 * First 3 textures will get 3/4 of size of the cache, divived evenly
1287 * between them. The last 1/4 of the cache must be divided between
1288 * the last 2 textures, each will therefore get 1/8 of the cache.
1289 * Why not just to use "5 + texture_index" ?
1290 *
1291 * This simple trick works for all "num" <= 16.
1292 */
1293 if (num <= 1)
1294 return R300_TX_CACHE(R300_TX_CACHE_WHOLE);
1295 else
1296 return R300_TX_CACHE(num + index);
1297 }
1298
1299 static void r300_set_fragment_sampler_views(struct pipe_context* pipe,
1300 unsigned count,
1301 struct pipe_sampler_view** views)
1302 {
1303 struct r300_context* r300 = r300_context(pipe);
1304 struct r300_textures_state* state =
1305 (struct r300_textures_state*)r300->textures_state.state;
1306 struct r300_texture *texture;
1307 unsigned i, real_num_views = 0, view_index = 0;
1308 unsigned tex_units = r300->screen->caps.num_tex_units;
1309 boolean dirty_tex = FALSE;
1310
1311 if (count > tex_units) {
1312 return;
1313 }
1314
1315 /* Calculate the real number of views. */
1316 for (i = 0; i < count; i++) {
1317 if (views[i])
1318 real_num_views++;
1319 }
1320
1321 for (i = 0; i < count; i++) {
1322 if (&state->sampler_views[i]->base != views[i]) {
1323 pipe_sampler_view_reference(
1324 (struct pipe_sampler_view**)&state->sampler_views[i],
1325 views[i]);
1326
1327 if (!views[i]) {
1328 continue;
1329 }
1330
1331 /* A new sampler view (= texture)... */
1332 dirty_tex = TRUE;
1333
1334 /* Set the texrect factor in the fragment shader.
1335 * Needed for RECT and NPOT fallback. */
1336 texture = r300_texture(views[i]->texture);
1337 if (texture->desc.is_npot) {
1338 r300->fs_rc_constant_state.dirty = TRUE;
1339 }
1340
1341 state->sampler_views[i]->texcache_region =
1342 r300_assign_texture_cache_region(view_index, real_num_views);
1343 view_index++;
1344 }
1345 }
1346
1347 for (i = count; i < tex_units; i++) {
1348 if (state->sampler_views[i]) {
1349 pipe_sampler_view_reference(
1350 (struct pipe_sampler_view**)&state->sampler_views[i],
1351 NULL);
1352 }
1353 }
1354
1355 state->sampler_view_count = count;
1356
1357 r300->textures_state.dirty = TRUE;
1358
1359 if (dirty_tex) {
1360 r300->texture_cache_inval.dirty = TRUE;
1361 }
1362 }
1363
1364 static struct pipe_sampler_view *
1365 r300_create_sampler_view(struct pipe_context *pipe,
1366 struct pipe_resource *texture,
1367 const struct pipe_sampler_view *templ)
1368 {
1369 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view);
1370 struct r300_texture *tex = r300_texture(texture);
1371 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500;
1372
1373 if (view) {
1374 view->base = *templ;
1375 view->base.reference.count = 1;
1376 view->base.context = pipe;
1377 view->base.texture = NULL;
1378 pipe_resource_reference(&view->base.texture, texture);
1379
1380 view->swizzle[0] = templ->swizzle_r;
1381 view->swizzle[1] = templ->swizzle_g;
1382 view->swizzle[2] = templ->swizzle_b;
1383 view->swizzle[3] = templ->swizzle_a;
1384
1385 view->format = tex->tx_format;
1386 view->format.format1 |= r300_translate_texformat(templ->format,
1387 view->swizzle,
1388 is_r500);
1389 if (is_r500) {
1390 view->format.format2 |= r500_tx_format_msb_bit(templ->format);
1391 }
1392 }
1393
1394 return (struct pipe_sampler_view*)view;
1395 }
1396
1397 static void
1398 r300_sampler_view_destroy(struct pipe_context *pipe,
1399 struct pipe_sampler_view *view)
1400 {
1401 pipe_resource_reference(&view->texture, NULL);
1402 FREE(view);
1403 }
1404
1405 static void r300_set_scissor_state(struct pipe_context* pipe,
1406 const struct pipe_scissor_state* state)
1407 {
1408 struct r300_context* r300 = r300_context(pipe);
1409
1410 memcpy(r300->scissor_state.state, state,
1411 sizeof(struct pipe_scissor_state));
1412
1413 r300->scissor_state.dirty = TRUE;
1414 }
1415
1416 static void r300_set_viewport_state(struct pipe_context* pipe,
1417 const struct pipe_viewport_state* state)
1418 {
1419 struct r300_context* r300 = r300_context(pipe);
1420 struct r300_viewport_state* viewport =
1421 (struct r300_viewport_state*)r300->viewport_state.state;
1422
1423 r300->viewport = *state;
1424
1425 if (r300->draw) {
1426 draw_set_viewport_state(r300->draw, state);
1427 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT;
1428 return;
1429 }
1430
1431 /* Do the transform in HW. */
1432 viewport->vte_control = R300_VTX_W0_FMT;
1433
1434 if (state->scale[0] != 1.0f) {
1435 viewport->xscale = state->scale[0];
1436 viewport->vte_control |= R300_VPORT_X_SCALE_ENA;
1437 }
1438 if (state->scale[1] != 1.0f) {
1439 viewport->yscale = state->scale[1];
1440 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA;
1441 }
1442 if (state->scale[2] != 1.0f) {
1443 viewport->zscale = state->scale[2];
1444 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA;
1445 }
1446 if (state->translate[0] != 0.0f) {
1447 viewport->xoffset = state->translate[0];
1448 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA;
1449 }
1450 if (state->translate[1] != 0.0f) {
1451 viewport->yoffset = state->translate[1];
1452 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA;
1453 }
1454 if (state->translate[2] != 0.0f) {
1455 viewport->zoffset = state->translate[2];
1456 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA;
1457 }
1458
1459 r300->viewport_state.dirty = TRUE;
1460 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) {
1461 r300->fs_rc_constant_state.dirty = TRUE;
1462 }
1463 }
1464
1465 static void r300_set_vertex_buffers(struct pipe_context* pipe,
1466 unsigned count,
1467 const struct pipe_vertex_buffer* buffers)
1468 {
1469 struct r300_context* r300 = r300_context(pipe);
1470 struct pipe_vertex_buffer *vbo;
1471 unsigned i, max_index = (1 << 24) - 1;
1472 boolean any_user_buffer = FALSE;
1473
1474 if (count == r300->vertex_buffer_count &&
1475 memcmp(r300->vertex_buffer, buffers,
1476 sizeof(struct pipe_vertex_buffer) * count) == 0) {
1477 return;
1478 }
1479
1480 if (r300->screen->caps.has_tcl) {
1481 /* HW TCL. */
1482 r300->incompatible_vb_layout = FALSE;
1483
1484 /* Check if the strides and offsets are aligned to the size of DWORD. */
1485 for (i = 0; i < count; i++) {
1486 if (buffers[i].buffer) {
1487 if (buffers[i].stride % 4 != 0 ||
1488 buffers[i].buffer_offset % 4 != 0) {
1489 r300->incompatible_vb_layout = TRUE;
1490 break;
1491 }
1492 }
1493 }
1494
1495 for (i = 0; i < count; i++) {
1496 /* Why, yes, I AM casting away constness. How did you know? */
1497 vbo = (struct pipe_vertex_buffer*)&buffers[i];
1498
1499 /* Skip NULL buffers */
1500 if (!buffers[i].buffer) {
1501 continue;
1502 }
1503
1504 if (r300_buffer_is_user_buffer(vbo->buffer)) {
1505 any_user_buffer = TRUE;
1506 }
1507
1508 if (vbo->max_index == ~0) {
1509 /* if no VBO stride then only one vertex value so max index is 1 */
1510 /* should think about converting to VS constants like svga does */
1511 if (!vbo->stride)
1512 vbo->max_index = 1;
1513 else
1514 vbo->max_index =
1515 (vbo->buffer->width0 - vbo->buffer_offset) / vbo->stride;
1516 }
1517
1518 max_index = MIN2(vbo->max_index, max_index);
1519 }
1520
1521 r300->any_user_vbs = any_user_buffer;
1522 r300->vertex_buffer_max_index = max_index;
1523
1524 } else {
1525 /* SW TCL. */
1526 draw_set_vertex_buffers(r300->draw, count, buffers);
1527 }
1528
1529 /* Common code. */
1530 for (i = 0; i < count; i++) {
1531 /* Reference our buffer. */
1532 pipe_resource_reference(&r300->vertex_buffer[i].buffer, buffers[i].buffer);
1533 }
1534 for (; i < r300->vertex_buffer_count; i++) {
1535 /* Dereference any old buffers. */
1536 pipe_resource_reference(&r300->vertex_buffer[i].buffer, NULL);
1537 }
1538
1539 memcpy(r300->vertex_buffer, buffers,
1540 sizeof(struct pipe_vertex_buffer) * count);
1541 r300->vertex_buffer_count = count;
1542 }
1543
1544 static void r300_set_index_buffer(struct pipe_context* pipe,
1545 const struct pipe_index_buffer *ib)
1546 {
1547 struct r300_context* r300 = r300_context(pipe);
1548
1549 if (ib) {
1550 pipe_resource_reference(&r300->index_buffer.buffer, ib->buffer);
1551 memcpy(&r300->index_buffer, ib, sizeof(r300->index_buffer));
1552 }
1553 else {
1554 pipe_resource_reference(&r300->index_buffer.buffer, NULL);
1555 memset(&r300->index_buffer, 0, sizeof(r300->index_buffer));
1556 }
1557
1558 /* TODO make this more like a state */
1559 }
1560
1561 /* Initialize the PSC tables. */
1562 static void r300_vertex_psc(struct r300_vertex_element_state *velems)
1563 {
1564 struct r300_vertex_stream_state *vstream = &velems->vertex_stream;
1565 uint16_t type, swizzle;
1566 enum pipe_format format;
1567 unsigned i;
1568
1569 if (velems->count > 16) {
1570 fprintf(stderr, "r300: More than 16 vertex elements are not supported,"
1571 " requested %i, using 16.\n", velems->count);
1572 velems->count = 16;
1573 }
1574
1575 /* Vertex shaders have no semantics on their inputs,
1576 * so PSC should just route stuff based on the vertex elements,
1577 * and not on attrib information. */
1578 for (i = 0; i < velems->count; i++) {
1579 format = velems->hw_format[i];
1580
1581 type = r300_translate_vertex_data_type(format);
1582 if (type == R300_INVALID_FORMAT) {
1583 fprintf(stderr, "r300: Bad vertex format %s.\n",
1584 util_format_short_name(format));
1585 assert(0);
1586 abort();
1587 }
1588
1589 type |= i << R300_DST_VEC_LOC_SHIFT;
1590 swizzle = r300_translate_vertex_data_swizzle(format);
1591
1592 if (i & 1) {
1593 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16;
1594 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16;
1595 } else {
1596 vstream->vap_prog_stream_cntl[i >> 1] |= type;
1597 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle;
1598 }
1599 }
1600
1601 /* Set the last vector in the PSC. */
1602 if (i) {
1603 i -= 1;
1604 }
1605 vstream->vap_prog_stream_cntl[i >> 1] |=
1606 (R300_LAST_VEC << (i & 1 ? 16 : 0));
1607
1608 vstream->count = (i >> 1) + 1;
1609 }
1610
1611 #define FORMAT_REPLACE(what, withwhat) \
1612 case PIPE_FORMAT_##what: *format = PIPE_FORMAT_##withwhat; break
1613
1614 static void* r300_create_vertex_elements_state(struct pipe_context* pipe,
1615 unsigned count,
1616 const struct pipe_vertex_element* attribs)
1617 {
1618 struct r300_vertex_element_state *velems;
1619 unsigned i;
1620 enum pipe_format *format;
1621
1622 assert(count <= PIPE_MAX_ATTRIBS);
1623 velems = CALLOC_STRUCT(r300_vertex_element_state);
1624 if (velems != NULL) {
1625 velems->count = count;
1626 memcpy(velems->velem, attribs, sizeof(struct pipe_vertex_element) * count);
1627
1628 if (r300_screen(pipe->screen)->caps.has_tcl) {
1629 /* Set the best hw format in case the original format is not
1630 * supported by hw. */
1631 for (i = 0; i < count; i++) {
1632 velems->hw_format[i] = velems->velem[i].src_format;
1633 format = &velems->hw_format[i];
1634
1635 /* This is basically the list of unsupported formats.
1636 * For now we don't care about the alignment, that's going to
1637 * be sorted out after the PSC setup. */
1638 switch (*format) {
1639 FORMAT_REPLACE(R64_FLOAT, R32_FLOAT);
1640 FORMAT_REPLACE(R64G64_FLOAT, R32G32_FLOAT);
1641 FORMAT_REPLACE(R64G64B64_FLOAT, R32G32B32_FLOAT);
1642 FORMAT_REPLACE(R64G64B64A64_FLOAT, R32G32B32A32_FLOAT);
1643
1644 FORMAT_REPLACE(R32_UNORM, R32_FLOAT);
1645 FORMAT_REPLACE(R32G32_UNORM, R32G32_FLOAT);
1646 FORMAT_REPLACE(R32G32B32_UNORM, R32G32B32_FLOAT);
1647 FORMAT_REPLACE(R32G32B32A32_UNORM, R32G32B32A32_FLOAT);
1648
1649 FORMAT_REPLACE(R32_USCALED, R32_FLOAT);
1650 FORMAT_REPLACE(R32G32_USCALED, R32G32_FLOAT);
1651 FORMAT_REPLACE(R32G32B32_USCALED, R32G32B32_FLOAT);
1652 FORMAT_REPLACE(R32G32B32A32_USCALED,R32G32B32A32_FLOAT);
1653
1654 FORMAT_REPLACE(R32_SNORM, R32_FLOAT);
1655 FORMAT_REPLACE(R32G32_SNORM, R32G32_FLOAT);
1656 FORMAT_REPLACE(R32G32B32_SNORM, R32G32B32_FLOAT);
1657 FORMAT_REPLACE(R32G32B32A32_SNORM, R32G32B32A32_FLOAT);
1658
1659 FORMAT_REPLACE(R32_SSCALED, R32_FLOAT);
1660 FORMAT_REPLACE(R32G32_SSCALED, R32G32_FLOAT);
1661 FORMAT_REPLACE(R32G32B32_SSCALED, R32G32B32_FLOAT);
1662 FORMAT_REPLACE(R32G32B32A32_SSCALED,R32G32B32A32_FLOAT);
1663
1664 FORMAT_REPLACE(R32_FIXED, R32_FLOAT);
1665 FORMAT_REPLACE(R32G32_FIXED, R32G32_FLOAT);
1666 FORMAT_REPLACE(R32G32B32_FIXED, R32G32B32_FLOAT);
1667 FORMAT_REPLACE(R32G32B32A32_FIXED, R32G32B32A32_FLOAT);
1668
1669 default:;
1670 }
1671
1672 velems->incompatible_layout =
1673 velems->incompatible_layout ||
1674 velems->velem[i].src_format != velems->hw_format[i] ||
1675 velems->velem[i].src_offset % 4 != 0;
1676 }
1677
1678 /* Now setup PSC.
1679 * The unused components will be replaced by (..., 0, 1). */
1680 r300_vertex_psc(velems);
1681
1682 /* Align the formats to the size of DWORD.
1683 * We only care about the blocksizes of the formats since
1684 * swizzles are already set up.
1685 * Also compute the vertex size. */
1686 for (i = 0; i < count; i++) {
1687 /* This is OK because we check for aligned strides too. */
1688 velems->hw_format_size[i] =
1689 align(util_format_get_blocksize(velems->hw_format[i]), 4);
1690 velems->vertex_size_dwords += velems->hw_format_size[i] / 4;
1691 }
1692 }
1693 }
1694 return velems;
1695 }
1696
1697 static void r300_bind_vertex_elements_state(struct pipe_context *pipe,
1698 void *state)
1699 {
1700 struct r300_context *r300 = r300_context(pipe);
1701 struct r300_vertex_element_state *velems = state;
1702
1703 if (velems == NULL) {
1704 return;
1705 }
1706
1707 r300->velems = velems;
1708
1709 if (r300->draw) {
1710 draw_set_vertex_elements(r300->draw, velems->count, velems->velem);
1711 return;
1712 }
1713
1714 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state);
1715 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2;
1716 }
1717
1718 static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state)
1719 {
1720 FREE(state);
1721 }
1722
1723 static void* r300_create_vs_state(struct pipe_context* pipe,
1724 const struct pipe_shader_state* shader)
1725 {
1726 struct r300_context* r300 = r300_context(pipe);
1727 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader);
1728
1729 /* Copy state directly into shader. */
1730 vs->state = *shader;
1731 vs->state.tokens = tgsi_dup_tokens(shader->tokens);
1732
1733 if (r300->screen->caps.has_tcl) {
1734 r300_init_vs_outputs(vs);
1735 r300_translate_vertex_shader(r300, vs);
1736 } else {
1737 r300_draw_init_vertex_shader(r300->draw, vs);
1738 }
1739
1740 return vs;
1741 }
1742
1743 static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
1744 {
1745 struct r300_context* r300 = r300_context(pipe);
1746 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1747
1748 if (vs == NULL) {
1749 r300->vs_state.state = NULL;
1750 return;
1751 }
1752 if (vs == r300->vs_state.state) {
1753 return;
1754 }
1755 r300->vs_state.state = vs;
1756
1757 /* The majority of the RS block bits is dependent on the vertex shader. */
1758 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */
1759
1760 if (r300->screen->caps.has_tcl) {
1761 unsigned fc_op_dwords = r300->screen->caps.is_r500 ? 3 : 2;
1762 r300->vs_state.dirty = TRUE;
1763 r300->vs_state.size =
1764 vs->code.length + 9 +
1765 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0) +
1766 (vs->code.num_fc_ops ? vs->code.num_fc_ops * fc_op_dwords + 4 : 0);
1767
1768 if (vs->externals_count) {
1769 r300->vs_constants.dirty = TRUE;
1770 r300->vs_constants.size = vs->externals_count * 4 + 3;
1771 } else {
1772 r300->vs_constants.size = 0;
1773 }
1774
1775 r300->pvs_flush.dirty = TRUE;
1776 } else {
1777 draw_bind_vertex_shader(r300->draw,
1778 (struct draw_vertex_shader*)vs->draw_vs);
1779 }
1780 }
1781
1782 static void r300_delete_vs_state(struct pipe_context* pipe, void* shader)
1783 {
1784 struct r300_context* r300 = r300_context(pipe);
1785 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1786
1787 if (r300->screen->caps.has_tcl) {
1788 rc_constants_destroy(&vs->code.constants);
1789 } else {
1790 draw_delete_vertex_shader(r300->draw,
1791 (struct draw_vertex_shader*)vs->draw_vs);
1792 }
1793
1794 FREE((void*)vs->state.tokens);
1795 FREE(shader);
1796 }
1797
1798 static void r300_set_constant_buffer(struct pipe_context *pipe,
1799 uint shader, uint index,
1800 struct pipe_resource *buf)
1801 {
1802 struct r300_context* r300 = r300_context(pipe);
1803 struct r300_constant_buffer *cbuf;
1804 uint32_t *mapped = r300_buffer(buf)->user_buffer;
1805 int max_size = 0, max_size_bytes = 0, clamped_size = 0;
1806
1807 switch (shader) {
1808 case PIPE_SHADER_VERTEX:
1809 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state;
1810 max_size = 256;
1811 break;
1812 case PIPE_SHADER_FRAGMENT:
1813 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state;
1814 if (r300->screen->caps.is_r500) {
1815 max_size = 256;
1816 } else {
1817 max_size = 32;
1818 }
1819 break;
1820 default:
1821 assert(0);
1822 return;
1823 }
1824 max_size_bytes = max_size * 4 * sizeof(float);
1825
1826 if (buf == NULL || buf->width0 == 0 ||
1827 (mapped = r300_buffer(buf)->constant_buffer) == NULL) {
1828 cbuf->count = 0;
1829 return;
1830 }
1831
1832 if (shader == PIPE_SHADER_FRAGMENT ||
1833 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) {
1834 assert((buf->width0 % (4 * sizeof(float))) == 0);
1835
1836 /* Check the size of the constant buffer. */
1837 /* XXX Subtract immediates and RC_STATE_* variables. */
1838 if (buf->width0 > max_size_bytes) {
1839 fprintf(stderr, "r300: Max size of the constant buffer is "
1840 "%i*4 floats.\n", max_size);
1841 }
1842
1843 clamped_size = MIN2(buf->width0, max_size_bytes);
1844 cbuf->count = clamped_size / (4 * sizeof(float));
1845 cbuf->ptr = mapped;
1846 }
1847
1848 if (shader == PIPE_SHADER_VERTEX) {
1849 if (r300->screen->caps.has_tcl) {
1850 if (r300->vs_constants.size) {
1851 r300->vs_constants.dirty = TRUE;
1852 }
1853 r300->pvs_flush.dirty = TRUE;
1854 } else if (r300->draw) {
1855 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX,
1856 0, mapped, buf->width0);
1857 }
1858 } else if (shader == PIPE_SHADER_FRAGMENT) {
1859 r300->fs_constants.dirty = TRUE;
1860 }
1861 }
1862
1863 void r300_init_state_functions(struct r300_context* r300)
1864 {
1865 r300->context.create_blend_state = r300_create_blend_state;
1866 r300->context.bind_blend_state = r300_bind_blend_state;
1867 r300->context.delete_blend_state = r300_delete_blend_state;
1868
1869 r300->context.set_blend_color = r300_set_blend_color;
1870
1871 r300->context.set_clip_state = r300_set_clip_state;
1872 r300->context.set_sample_mask = r300_set_sample_mask;
1873
1874 r300->context.set_constant_buffer = r300_set_constant_buffer;
1875
1876 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state;
1877 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
1878 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
1879
1880 r300->context.set_stencil_ref = r300_set_stencil_ref;
1881
1882 r300->context.set_framebuffer_state = r300_set_framebuffer_state;
1883
1884 r300->context.create_fs_state = r300_create_fs_state;
1885 r300->context.bind_fs_state = r300_bind_fs_state;
1886 r300->context.delete_fs_state = r300_delete_fs_state;
1887
1888 r300->context.set_polygon_stipple = r300_set_polygon_stipple;
1889
1890 r300->context.create_rasterizer_state = r300_create_rs_state;
1891 r300->context.bind_rasterizer_state = r300_bind_rs_state;
1892 r300->context.delete_rasterizer_state = r300_delete_rs_state;
1893
1894 r300->context.create_sampler_state = r300_create_sampler_state;
1895 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states;
1896 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures;
1897 r300->context.delete_sampler_state = r300_delete_sampler_state;
1898
1899 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views;
1900 r300->context.create_sampler_view = r300_create_sampler_view;
1901 r300->context.sampler_view_destroy = r300_sampler_view_destroy;
1902
1903 r300->context.set_scissor_state = r300_set_scissor_state;
1904
1905 r300->context.set_viewport_state = r300_set_viewport_state;
1906
1907 r300->context.set_vertex_buffers = r300_set_vertex_buffers;
1908 r300->context.set_index_buffer = r300_set_index_buffer;
1909
1910 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state;
1911 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state;
1912 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state;
1913
1914 r300->context.create_vs_state = r300_create_vs_state;
1915 r300->context.bind_vs_state = r300_bind_vs_state;
1916 r300->context.delete_vs_state = r300_delete_vs_state;
1917 }